Dell Precision M4700 LA-7931P Rev 10 (A00) Schematics

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MODEL NAME : QAR00
PCB NO : LA-7931P ( DAA00002T00 )
BOM P/N : 4319FN31L01
1
4319FN31L02
Compal Confidential 1
Vans 15
rPGA Ivy Bridge + FCBGA PCH Panther Point + MXMⅢ type A x1
Rev: 1.0 (A00)
2
2012.06.07 2
@ : Nopop component
CONN@ : ME connector
5@ : 6-bit LCD panel
6@ : 10-bit LCD panel
1@, 2@, 3@, 4@ : for TPM / TCM
3
PXDP@,JTAG@ : Total debug connector (pop them until ST) 3
MB Type BOM P/N Include 6‐bit MB Type BOM P/N Include 10‐bit
TPM 4319FN31L01 1@ 3@ 5@ PXDP@ TPM 4319FN31L02 1@ 3@ 6@ PXDP@

JTAG@ JTAG@
SATA Re‐driver USB3 Re‐driver
Source X76 P/N Page Source X76 P/N Page ROM part Source X76 P/N Page
(U26,U637) (U638)
PS8520B PS8720B U52 (SA000039A2L)
main source X7641231L01 main source X7641231L03 main (Winbond) X7640631L01
(SA00004WF00) (SA00004UI00) U53 (SA00003K80L)
35,43 40 17
MAX4951C PS8720A U52 (SA000046400)
4 2nd source X7641231L02 2nd source X7641231L04 2nd (EON) X7640631L03 4
(SA00002EY1L) (SA00005PO00) U53 (SA00004LI00)

DELL CONFIDENTIAL/PROPRIETARY
MB PCB
Part Compal Electronics, Inc.
Description PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Number Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
DAA00002T00 PCB 0FE LA‐7931P REV0 M/B DIS BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Cover Sheet
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
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power CKT: 05/17 PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7931P
Date: Monday, July 23, 2012 Sheet 1 of 70
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& LVDS 6‐bit
& LVDS 10‐bit Intel (DDRIII)
Ivy Bridge Memory Bus 204pin DDRIII SO‐DIMM x4
eDP to LVDS Processorr Dual Channel P.12~P.15
(STDP4010) (10-bit panel output) PEG x16 (DIS) PGA 989 Socket 1.5V DDRIII OC : 1866 MHz
1 P.30~P.31 35W Dual Core 1333 /1600 MHz 1
LVDS MUX 45W Quad Core
LVDS Panel (TS3DV20812) 55W QC Extreme Edition SATA Port 0
SATA 3.0 Repeater
DP 1st HDD Conn.
Conn P.28 P.27 LVDS (DIS) DP_D P.6~P.11 (PS8520B) P.35 P.35
LVDS
DP Redriver LVDS
DP 1.2
(PS8330B) DP (DIS)
Conn P.29 DP_A FDI x8
DMI x4 gen 2
SATA Port 3 ODD Conn.
P.29 MXM Conn. P.36
(10-bit panel output)

TYPE A
CRT SW CRT SATA Port 4
CRT Conn SATA3.0 USB / eSATA Conn.
P.32 (MAX14885)
DP_C P.39
USB2.0 port 0
P.32
Docking CRT USB Port 9
DP_B
P.16 SATA2.0 USB 3.0 Repeater USB 3.0 Conn Right Side
HDMI 1.4a DP/HDMI DeMUX
DP (DIS)
Conn P.34 (PS8336B) LVDS LVDS Intel
USB Port 0 (PS8710B) P.40 USB Charger P.40
P.34
CRT CRT Panther Point USB Port 1 USB 3.0 Repeater
Docking DP1 USB3.0 USB 3.0 Conn Right Side
2 PCH (PS8710B) P.40 P.40 2
DP(DIS) BGA 989 Balls USB Port 2

Docking DP2
USB 2.0 Conn Left Side
USB Port 6 USB2.0 port 1
USB 2.0 Conn Left Side
PCIE BUS On IO board
USB2.0 USB Port 11
Port 8 Port 3 Port 7 Port 5 SATA Port 2 Port 6 Port 2 BT 4.0+LE P.49
IEEE1394 Intel Lewisville Mini Card‐3 Mini Card‐1 USB Port 12
Digital Camera P.28 through LVDS Cable
+ Express Card (82579LM) PP PCIE/SATA MUX WLAN/WiGi
P.37 (PI2DBS212)
Card reader P.42 P.43 P.42 HD Audio USB Port 13 Touch screen P.28
USB Port 10 USB Port 4
LAN switch P.17~P.24
(PI3L720)
1394 SDXC P.37 RFID
On IO board Mini Card‐2 China TCM1.2
Docking LAN
WWAN/GPS SSX44B P.41 W25X64ZE BRCM5882
P.17 USB Port 7 TDA8034HN
mSATA 8MB TPM 1.2
SPI
RJ45 P.43
Discrete TPM
P.38
3
USB Port 5 AT97SC3204 W25Q32BV 3
P.41 P.17 Smart Card

4MB
SMSC SIO
LPC BUS
ECE5048 BC BUS FP_USB Fingerprint
P.47 On USH Board CONN
SMSC KBC
Docking LPC MEC5055
HeadPhone Jack
P.48
SATA Port 5
Audio Codec
SIM Card 92HD93 Array MIC Jack
P.43
USB 2.0 Port 8
KB CONN
Free Fall Sensor Docking DAI
TP CONN P.49
(LNG3DMTR) Int. Speaker Speaker module
P.35 On IO board
Docking CRT On IO board
Current Monitor Docking LAN

(EMC1701) E‐Dock DC‐IN
4
P.53 4
P.26 USB3.0 Port 3

Thermal Docking LPC
GUARDIAN III DELL CONFIDENTIAL/PROPRIETARY
Docking DP1
EMC4002 P.25 Compal Electronics, Inc.
Title
Docking DP2 P.45 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Block Diagram
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
A B WWW.AliSaler.Com C
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
D
Date: Monday, July 23, 2012
LA-7931P
E
Sheet 2 of 70
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POWER STATES
USB PORT# DESTINATION
Signal SLP SLP SLP S4 SLP ALWAYS M SUS RUN CLOCKS
State S3# S4# S5# STATE# M# PLANE PLANE PLANE PLANE
0 JUSB1 (Ext Right Side) USB3.0
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH HIGH ON ON ON ON ON
1 JUSB2 (Ext Right Side) USB3.0
D
S3 (Suspend to RAM) / M1 LOW HIGH HIGH HIGH HIGH ON ON ON OFF OFF D
2 IO Board- JUSB1 (Ext Left Side)
S4 (Suspend to DISK) / M1 LOW LOW HIGH LOW HIGH ON ON OFF OFF OFF
3 Docking USB3.0
S5 (SOFT OFF) / M1 LOW LOW LOW LOW HIGH ON ON OFF OFF OFF
4 Docking USB 2.0
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH HIGH LOW ON OFF ON OFF OFF
5 WWAN
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW LOW ON OFF OFF OFF OFF PCH
6 IO Board- JUSB2 (Ext Left Side)
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW LOW ON OFF OFF OFF OFF
7 USH
PM TABLE 8 WLAN
+15V_ALW +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M
+5V_ALW +1.5V_MEM +3.3V_RUN +1.05V_M +1.05V_M SATA DESTINATION 9 ESATA
C
+3.3V_ALW_PCH +1.8V_RUN (M-OFF) C
power SATA 0 HDD 1 Express Card
plane +3.3V_RTC_LDO +1.5V_RUN 10
+0.75V_DDR_VTT
+VCC_CORE SATA 1 NA 11 BT 4.0
+1.05V_RUN_VTT
+1.05V_RUN SATA 2 mSATA 12 Carmera
State
SATA 3 ODD 13 Touch Screen

S0 ON ON ON ON ON
SATA 4 ESATA
0 BIO
S3 ON ON OFF ON OFF
SATA 5 Dock USH
1 NA
S5 S4/AC ON OFF OFF ON OFF
S5 S4/AC don't exist OFF OFF OFF OFF OFF
B
PCI EXPRESS DESTINATION B
Stack up
Lane 1 NA
Lane 2 MINI CARD-1 WLAN/DMC

Lane 3 Express Card
Lane 4 NA
Lane 5 MINI CARD-3 (Pink Panther)
Lane 6 MINI CARD-2 WWAN/mSATA/GPS
Lane 7 10/100/1G LOM
A
Lane 8 Cardreader A
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Index and Config.
WWW.AliSaler.Com LA-7931P
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
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PWR_SHARE_EN#
MODC_EN
SIO_SLP_S3#
ESATA_USB_PWR_EN#
EN_INVPWR FDC654P
DOCK +BL_PWR_SRC
(Q21)
TPS2560
(U48)
D TPS2560 SI3456DDV SI3456DDV D
RUN_GFX_ON SI4835DDY (U45) (Q27) (Q30)

+MXM_PWR_SRC
(Q186) Pop option
ADAPTER
+5V_ESATA_PWR
PCH_ALW_ON +5V_USB_PWR1 +5V_HDD +5V_MOD

TP0610K
+PWR_SRC_S +5V_USB_PWR2 +5V_ALW_PCH
(PQ4)
+PWR_SRC
BATTERY
+5V_RUN +5V_MXM
ALW_ON_3.3V#
SSM3K7002FU
ALWON (QH4)
RUN_GFX_ON SI4800BDY
SIO_SLP_S3# RT8205 (Q76)
SI3456DDV
CHARGER +LCDVDD SY8033 (PU101) +5V_ALW
C (Q18) +1.8V_RUN C
(PU4) +5V_RUN_ENABLE
MXM_ENVDD
ENVDD_PCH
EN_LCDPWR
LCD_VCC_TEST_EN
+3.3V_ALW DMN3030LSS
MCARD_WWAN_PWREN
(Q329)
MCARD_MISC_PWREN
1.05V_VTTPWRGD
NVRAM_PWR_EN
PCH_ALW_ON
RUN_GFX_ON
SIO_SLP_LAN#
SIO_SLP_A#
SIO_SLP_A#
CPU_VTT_ON
SIO_SLP_S3#
+5V_RUN
SYSON
SUS_ON
1.05V_0.8V_PWROK
RT8207 TPS51212 TPS51212

TPS51461 SI3456DDV SI3456DDV SI3456DDV SI3456DDV SI3456DDV SI3456DDV SLG59M232VTR SI3456DDV SI3456DDV
(PU151) (PU5) (PU6)
(PU7) (Q46) (Q40) (Q44) (Q49) (Q54) (Q34) (U78) (Q58) (Q25)
B B
+1.5V_MEM +1.05V_M +1.05V_RUN_VTT

+VCC_SA +3.3V_PCIE_WWAN +3.3V_SUS +3.3V_LAN +3.3V_RUN +3.3V_M +3V_MXM
SIO_SLP_S3#
CCD_OFF
+3.3V_PCIE_NVM +3.3V_PCIE_FLASH +3.3V_ALW_PCH Pop option
ISL95836
SI4164 (PU702)
+3.3V_M LDO of 82579
(Q63)
(U31) PMV65XP
(Q24)
+VCC_CORE +VCC_GFXCORE Pop option
+1.05V_RUN
+1.05V_M +1.0V_LAN
SUSP#
SIO_SLP_S3# SIO_SLP_S3#
+CAMERA_VDD
A A
+0.75V_DDR_VTT AO4728L NTGS4141

(QC3) (Q59) DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Rail
+1.5V_CPU_VDDQ +1.5V_RUN +VCCAFDI_VRM
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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7931P
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SMBUS Address [0x9a]
2.2K
2.2K
+3.3V_ALW_PCH
H14 MEM_SMBCLK 202
2N7002 SMBUS Address [A0h]
C9 MEM_SMBDATA 200 DIMM1 A0h --> 1010 0000
2N7002
2.2K 202
SMBUS Address [A4h]
D PCH 200 DIMM2 A4h --> 1010 0100
D
2.2K
+3.3V_LAN
202
C8 28 SMBUS Address [A4h]
LAN_SMBCLK DIMM3
31
200 A4h --> 1010 0100
G12 LAN_SMBDATA LOM SMBUS Address [C8]
M16 E14 202
2.2K 200 DIMM4

SML1_SMBDATA
SML1_SMBCLK
+3.3V_ALW_PCH 53
2.2K
51 XDP2
A5 B6
SMBUS Address [TBD]
2.2K
10K
3A 3A
2.2K +3.3V_ALW SMBUS Address +3.3V_RUN
10K
APR_EC: 0x48
DOCK_SMB_CLK 127
1A B4 SPR_EC: 0x70 14
129 DOCKING MSLICE_EC: 0x72 G Sensor
1A A3 DOCK_SMB_DAT 13 SMBUS Address [TBD]
USB: 0x59
AUDIO: 0x34
SLICE_BATTERY: 0x17
2.2K 30
SLICE_CHARGER: 0x13
32 WWAN
C +3.3V_ALW SMBUS Address [TBD] C
2.2K
U5
1B B5 LCD_SMBCLK 1
1B A4 LCD_SMBDAT 10 Current Monitor
2.2K SMBUS Address

U6 SMB_ADM1032: 0x98
1
SMB_DIAG_DUMP: 0x04
KBC 2.2K
+3.3V_ALW 10 Current Monitor SMB_DIAG_DUMP2: 0x05
100 ohm SMB_BLACKTOP: 0x60
1C A56 PBAT_SMBCLK 7
BATTERY 12
1C B59 PBAT_SMBDAT 100 ohm 6
CONN
2.2K SMBUS Address [0x16]
14 JLVDS3
+3.3V_SUS
2.2K
A50
1E USH_SMBCLK M9
B53
1E USH_SMBDAT L9 USH SMBUS Address [0xa4]
2.2K
B B
+3.3V_SUS
2.2K
MEC 5055
2B A49 CARD_SMBCLK 7
Express card SMBUS Address [TBD]
2B B52 CARD_SMBDAT 8
2.2K
+3.3V_ALW
2.2K
1G B50 CHARGER_SMBCLK 10
A47 CHARGER_SMBDAT 9 Charger
1G SMBUS Address [0x12]
2.2K
+3.3V_ALW
2.2K
B7 BAY_SMBDAT
2D
A7 BAY_SMBCLK
2D
4.7K
+3.3V_RUN
A 4.7K A
B49
2A GPU_SMBCLK 70
B48 2N7002
2A GPU_SMBDAT 68 MXM SMBUS Address [0x30]
2N7002

Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SMBUS Bolck Diagram
5 4
WWW.AliSaler.Com BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
3 2
Size
Date:
Document Number
LA-7931P
Monday, July 23, 2012
1
Sheet 5 of 70
Rev
1.0
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PEG_CRX_GTX_C_P[0..15]
PEG_CRX_GTX_C_P[0..15] <16>
PEG_CRX_GTX_C_N[0..15]
PEG_CRX_GTX_C_N[0..15] <16>
PEG_CTX_GRX_P[0..15]
JCPU1A CONN@ PEG_CTX_GRX_P[0..15] <16> JCPU1I CONN@
J22 PEG_COMP PEG_CTX_GRX_N[0..15]
D PEG_ICOMPI J21 PEG_CTX_GRX_N[0..15] <16> D
DMI_CRX_PTX_N0 B27 PEG_ICOMPO H22
<19> DMI_CRX_PTX_N0 DMI_RX#[0] PEG_RCOMPO
DMI_CRX_PTX_N1 B25 T35 F22
<19> DMI_CRX_PTX_N1 DMI_RX#[1] VSS161 VSS234
DMI_CRX_PTX_N2 A25 T34 F19
<19> DMI_CRX_PTX_N2 DMI_RX#[2] VSS162 VSS235
DMI_CRX_PTX_N3 B24 K33 PEG_CRX_GTX_N0 CC8 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N0 T33 E30
<19> DMI_CRX_PTX_N3 DMI_RX#[3] PEG_RX#[0] VSS163 VSS236
M35 PEG_CRX_GTX_N1 CC9 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N1 T32 E27
DMI_CRX_PTX_P0 B28 PEG_RX#[1] L34 PEG_CRX_GTX_N2 CC10 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N2 T31 VSS164 VSS237 E24
<19> DMI_CRX_PTX_P0 DMI_RX[0] PEG_RX#[2] VSS165 VSS238
DMI_CRX_PTX_P1 B26 J35 PEG_CRX_GTX_N3 CC1 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N3 T30 E21
DMI_CRX_PTX_P2 A24 J32 PEG_CRX_GTX_N4 CC2 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N4 T29 E18
DMI_CRX_PTX_P3 B23 H34 PEG_CRX_GTX_N5 CC11 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N5 T28 E15
DMI
H31 PEG_CRX_GTX_N6 CC12 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N6 T27 E13
DMI_CTX_PRX_N0 G21 PEG_RX#[6] G33 PEG_CRX_GTX_N7 CC3 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N7 T26 VSS169 VSS242 E10
<19> DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7] VSS170 VSS243
<19> DMI_CTX_PRX_N1 DMI_CTX_PRX_N1 E22 G30 PEG_CRX_GTX_N8 CC4 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N8 P9 E9
DMI_CTX_PRX_N2 F21 DMI_TX#[1] PEG_RX#[8] F35 PEG_CRX_GTX_N9 CC13 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N9 P8 VSS171 VSS244 E8
<19> DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9] VSS172 VSS245
<19> DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 D21 E34 PEG_CRX_GTX_N10 CC14 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N10 P6 E7
DMI_TX#[3] PEG_RX#[10] E32 PEG_CRX_GTX_N11 CC5 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N11 P5 VSS173 VSS246 E6
DMI_CTX_PRX_P0 G22 PEG_RX#[11] D33 PEG_CRX_GTX_N12 CC6 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N12 P3 VSS174 VSS247 E5
<19> DMI_CTX_PRX_P0 DMI_TX[0] PEG_RX#[12] VSS175 VSS248
<19> DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 D22 D31 PEG_CRX_GTX_N13 CC15 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N13 P2 E4
DMI_CTX_PRX_P2 F20 DMI_TX[1] PEG_RX#[13] B33 PEG_CRX_GTX_N14 CC16 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N14 N35 VSS176 VSS249 E3
DMI_CTX_PRX_P3 C21 C32 PEG_CRX_GTX_N15 CC7 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N15 N34 E2
PCI EXPRESS* - GRAPHICS

N33 E1
J33 PEG_CRX_GTX_P0 CC17 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P0 N32 VSS179 VSS252 D35
PEG_RX[0] L35 PEG_CRX_GTX_P1 CC18 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P1 N31 VSS180 VSS253 D32
PEG_RX[1] K34 PEG_CRX_GTX_P2 CC19 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P2 N30 VSS181 VSS254 D29
FDI_CTX_PRX_N0 A21 PEG_RX[2] H35 PEG_CRX_GTX_P3 CC20 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P3 N29 VSS182 VSS255 D26
<19> FDI_CTX_PRX_N0 FDI0_TX#[0] PEG_RX[3] VSS183 VSS256
<19> FDI_CTX_PRX_N1 FDI_CTX_PRX_N1 H19 H32 PEG_CRX_GTX_P4 CC21 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P4 N28 D20
FDI_CTX_PRX_N2 E19 FDI0_TX#[1] PEG_RX[4] G34 PEG_CRX_GTX_P5 CC22 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P5 N27 VSS184 VSS257 D17
<19> FDI_CTX_PRX_N3 FDI_CTX_PRX_N3 F18 G31 PEG_CRX_GTX_P6 CC23 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P6 N26 C34
FDI_CTX_PRX_N4 B21 FDI0_TX#[3] PEG_RX[6] F33 PEG_CRX_GTX_P7 CC24 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P7 M34 VSS186 VSS259 C31
<19> FDI_CTX_PRX_N4
Intel(R) FDI
FDI_CTX_PRX_N5 C20 FDI1_TX#[0] PEG_RX[7] F30 PEG_CRX_GTX_P8 CC25 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P8 L33 VSS187 VSS260 C28
<19> FDI_CTX_PRX_N6 FDI_CTX_PRX_N6 D18 E35 PEG_CRX_GTX_P9 CC26 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P9 L30 C27
FDI_CTX_PRX_N7 E17 FDI1_TX#[2] PEG_RX[9] E33 PEG_CRX_GTX_P10 CC27 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P10 L27 VSS189 VSS262 C25
C F32 PEG_CRX_GTX_P11 CC28 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P11 L9 C23 C
PEG_RX[11] D34 PEG_CRX_GTX_P12 CC29 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P12 L8 VSS191 VSS264 C10
FDI_CTX_PRX_P0 A22 PEG_RX[12] E31 PEG_CRX_GTX_P13 CC30 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P13 L6 VSS192 VSS265 C1
<19> FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13] VSS193 VSS266
<19> FDI_CTX_PRX_P1 FDI_CTX_PRX_P1 G19 C33 PEG_CRX_GTX_P14 CC31 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P14 L5 B22
FDI_CTX_PRX_P2 E20 FDI0_TX[1] PEG_RX[14] B32 PEG_CRX_GTX_P15 CC32 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P15 L4 VSS194 VSS267 B19
<19> FDI_CTX_PRX_P2
<19>
<19>
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
G18
B20
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
PEG_RX[15]
PEG_TX#[0]
M29 PEG_CTX_GRX_C_N0 CC33 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N0
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
<19> FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 C19 M32 PEG_CTX_GRX_C_N1 CC34 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N1 L1 B13
FDI_CTX_PRX_P6 D19 FDI1_TX[1] PEG_TX#[1] M31 PEG_CTX_GRX_C_N2 CC35 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N2 K35 VSS198 VSS271 B11
<19> FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2] VSS199 VSS272
<19> FDI_CTX_PRX_P7 FDI_CTX_PRX_P7 F17 L32 PEG_CTX_GRX_C_N3 CC36 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N3 K32 B9
FDI1_TX[3] PEG_TX#[3] L29 PEG_CTX_GRX_C_N4 CC37 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N4 K29 VSS200 VSS273 B8
FDI_FSYNC0 J18 PEG_TX#[4] K31 PEG_CTX_GRX_C_N5 CC38 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N5 K26 VSS201 VSS274 B7
<19> FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5] VSS202 VSS275
FDI_FSYNC1 J17 K28 PEG_CTX_GRX_C_N6 CC39 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N6 J34 B5
<19> FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] VSS203 VSS276
J30 PEG_CTX_GRX_C_N7 CC40 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N7 J31 B3
FDI_INT H20 PEG_TX#[7] J28 PEG_CTX_GRX_C_N8 CC41 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N8 H33 VSS204 VSS277 B2
<19> FDI_INT FDI_INT PEG_TX#[8] VSS205 VSS278
H29 PEG_CTX_GRX_C_N9 CC42 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N9 H30 A35
FDI_LSYNC0 J19 PEG_TX#[9] G27 PEG_CTX_GRX_C_N10 CC43 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N10 H27 VSS206 VSS279 A32
<19> FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10] VSS207 VSS280
FDI_LSYNC1 H17 E29 PEG_CTX_GRX_C_N11 CC44 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N11 H24 A29
<19> FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] VSS208 VSS281
F27 PEG_CTX_GRX_C_N12 CC45 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N12 H21 A26
PEG_TX#[12] D28 PEG_CTX_GRX_C_N13 CC46 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N13 H18 VSS209 VSS282 A23
(1) EDP_COMPIO use 4mil trace to RC1 PEG_TX#[13] F26 PEG_CTX_GRX_C_N14 CC47 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N14 H15 VSS210 VSS283 A20
(2) EDP_ICOMPO use 12mil to RC1 PEG_TX#[14] E25 PEG_CTX_GRX_C_N15 CC48 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N15 H13 VSS211 VSS284 A3
EDP_COMP A18 PEG_TX#[15] H10 VSS212 VSS285
A17 eDP_COMPIO M28 PEG_CTX_GRX_C_P0 CC49 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P0 H9 VSS213
B16 eDP_ICOMPO PEG_TX[0] M33 PEG_CTX_GRX_C_P1 CC50 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P1 H8 VSS214
eDP_HPD# PEG_TX[1] M30 PEG_CTX_GRX_C_P2 CC51 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P2 H7 VSS215
PEG_TX[2] L31 PEG_CTX_GRX_C_P3 CC52 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P3 H6 VSS216
C15 PEG_TX[3] L28 PEG_CTX_GRX_C_P4 CC53 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P4 H5 VSS217
D15 eDP_AUX PEG_TX[4] K30 PEG_CTX_GRX_C_P5 CC54 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P5 H4 VSS218
eDP_AUX# PEG_TX[5] K27 PEG_CTX_GRX_C_P6 CC55 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P6 H3 VSS219
PEG_TX[6] J29 PEG_CTX_GRX_C_P7 CC56 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P7 H2 VSS220
eDP
C17 PEG_TX[7] J27 PEG_CTX_GRX_C_P8 CC57 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P8 H1 VSS221

B F16 eDP_TX[0] PEG_TX[8] H28 PEG_CTX_GRX_C_P9 CC58 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P9 G35 VSS222 B
C16 eDP_TX[1] PEG_TX[9] G28 PEG_CTX_GRX_C_P10 CC59 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P10 G32 VSS223
G15 eDP_TX[2] PEG_TX[10] E28 PEG_CTX_GRX_C_P11 CC60 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P11 G29 VSS224
eDP_TX[3] PEG_TX[11] F28 PEG_CTX_GRX_C_P12 CC61 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P12 G26 VSS225
C18 PEG_TX[12] D27 PEG_CTX_GRX_C_P13 CC62 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P13 G23 VSS226
E16 eDP_TX#[0] PEG_TX[13] E26 PEG_CTX_GRX_C_P14 CC63 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P14 G20 VSS227
D16 eDP_TX#[1] PEG_TX[14] D25 PEG_CTX_GRX_C_P15 CC64 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P15 G17 VSS228
F15 eDP_TX#[2] PEG_TX[15] G11 VSS229
eDP_TX#[3] F34 VSS230
F31 VSS231
TYCO_2134146-3_IVYBRIDGE~D F29 VSS232
VSS233
Link CIS OK
+1.05V_RUN_VTT
0722 +1.05V_RUN_VTT
2 1 EDP_COMP 1 2 PEG_COMP
RC1 24.9_0402_1%~D RC2 24.9_0402_1%~D TYCO_2134146-3_IVYBRIDGE~D
eDP Compensation PEG Compensation
PEG_ICOMPI and RCOMPO signals
Link CIS OK
eDP_COMPIO and ICOMPO signals should be shorted near should be shorted and routed with
balls and routed with typical impedance <25 mohms ‐ max length = 500 mils
‐ typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with
A A
‐ max length = 500 mils
‐ typical impedance = 14.5 mohms
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Ivy Bridge (1/6)
5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com Follow DG Rev0.71 SM_DRAMPWROK topology
+1.5V_CPU_VDDQ
+3.3V_ALW_PCH
+3.3V_ALW_PCH 1 2 SYS_PWROK_XDP +1.05V_RUN_VTT

@ RC3 1K_0402_5%~D
1
CC65
1 2 JXDP1 CONN@
RC4 +1.05V_RUN_VTT XDP_PREQ# 1
0.1U_0402_16V4Z~D 200_0402_5%~D XDP_PRDY# 2 OBSFN_A0
OBSFN_A1
5
3
2
1 4 GND
G VCC
<48,49> RUNPWROK B OBSDATA_A[0]
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
4 VDDPWRGOOD 1 2 VDDPWRGOOD_R 5
2 Y RC5 130_0402_5%~D 6 OBSDATA_A[1]
<19> PM_DRAM_PWRGD A 1 1 GND
D UC1 7 D
OBSDATA_A[2]
1
39_0402_5%~D
CC66
CC67
+3.3V_ALW_PCH 1 2 MC74VHC1G09DFT2G_SC70-5 8
3
OBSDATA_A[3]
@ RC7
RC6 200_0402_5%~D 9
2 2 H_CPUPWRGD RC8 1 2 1K_0402_5%~D H_CPUPWRGD_XDP 10 GND
@ RC9 1 2 0_0402_5%~D CFD_PWRBTN#_XDP 11 HOOK0
<17,19> SIO_PWRBTN#_R HOOK1
RC10 1 2 1K_0402_5%~D XDP_HOOK2 12
<9> CFG0
2
HOOK2
SSM3K7002FU_SC70-3~D
@ RC12 1 2 0_0402_5%~D SYS_PWROK_XDP 13
<19,48> SYS_PWROK HOOK3
Place near JXDP1 CLK_XDP 14
CLK_XDP# 15 HOOK4
HOOK5
1
D
@ QC1
16
2 XDP_RST#_R 17 VCCOBS_AB
<11,52> RUN_ON_CPU1.5VS3# HOOK6
G XDP_DBRESET# 18
19 HOOK7
S
3
+1.05V_RUN_VTT XDP_TDO 20 GND
XDP_TRST# 21 TDO
1 2 H_THERMTRIP# XDP_TDI 22 TRSTn
@ RC11 56_0402_5%~D XDP_TMS 23 TDI
1 2 H_CATERR# 24 TMS 27
@ RC13 49.9_0402_1%~D 25 TCK1 GND 28
1 2 H_PROCHOT# XDP_TCLK 26 GND GND
RC16 62_0402_5%~D TCK0
MOLEX_52435-2671
JCPU1B CONN@
Link CIS OK
C26 BCLK
A28
A27
CPU_DMI @ RC17
CPU_DMI# @ RC18
1
1
2 0_0402_5%~D
2 0_0402_5%~D
CLK_CPU_DMI <18>
0722
<21> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <18>
MISC
CLOCKS
C AN34 C
<48> CPU_DETECT# SKTOCC# A16 CPU_DPLL RC19 1 2 1K_0402_1%~D XDP_RST#_R 2 1
DPLL_REF_CLK PLTRST_XDP# <20>
A15 CPU_DPLL# RC21 1 2 1K_0402_1%~D +1.05V_RUN_VTT RC20 1K_0402_5%~D
DPLL_REF_CLK#
H_CATERR# AL33 CLK_XDP @ RH1 1 2 0_0402_5%~D

CATERR# CLK_CPU_ITP <18>
CLK_XDP# @ RH2 1 2 0_0402_5%~D
CLK_CPU_ITP# <18>
D
AN33 R8 DDR3_DRAMRST#_CPU 3 1
THERMAL
<49> PECI_EC PECI SM_DRAMRST# DDR3_DRAMRST# <12>

QC2 <9> CLK_XDP_ITP 1 2
4.99K_0402_1%~D
DDR3
MISC BSS138W-7-F_SOT323-3~D @ RH3 0_0402_5%~D
G
2
1
<26,49,60,62> H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 <9> CLK_XDP_ITP# 1 2
PROCHOT# SM_RCOMP[0]
RC23
RC22 56_0402_5%~D A5 SM_RCOMP1 @ RH4 0_0402_5%~D
SM_RCOMP[1] A4 SM_RCOMP2 DDR_HVREF_RST
Place RC22 near CPU SM_RCOMP[2]
<25> H_THERMTRIP# 1 2 H_THERMTRIP#_R AN32 1
2
@ RC24 0_0402_5%~D THERMTRIP#
CC68
0.047U_0402_16V4Z~D
2
AP29 XDP_PRDY#
PRDY# AP27 XDP_PREQ#
PREQ# @ RC25 1 2 0_0402_5%~D
<18> DDR_HVREF_RST_PCH
AR26 XDP_TCLK
TCK AR27 XDP_TMS @ RC26 1 2 0_0402_5%~D
TMS <49> DDR_HVREF_RST_GATE DDR_HVREF_RST <12>
H_PM_SYNC AM34 AP30 XDP_TRST#
PWR MANAGEMENT
PU/PD for JTAG signals
JTAG & BPM
<19> H_PM_SYNC PM_SYNC TRST#

AR28 XDP_TDI_R +3.3V_RUN
TDI AP26 XDP_TDO_R
@ RC27 1 2 H_CPUPWRGD_R AP33 TDO
B <21> H_CPUPWRGD UNCOREPWRGOOD B
0_0402_5%~D XDP_DBRESET# 1 2
@ RC29 1K_0402_5%~D RC28
AL35 XDP_DBRESET#_R 1 2 0_0402_5%~D XDP_DBRESET# <17,19>
VDDPWRGOOD_R V8 DBR# +1.05V_RUN_VTT
SM_DRAMPWROK
AT28 XDP_OBS0 XDP_TMS 1 2
BPM#[0] AR29 XDP_OBS1 PAD~D T69 @ 51_0402_1%~D RC31
BPM#[1] AR30 XDP_OBS2 PAD~D T70 @ XDP_TDI_R 1 2
PCH_PLTRST#_R AR33 BPM#[2] AT30 XDP_OBS3 PAD~D T68 @ 51_0402_1%~D RC35
RESET# BPM#[3] AP32 XDP_OBS4 PAD~D T67 @ XDP_PREQ# 1 2
BPM#[4] AR31 XDP_OBS5 PAD~D T78 @ 51_0402_1%~D @ RC38
BPM#[5] AT31 XDP_OBS6 PAD~D T77 @ XDP_TDO 1 2
BPM#[6] AR32 XDP_OBS7 PAD~D T79 @ 51_0402_1%~D RC42
BPM#[7] PAD~D T80 @
XDP_TCLK 1 2
XDP_TDI_R @ RC34 1 2 0_0402_5%~D XDP_TDI 51_0402_1%~D RC44
TYCO_2134146-3_IVYBRIDGE~D XDP_TDO_R @ RC40 1 2 0_0402_5%~D XDP_TDO XDP_TRST# 1 2
51_0402_1%~D RC45
Link CIS OK For ESD concern, please put near CPU
Max length = 500 mils
Buffered reset to CPU Trace width = 15mils
+3.3V_RUN
SM_RCOMP2 1 2
+1.05V_RUN_VTT 200_0402_1%~D RC47
0.1U_0402_16V4Z~D
SM_RCOMP1 1 2
1 H_CPUPWRGD 1 2 25.5_0402_1%~D RC48
75_0402_1%~D
10K_0402_5%~D RC46 SM_RCOMP0 1 2

1
CC69
140_0402_1%~D RC50
RC49
A 2 A
2
5
1
Avoid stub in the PWRGD path DELL CONFIDENTIAL/PROPRIETARY
P
NC 4 PCH_PLTRST#_BUF 1 2 PCH_PLTRST#_R
2 Y RC51 43_0402_5%~D while placing resistors RC27& RC46
<20> PCH_PLTRST# A
G
UC2
SN74LVC1G07DCKR_SC70-5~D Compal Electronics, Inc.
3
Title
Open drain buffer TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Ivy Bridge (2/6)
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
5 4
WWW.AliSaler.Com PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3 2
LA-7931P
1
Sheet 7 of 70
1.0
5 4 3 2 1
WWW.AliSaler.Com
D D
JCPU1D CONN@
JCPU1C CONN@
AE2 M_CLK_DDR2
<14,15> DDR_B_D[0..63] SB_CK[0] M_CLK_DDR2 <15>
AB6 M_CLK_DDR0 AD2 M_CLK_DDR#2
<12,13> DDR_A_D[0..63] SA_CK[0] M_CLK_DDR0 <13> SB_CLK#[0] M_CLK_DDR#2 <15>
AA6 M_CLK_DDR#0 DDR_B_D0 C9 R9 DDR_CKE2_DIMM4
SA_CLK#[0] M_CLK_DDR#0 <13> SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMM4 <15>
DDR_A_D0 C5 V9 DDR_CKE0_DIMM2 DDR_B_D1 A7
SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMM2 <13> SB_DQ[1]
DDR_A_D1 D5 DDR_B_D2 D10
DDR_A_D2 D3 SA_DQ[1] DDR_B_D3 C8 SB_DQ[2]
DDR_A_D3 D2 SA_DQ[2] DDR_B_D4 A9 SB_DQ[3] AE1 M_CLK_DDR3
SA_DQ[3] SB_DQ[4] SB_CK[1] M_CLK_DDR3 <15>
DDR_A_D4 D6 AA5 M_CLK_DDR1 DDR_B_D5 A8 AD1 M_CLK_DDR#3
SA_DQ[4] SA_CK[1] M_CLK_DDR1 <13> SB_DQ[5] SB_CLK#[1] M_CLK_DDR#3 <15>
DDR_A_D5 C6 AB5 M_CLK_DDR#1 DDR_B_D6 D9 R10 DDR_CKE3_DIMM4
SA_DQ[5] SA_CLK#[1] M_CLK_DDR#1 <13> SB_DQ[6] SB_CKE[1] DDR_CKE3_DIMM4 <15>
DDR_A_D6 C2 V10 DDR_CKE1_DIMM2 DDR_B_D7 D8
DDR_A_D7 C3 DDR_B_D8 G4
DDR_A_D8 F10 SA_DQ[7] DDR_B_D9 F4 SB_DQ[8]
DDR_A_D9 F8 SA_DQ[8] DDR_B_D10 F1 SB_DQ[9] AB2 M_CLK_DDR6
DDR_A_D10 G10 AB4 M_CLK_DDR4 DDR_B_D11 G1 AA2 M_CLK_DDR#6
DDR_A_D11 G9 AA4 M_CLK_DDR#4 DDR_B_D12 G5 T9 DDR_CKE6_DIMM3
DDR_A_D12 F9 W9 DDR_CKE4_DIMM1 DDR_B_D13 F5
DDR_A_D13 F7 DDR_B_D14 F2
DDR_A_D14 G8 SA_DQ[13] DDR_B_D15 G2 SB_DQ[14]
DDR_A_D15 G7 SA_DQ[14] DDR_B_D16 J7 SB_DQ[15] AA1 M_CLK_DDR7
DDR_A_D16 K4 AB3 M_CLK_DDR5 DDR_B_D17 J8 AB1 M_CLK_DDR#7
DDR_A_D17 K5 AA3 M_CLK_DDR#5 DDR_B_D18 K10 T10 DDR_CKE7_DIMM3
DDR_A_D18 K1 W10 DDR_CKE5_DIMM1 DDR_B_D19 K9
DDR_A_D19 J1 DDR_B_D20 J9
DDR_A_D20 J5 SA_DQ[19] DDR_B_D21 J10 SB_DQ[20]
DDR_A_D21 J4 SA_DQ[20] DDR_B_D22 K8 SB_DQ[21] AD3 DDR_CS2_DIMM4#
C SA_DQ[21] SB_DQ[22] SB_CS#[0] DDR_CS2_DIMM4# <15> C
DDR_A_D22 J2 AK3 DDR_CS0_DIMM2# DDR_B_D23 K7 AE3 DDR_CS3_DIMM4#
SA_DQ[22] SA_CS#[0] DDR_CS0_DIMM2# <13> SB_DQ[23] SB_CS#[1] DDR_CS3_DIMM4# <15>
DDR_A_D23 K2 AL3 DDR_CS1_DIMM2# DDR_B_D24 M5 AD6 DDR_CS6_DIMM3#
DDR_A_D24 M8 AG1 DDR_CS4_DIMM1# DDR_B_D25 N4 AE6 DDR_CS7_DIMM3#
DDR_A_D25 N10 AH1 DDR_CS5_DIMM1# DDR_B_D26 N2
SA_DQ[25] SA_CS#[3] DDR_CS5_DIMM1# <12> SB_DQ[26]
DDR_A_D26 N8 DDR_B_D27 N1
DDR_A_D27 N7 SA_DQ[26] DDR_B_D28 M4 SB_DQ[27]
DDR_A_D28 M10 SA_DQ[27] DDR_B_D29 N5 SB_DQ[28] AE4 M_ODT2
SA_DQ[28] SB_DQ[29] SB_ODT[0] M_ODT2 <15>
DDR_A_D29 M9 AH3 M_ODT0 DDR_B_D30 M2 AD4 M_ODT3
SA_DQ[29] SA_ODT[0] M_ODT0 <13> SB_DQ[30] SB_ODT[1] M_ODT3 <15>
DDR_A_D30 N9 AG3 M_ODT1 DDR_B_D31 M1 AD5 M_ODT6
DDR SYSTEM MEMORY B

SA_DQ[30] SA_ODT[1] M_ODT1 <13> SB_DQ[31] SB_ODT[2] M_ODT6 <14>
DDR_A_D31 M7 AG2 M_ODT4 DDR_B_D32 AM5 AE5 M_ODT7
M_ODT4 <12> M_ODT7 <14>
DDR SYSTEM MEMORY A
DDR_A_D32 AG6 SA_DQ[31] SA_ODT[2] AH2 M_ODT5 DDR_B_D33 AM6 SB_DQ[32] SB_ODT[3]
SA_DQ[32] SA_ODT[3] M_ODT5 <12> SB_DQ[33]
DDR_A_D33 AG5 DDR_B_D34 AR3
DDR_A_D34 AK6 SA_DQ[33] DDR_B_D35 AP3 SB_DQ[34]
DDR_A_D35 AK5 SA_DQ[34] DDR_B_D36 AN3 SB_DQ[35]
SA_DQ[35] SB_DQ[36] DDR_B_DQS#[0..7] <14,15>
DDR_A_D36 AH5 DDR_B_D37 AN2 D7 DDR_B_DQS#0
SA_DQ[36] DDR_A_DQS#[0..7] <12,13> SB_DQ[37] SB_DQS#[0]
DDR_A_D37 AH6 C4 DDR_A_DQS#0 DDR_B_D38 AN1 F3 DDR_B_DQS#1
DDR_A_D38 AJ5 SA_DQ[37] SA_DQS#[0] G6 DDR_A_DQS#1 DDR_B_D39 AP2 SB_DQ[38] SB_DQS#[1] K6 DDR_B_DQS#2
DDR_A_D39 AJ6 SA_DQ[38] SA_DQS#[1] J3 DDR_A_DQS#2 DDR_B_D40 AP5 SB_DQ[39] SB_DQS#[2] N3 DDR_B_DQS#3
DDR_A_D40 AJ8 SA_DQ[39] SA_DQS#[2] M6 DDR_A_DQS#3 DDR_B_D41 AN9 SB_DQ[40] SB_DQS#[3] AN5 DDR_B_DQS#4
DDR_A_D41 AK8 SA_DQ[40] SA_DQS#[3] AL6 DDR_A_DQS#4 DDR_B_D42 AT5 SB_DQ[41] SB_DQS#[4] AP9 DDR_B_DQS#5
DDR_A_D42 AJ9 SA_DQ[41] SA_DQS#[4] AM8 DDR_A_DQS#5 DDR_B_D43 AT6 SB_DQ[42] SB_DQS#[5] AK12 DDR_B_DQS#6
DDR_A_D43 AK9 SA_DQ[42] SA_DQS#[5] AR12 DDR_A_DQS#6 DDR_B_D44 AP6 SB_DQ[43] SB_DQS#[6] AP15 DDR_B_DQS#7
DDR_A_D44 AH8 SA_DQ[43] SA_DQS#[6] AM15 DDR_A_DQS#7 DDR_B_D45 AN8 SB_DQ[44] SB_DQS#[7]
DDR_A_D45 AH9 SA_DQ[44] SA_DQS#[7] DDR_B_D46 AR6 SB_DQ[45]
DDR_A_D46 AL9 SA_DQ[45] DDR_B_D47 AR5 SB_DQ[46]
DDR_A_D47 AL8 SA_DQ[46] DDR_B_D48 AR9 SB_DQ[47]
SA_DQ[47] SB_DQ[48] DDR_B_DQS[0..7] <14,15>
DDR_A_D48 AP11 DDR_B_D49 AJ11 C7 DDR_B_DQS0
SA_DQ[48] DDR_A_DQS[0..7] <12,13> SB_DQ[49] SB_DQS[0]
DDR_A_D49 AN11 D4 DDR_A_DQS0 DDR_B_D50 AT8 G3 DDR_B_DQS1
DDR_A_D50 AL12 SA_DQ[49] SA_DQS[0] F6 DDR_A_DQS1 DDR_B_D51 AT9 SB_DQ[50] SB_DQS[1] J6 DDR_B_DQS2
DDR_A_D51 AM12 SA_DQ[50] SA_DQS[1] K3 DDR_A_DQS2 DDR_B_D52 AH11 SB_DQ[51] SB_DQS[2] M3 DDR_B_DQS3
DDR_A_D52 AM11 SA_DQ[51] SA_DQS[2] N6 DDR_A_DQS3 DDR_B_D53 AR8 SB_DQ[52] SB_DQS[3] AN6 DDR_B_DQS4
DDR_A_D53 AL11 SA_DQ[52] SA_DQS[3] AL5 DDR_A_DQS4 DDR_B_D54 AJ12 SB_DQ[53] SB_DQS[4] AP8 DDR_B_DQS5
B DDR_A_D54 AP12 SA_DQ[53] SA_DQS[4] AM9 DDR_A_DQS5 DDR_B_D55 AH12 SB_DQ[54] SB_DQS[5] AK11 DDR_B_DQS6 B
DDR_A_D55 AN12 SA_DQ[54] SA_DQS[5] AR11 DDR_A_DQS6 DDR_B_D56 AT11 SB_DQ[55] SB_DQS[6] AP14 DDR_B_DQS7
DDR_A_D56 AJ14 SA_DQ[55] SA_DQS[6] AM14 DDR_A_DQS7 DDR_B_D57 AN14 SB_DQ[56] SB_DQS[7]
DDR_A_D57 AH14 SA_DQ[56] SA_DQS[7] DDR_B_D58 AR14 SB_DQ[57]
DDR_A_D58 AL15 SA_DQ[57] DDR_B_D59 AT14 SB_DQ[58]
SA_DQ[58] SB_DQ[59] DDR_B_MA[0..15] <14,15>
DDR_A_D59 AK15 DDR_B_D60 AT12
SA_DQ[59] DDR_A_MA[0..15] <12,13> SB_DQ[60]
DDR_A_D60 AL14 DDR_B_D61 AN15 AA8 DDR_B_MA0
DDR_A_D61 AK14 SA_DQ[60] AD10 DDR_A_MA0 DDR_B_D62 AR15 SB_DQ[61] SB_MA[0] T7 DDR_B_MA1
DDR_A_D62 AJ15 SA_DQ[61] SA_MA[0] W1 DDR_A_MA1 DDR_B_D63 AT15 SB_DQ[62] SB_MA[1] R7 DDR_B_MA2
DDR_A_D63 AH15 SA_DQ[62] SA_MA[1] W2 DDR_A_MA2 SB_DQ[63] SB_MA[2] T6 DDR_B_MA3
SA_DQ[63] SA_MA[2] W7 DDR_A_MA3 SB_MA[3] T2 DDR_B_MA4
SA_MA[3] V3 DDR_A_MA4 SB_MA[4] T4 DDR_B_MA5
SA_MA[5] W3 DDR_A_MA6 DDR_B_BS0 AA9 SB_MA[6] R2 DDR_B_MA7
SA_MA[6] <14,15> DDR_B_BS0 SB_BS[0] SB_MA[7]
DDR_A_BS0 AE10 W6 DDR_A_MA7 DDR_B_BS1 AA7 T5 DDR_B_MA8
<12,13> DDR_A_BS0 SA_BS[0] SA_MA[7] <14,15> DDR_B_BS1 SB_BS[1] SB_MA[8]
DDR_A_BS1 AF10 V1 DDR_A_MA8 DDR_B_BS2 R6 R3 DDR_B_MA9
<12,13> DDR_A_BS1 SA_BS[1] SA_MA[8] <14,15> DDR_B_BS2 SB_BS[2] SB_MA[9]
DDR_A_BS2 V6 W5 DDR_A_MA9 AB7 DDR_B_MA10
<12,13> DDR_A_BS2 SA_BS[2] SA_MA[9] SB_MA[10]
AD8 DDR_A_MA10 R1 DDR_B_MA11
SA_MA[11] W4 DDR_A_MA12 DDR_B_CAS# AA10 SB_MA[12] AB10 DDR_B_MA13
SA_MA[12] <14,15> DDR_B_CAS# SB_CAS# SB_MA[13]
DDR_A_CAS# AE8 AF8 DDR_A_MA13 DDR_B_RAS# AB8 R5 DDR_B_MA14
<12,13> DDR_A_CAS# SA_CAS# SA_MA[13] <14,15> DDR_B_RAS# SB_RAS# SB_MA[14]
DDR_A_RAS# AD9 V5 DDR_A_MA14 DDR_B_WE# AB9 R4 DDR_B_MA15
<12,13> DDR_A_RAS# SA_RAS# SA_MA[14] <14,15> DDR_B_WE# SB_WE# SB_MA[15]
DDR_A_WE# AF9 V7 DDR_A_MA15
<12,13> DDR_A_WE# SA_WE# SA_MA[15]
TYCO_2134146-3_IVYBRIDGE~D
TYCO_2134146-3_IVYBRIDGE~D
A Link CIS OK Link CIS OK A
Title
5 4 3 2 1
5 4 3 2 1
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CFG Straps for Processor
CFG2
1
1K_0402_5%~D
@ RC52
D D
2
JCPU1E CONN@
AH27 @ T4 PAD~D
CFG0 AK28 VCC_DIE_SENSE AH26
<7> CFG0
CFG1 AK29 CFG[0] VSS_DIE_SENSE PEG Static Lane Reversal ‐ CFG2 is for the 16x
@ T60 PAD~D CFG2 AL26 CFG[1]
CFG3 AL27 CFG[2] 1:(Default) Normal Operation; Lane #
@ T55 PAD~D CFG4 AK26 CFG[3] L7
CFG5 AL29 CFG[4] RSVD28 AG7 @ T5 PAD~D CFG2 definition matches socket pin map definition
CFG6 AL30 CFG[5] RSVD29 AE7 @ T6 PAD~D
CFG7 AM31 CFG[6] RSVD30 AK2 @ T7 PAD~D 0:Lane Reversed
CFG8 AM32 CFG[7] RSVD31 @ T8 PAD~D
@ T65 PAD~D CFG9 AM30 CFG[8] W8
@ T64 PAD~D CFG[9] RSVD32
CFG
CFG10 AM28 @ T1 PAD~D
@ T76 PAD~D CFG11 AM26 CFG[10] CFG4
@ T75 PAD~D CFG12 AN28 CFG[11] AT26
CFG[12] RSVD33
1
@ T2 PAD~D
@
1K_0402_5%~D
CFG13 AN31 AM33 @ T9 PAD~D
@ T3 PAD~D CFG[13] RSVD34
RC53
CFG14 AN26 AJ27 @ T10 PAD~D
@ T11 PAD~D CFG15 AM27 CFG[14] RSVD35 @ T12 PAD~D
+VCC_GFXCORE @ T13 PAD~D CFG16 AK31 CFG[15]
@ T72 PAD~D CFG17 AN29 CFG[16]
2
@ T71 PAD~D CFG[17]
1 2 VAXG_VAL_SENSE
@ RC54 49.9_0402_1%~D T8
RSVD37 J16 @ T14 PAD~D
RSVD38
1
VAXG_VAL_SENSE AJ31 H16 @ T15 PAD~D

@ RC55 VSSAXG_VAL_SENSE AH31 VAXG_VAL_SENSE RSVD39 G16 @ T16 PAD~D
C
100_0402_1%~D VCC_VAL_SNESE AJ33 VSSAXG_VAL_SENSE RSVD40 @ T17 PAD~D Display Port Presence Strap C
VSS_VAL_SNESE AH33 VCC_VAL_SENSE
VSS_VAL_SENSE 1 : Disabled; No Physical Display Port
2
1 2 VSSAXG_VAL_SENSE PAD~D T18 @ AJ26 AR35 attached to Embedded Display Port

@ RC56 49.9_0402_1%~D RSVD5 RSVD_NCTF1 AT34 @ T19 PAD~D CFG4
RSVD_NCTF2 AT33 @ T20 PAD~D 0 : Enabled; An external Display Port device is
RESERVED
RSVD_NCTF3 AP35 @ T21 PAD~D
RSVD_NCTF4 AR34 @ T22 PAD~D connected to the Embedded Display Port
RSVD_NCTF5 @ T23 PAD~D
PAD~D T24 @ F25

PAD~D T25 @ F24 RSVD8
+VCC_CORE PAD~D T26 @ F23 RSVD9 CFG6
PAD~D T27 @ D24 RSVD10 B34
PAD~D T29 @ G25 RSVD11 RSVD_NCTF6 A33 @ T28 PAD~D CFG5
1 2 VCC_VAL_SNESE PAD~D T31 @ G24 RSVD12 RSVD_NCTF7 A34 @ T30 PAD~D
RSVD13 RSVD_NCTF8
1
1K_0402_5%~D
1K_0402_5%~D
@ RC57 49.9_0402_1%~D PAD~D T33 @ E23 B35 @ T32 PAD~D
RSVD14 RSVD_NCTF9
@ RC60
@ RC59
PAD~D T35 @ D23 C35 @ T34 PAD~D
RSVD15 RSVD_NCTF10
1
PAD~D T37 @ C30 @ T36 PAD~D

@ RC58 PAD~D T38 @ A31 RSVD16
PAD~D T39 @ B30 RSVD17
100_0402_1%~D
2
PAD~D T40 @ B29 RSVD18
PAD~D T41 @ D30 RSVD19 AJ32
2
PAD~D T43 @ B31 RSVD20 RSVD51 AK32 @ T42 PAD~D

1 2 VSS_VAL_SNESE PAD~D T45 @ A30 RSVD21 RSVD52 @ T44 PAD~D
@ RC61 49.9_0402_1%~D PAD~D T46 @ C29 RSVD22
RSVD23
AN35
BCLK_ITP CLK_XDP_ITP <7>
PAD~D T47 @ J20 AM35
PAD~D T48 @ B18 RSVD24 BCLK_ITP# CLK_XDP_ITP# <7> PCIE Port Bifurcation Straps
RSVD25
B 11: (Default) x16 ‐ Device 1 functions 1 and 2 disabled B
PAD~D T49 @ J15 AT2 @ T50 PAD~D 10: x8, x8 ‐ Device 1 function 1 enabled ; function 2

RSVD27 RSVD_NCTF11 AT1 @ T51 PAD~D
RSVD_NCTF12 AR1 @ T52 PAD~D disabled
RSVD_NCTF13 CFG[6:5]
01: Reserved ‐ (Device 1 function 1 disabled ; function
B1 @ T53 PAD~D 2 enabled)
KEY
00: x8,x4,x4 ‐ Device 1 functions 1 and 2 enabled
TYCO_2134146-3_IVYBRIDGE~D CFG7
1
1K_0402_5%~D
Link CIS OK
@ RC62
2
PEG DEFER TRAINING
1: (Default) PEG Train immediately
CFG7 following xxRESETB de assertion
A A
0: PEG Wait for BIOS for training
Title
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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7931P
5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com JCPU1F CONN@ POWER

+VCC_CORE
+1.05V_RUN_VTT
97A 8.5A
AG35
AG34 VCC1 AH13
AG33 VCC2 VCCIO1 AH10
AG32 VCC3 VCCIO2 AG10
D AG31 VCC4 VCCIO3 AC10 D
AG30 VCC5 VCCIO4 Y10
AG29 VCC6 VCCIO5 U10
AG28 VCC7 VCCIO6 P10
AG27 VCC8 VCCIO7 L10
AG26 VCC9 VCCIO8 J14
AF35 VCC10 VCCIO9 J13
AF32 VCC13 VCCIO12 H14
AF29 VCC16 VCCIO15 G14
AF26 VCC19 VCCIO18 F14
PEG AND DDR

AD35 VCC20 VCCIO19 F13
AD32 VCC23 VCCIO22 E14
AD31 VCC24 VCCIO23 E12
AD30 VCC25 VCCIO24
AD29 VCC26 E11
AD28 VCC27 VCCIO25 D14
AC35 VCC30 VCCIO28 D11
AC34 VCC31 VCCIO29 C14
AC30 VCC35 VCCIO33 B14
C AC29 VCC36 VCCIO34 B12 C
AC28 VCC37 VCCIO35 A14
AC27 VCC38 VCCIO36 A13
AC26 VCC39 VCCIO37 A12 +1.05V_RUN_VTT
AA35 VCC40 VCCIO38 A11
AA34 VCC41 VCCIO39
VCC42
1
AA33 J23
AA32 VCC43 VCCIO40 Note: Place the PU resistors close to CPU RC63
AA31 VCC44 75_0402_1%~D
AA30 VCC45 RC63 close to CPU 300 ‐ 1500mils
AA29 VCC46
2
AA28 VCC47
AA27 VCC48 H_CPU_SVIDALRT# 1 2
VCC49 VIDALERT_N <60>
AA26 RC64 43_0402_5%~D
Y35 VCC50
Y34 VCC51
CORE SUPPLY
Y33 VCC52
Y32 VCC53
Y31 VCC54
Y30 VCC55 +1.05V_RUN_VTT
Y29 VCC56
Y28 VCC57
VCC58
1
Y27
Y26 VCC59 RC65 CAD Note: Place the PU
V35 VCC60 130_0402_1%~D
V34 VCC61 AJ29 H_CPU_SVIDALRT# resistors close to CPU
V33 VCC62 VIDALERT# AJ30
SVID
VIDSCLK
VIDSCLK <60> RC65 close to CPU 300 ‐ 1500mils
2
V32 VCC63 VIDSCLK AJ28 VIDSOUT
VCC64 VIDSOUT VIDSOUT <60>
V31
V30 VCC65
V29 VCC66
V28 VCC67
B V27 VCC68 B
V26 VCC69
U35 VCC70
U34 VCC71
U33 VCC72
U32 VCC73
U31 VCC74
U30 VCC75
U29 VCC76
U28 VCC77
U27 VCC78
U26 VCC79 +VCC_CORE
R35 VCC80
R34 VCC81
VCC82
1
R33
R32 VCC83 @ RC66 RC67
R31 VCC84 1 2
VCC85 100_0402_1%~D
R30
R29 VCC86 100_0402_1%~D
Place RC68, RC69near CPU
2
R28 VCC87
R27 VCC88 AJ35 VCCSENSE_R@ RC68 1 2 0_0402_5%~D
SENSE LINES
VCC89 VCC_SENSE VCCSENSE <60>

R26 AJ34 VSSSENSE_R@ RC69 1 2 0_0402_5%~D
VCC90 VSS_SENSE VSSSENSE <60>
P35
P34 VCC91 2 1
VCC92 +1.05V_RUN_VTT
P33 10_0402_1% RC70
VCC93
1
P32 B10 VTT_SENSE <58>
P31 VCC94 VCCIO_SENSE A10 RC71
VCC95 VSS_SENSE_VCCIO VSSIO_SENSE_R <58>
P30 100_0402_1%~D
P29 VCC96
VCC97
1
10_0402_1%~D
P28
2
P27 VCC98
RC72
P26 VCC99
A VCC100 A
2
TYCO_2134146-3_IVYBRIDGE~D Compal Electronics, Inc.
Title
Ivy Bridge (5/6)
Link CIS OK TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com +1.5V_CPU_VDDQ Source Solve backdrive (follow B4).

+PWR_SRC_S
+1.5V_MEM QC3 +1.5V_CPU_VDDQ
+3.3V_ALW2 AO4304L_SO8
330K_0402_5%~D
8 1
1
7 2
RC73
10U_0805_6.3V6M~D
6 3
Solve 300mW
1
100K_0402_5%~D
20K_0402_5%~D
5 1
1
+1.5V_CPU_VDDQ
@
CC70
PWR consumption
RC76
RC77
2
4
issue. +1.5V_MEM +V_DDR_SMREF
1K_0402_1%~D
1
RUN_ON_CPU1.5VS3 2
2
D 1 2 D
1K_0402_1%~D
RC75
2
1
0.022U_0603_50V7~D
@ @ RC74 0_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
1M_0402_5%~D
RC78
1
+V_SM_VREF_CNT
QC5B
1 @ QC4
2
RC79
RUN_ON_CPU1.5VS3# 5 NTR4503NT1G_SOT23-3~D
CC71
2
1 3
4
2
2
6
1K_0402_1%~D
1
@ RC82 1 2 0_0402_5%~D @ JCPU1H CONN@
1K_0402_1%~D
<19,35,47,48,52,56> SIO_SLP_S3#
1
QC5A
RC80
@ RC83 1 2 0_0402_5%~D 2 2 AT35 AJ22
Solve 300mW
RC81
<49> CPU1.5V_S3_GATE VSS1 VSS81
AT32 AJ19
VSS2 VSS82
PWR consumption AT29 AJ16
2
AT27 VSS3 VSS83 AJ13
2
VSS4 VSS84
issue. RUN_ON_CPU1.5VS3 AT25
AT22 VSS5 VSS85
AJ10
AJ7
RUN_ON_CPU1.5VS3# <7,52> VSS6 VSS86
AT19 AJ4
AT16 VSS7 VSS87 AJ3
+VCC_GFXCORE AT13 VSS8 VSS88 AJ2
AT10 VSS9 VSS89 AJ1
AT7 VSS10 VSS90 AH35
VSS11 VSS91
1
100_0402_1%~D
AT4 AH34
AT3 VSS12 VSS92 AH32
POWER VSS13 VSS93
RC84
AR25 AH30
1 @ RC85 2 AR22 VSS14 VSS94 AH29
+VCC_GFXCORE JCPU1G CONN@ 100_0402_1%~D AR19 VSS15 VSS95 AH28
2
AR16 VSS16 VSS96 AH25
33A AR13 VSS17
VSS18
VSS98
VSS99
AH22
AT24 AK35 VCC_AXG_SENSE <60> AR10 AH19
AT23 VAXG1 VAXG_SENSE AK34 AR7 VSS19 VSS100 AH16
SENSE
LINES
VAXG2 VSSAXG_SENSE VSS_AXG_SENSE <60> VSS20 VSS101
100_0402_1%~D
AT21 AR4 AH7
VAXG3 VSS21 VSS102
1
C AT20 AR2 AH4 C
VAXG4 VSS22 VSS103
RC86
AT18 AP34 AG9
AT17 VAXG5 AP31 VSS23 VSS104 AG8
AR24 VAXG6 AP28 VSS24 VSS105 AG4
AR23 VAXG7 +V_SM_VREF_CNT AP25 VSS25 VSS106 AF6
2
AR21 VAXG8 AP22 VSS26 VSS107 AF5
AR20 VAXG9 AP19 VSS27 VSS108 AF3
AR18 VAXG10 AL1 AP16 VSS28 VSS109 AF2
AR17 VAXG11 SM_VREF AP13 VSS29 VSS110 AE35
AP24 VAXG12 AP10 VSS30 VSS111 AE34
VREF
AP20 VAXG15 B4 +DIMM0_1_VREF_CPU AP1 VSS33 VSS114 AE31
VAXG16 SA_DIMM_VREFDQ +DIMM0_1_VREF_CPU VSS34 VSS115
AP18 D1 +DIMM0_1_CA_CPU +DIMM0_1_CA_CPU AN30 AE30
AP17 VAXG17 SB_DIMM_VREFDQ AN27 VSS35 VSS116 AE29
AN24 VAXG18 CC72 2 1 0.1U_0402_10V7K~D AN25 VSS36 VSS117 AE28
Checking again
AN23
AN21
VAXG19
VAXG20
VAXG21
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
AN20 +1.5V_CPU_VDDQ CC73 2 1 0.1U_0402_10V7K~D AN16 AE9
AN18 VAXG22 AN13 VSS40 VSS121 AD7
AN17 VAXG23 6A AN10 VSS41 VSS122 AC9
DDR3 -1.5V RAILS
AM24 VAXG24 AF7 5A CC74 2 1 0.1U_0402_10V7K~D +1.5V_MEM AN7 VSS42 VSS123 AC8
AM23 VAXG25 VDDQ1 AF4 AN4 VSS43 VSS124 AC6
GRAPHICS
VAXG26 VDDQ2 VSS44 VSS125
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
330U_D2_2VM_R6M~D
AM21 AF1 AM29 AC5
AM20 VAXG27 VDDQ3 AC7 CC82 2 1 0.1U_0402_10V7K~D AM25 VSS45 VSS126 AC3
VAXG28 VDDQ4 1 1 1 1 1 1 1 VSS46 VSS127
CC75
CC76
CC77
CC78
CC79
CC80
CC81
AM18 AC4 AM22 AC2
AM17 VAXG29 VDDQ5 AC1 + AM19 VSS47 VSS128 AB35
AL24 VAXG30 VDDQ6 Y7 AM16 VSS48 VSS129 AB34
AL23 VAXG31 VDDQ7 Y4 2 2 2 2 2 2 AM13 VSS49 VSS130 AB33
AL21 VAXG32 VDDQ8 Y1 2 AM10 VSS50 VSS131 AB32
AL20 VAXG33 VDDQ9 U7 AM7 VSS51 VSS132 AB31
AL18 VAXG34 VDDQ10 U4 AM4 VSS52 VSS133 AB30
B AL17 VAXG35 VDDQ11 U1 AM3 VSS53 VSS134 AB29 B
AK24 VAXG36 VDDQ12 P7 AM2 VSS54 VSS135 AB28
AK23 VAXG37 VDDQ13 P4 AM1 VSS55 VSS136 AB27
AK21 VAXG38 VDDQ14 P1 AL34 VSS56 VSS137 AB26
AK20 VAXG39 VDDQ15 AL31 VSS57 VSS138 Y9
AK18 VAXG40 +VCC_SA AL28 VSS58 VSS139 Y8
AK17 VAXG41 AL25 VSS59 VSS140 Y6
AJ24 VAXG42 AL22 VSS60 VSS141 Y5
1 2 +DIMM0_1_VREF_CPU AJ20 VAXG45 6A AL13 VSS63 VSS144 W35
VAXG46 VSS64 VSS145
330U_D2_2VM_R6M~D
@ RC87 1K_0402_5%~D AJ18 AL10 W34
VAXG47 VSS65 VSS146
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
AJ17 M27 1 AL7 W33
VAXG48 VCCSA1 VSS66 VSS147
@
1 2 +DIMM0_1_CA_CPU AH24 M26 1 1 1 1 AL4 W32
VAXG49 VCCSA2 VSS67 VSS148
SA RAIL
CC83
CC84
CC85
CC86
CC87
@ RC88 1K_0402_5%~D AH23 L26 + AL2 W31
AH21 VAXG50 VCCSA3 J26 AK33 VSS68 VSS149 W30
AH20 VAXG51 VCCSA4 J25 AK30 VSS69 VSS150 W29
AH18 VAXG52 VCCSA5 J24 2 2 2 2 2 AK27 VSS70 VSS151 W28
AH17 VAXG53 VCCSA6 H26 AK25 VSS71 VSS152 W27
VAXG54 VCCSA7 H25 AK22 VSS72 VSS153 W26
VCCSA8 AK19 VSS73 VSS154 U9
AK16 VSS74 VSS155 U8
AK7 VSS77 VSS158 U3
H23 AK4 VSS78 VSS159 U2
1.8V RAIL
VCCSA_SENSE VCCSA_SENSE <59> VSS79 VSS160

+1.8V_RUN AJ25
1.5A VSS80
B6
A6 VCCPLL1 C22
VCCPLL2 VCCSA_VID[0] VCCSA_VID_0 <59>
10U_0603_6.3V6M~D
330U_D2_2.5VM_R6M~D
A2
MISC
1 C24 VCCSA_VID_1 <59>

VCCPLL3 VCCSA_VID[1]
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1 1 1 TYCO_2134146-3_IVYBRIDGE~D
CC88
A + A
Link CIS OK
CC89
CC90
CC91
A19 VCCP_PWRCTRL_R 1 2 0_0402_5%~D VCCP_PWRCTRL <58>

2 2 2 2 VCCIO_SEL
@ RC89
TYCO_2134146-3_IVYBRIDGE~D DELL CONFIDENTIAL/PROPRIETARY
Link CIS OK PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Title
5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com
All VREF traces should
have 10 mil trace width
JDIMM3 (Ch B1 H=9.2 STD)
JDIMM1 STD Type H=5.2 JDIMM1 (Ch A1 H=5.2 STD)

Populate RD1 for Intel DDR3
VREFDQ multiple methods M1
TOP
D
CPU D
@ RD1 +DIMM1_VREF_DQ
1 2 0_0402_5%~D +1.5V_MEM +1.5V_MEM
<8,13> DDR_A_DQS#[0..7] +V_DDR_REFA_M3
<8,13> DDR_A_D[0..63]
1 2 0_0402_5%~D 1
JDIMM1 CONN@
2
BOT
+V_DDR_REF
<8,13> DDR_A_DQS[0..7]
3 VREF_DQ
VSS2
VSS1
DQ4
4 DDR_A_D5 JDIMM2 (Ch A0 H=5.2 REV) JDIMM4 (Ch B0 H=5.2 STD)
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
@ RD2 DDR_A_D0 5 6 DDR_A_D1
DDR_A_D4 7 DQ0 DQ5 8
<8,13> DDR_A_MA[0..15] DQ1 VSS3
1 1 9 10 DDR_A_DQS#0
11 VSS4 DQS#0 12 DDR_A_DQS0
DM0 DQS0
CD1
CD2
13 14
DDR_A_D7 15 VSS5 VSS6 16 DDR_A_D2
+1.5V_MEM 2 2 DQ2 DQ6 +1.5V_MEM
DDR_A_D6 17 18 DDR_A_D3
19 DQ3 DQ7 20
1K_0402_1%~D
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
1
DQ9 DQ13
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
25 26
RD4
DDR_A_DQS#1 27 VSS9 VSS10 28
1 1 1 1 DQS#1 DM1
DDR_A_DQS1 29 30 DDR3_DRAMRST#_R
DQS1 RESET#
CD4
CD5
CD3
CD6
31 32
2
2 2 2 2 DDR_A_D14 35 DQ10 DQ14 36 DDR_A_D11
37 DQ11 DQ15 38
DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20 1 2
<13,14,15> DDR3_DRAMRST#_R DDR3_DRAMRST# <7>
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21 RD3 1K_0402_1%~D
43 DQ17 DQ21 44
DDR_A_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_A_D18
DDR_A_D19 51 VSS18 DQ22 52 DDR_A_D22
+1.5V_MEM DDR_A_D23 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_A_D28 @ RD5 1 2 0_0402_5%~D
DDR_A_D25 59 DQ24 DQ29 60
DQ25 VSS21
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
61 62 DDR_A_DQS#3
D
VSS22 DQS#3 3 1
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
63 64 DDR_A_DQS3 +DIMM0_1_VREF_CPU +V_DDR_REFA_M3

DM3 DQS3
330U_SX_2VY~D
C 1 65 66 C
VSS23 VSS24 QD1
@ CD13
1 1 1 1 1 1 1 DDR_A_D30 67 68 DDR_A_D26
DQ26 DQ30 BSS138-G_SOT23-3
G
CD7
CD8
CD9
CD10
CD11
CD12
CD14
+ DDR_A_D31 69 70 DDR_A_D27
2
71 DQ27 DQ31 72
VSS25 VSS26
<7> DDR_HVREF_RST
2 2 2 2 2 2 2 2
73 74
<8> DDR_CKE4_DIMM1 CKE0 CKE1 DDR_CKE5_DIMM1 <8>
75 76
77 VDD1 VDD2 78 DDR_A_MA15 @ RD6 1 2 0_0402_5%~D
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
<8,13> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
D
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7 +DIMM0_1_CA_CPU 3 1 +V_DDR_REFB_M3
87 A9 A7 88 QD2
DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6 BSS138-G_SOT23-3
A8 A6
G
DDR_A_MA5 91 92 DDR_A_MA4
2
Layout Note: 93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2 DDR_HVREF_RST
Place near JDIMM1.203,204 DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
M_CLK_DDR4 101 VDD9 VDD10 102 M_CLK_DDR5 M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
<8> M_CLK_DDR4 CK0 CK1 M_CLK_DDR5 <8>
M_CLK_DDR#4 103 104 M_CLK_DDR#5
<8> M_CLK_DDR#4 CK0# CK1# M_CLK_DDR#5 <8>
105 106
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <8,13>
DDR_A_BS0 109 110 DDR_A_RAS#
<8,13> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <8,13>
+0.75V_DDR_VTT 111 112
DDR_A_WE# 113 VDD13 VDD14 114
<8,13> DDR_A_WE# WE# S0# DDR_CS4_DIMM1# <8>
DDR_A_CAS# 115 116 M_ODT4
<8,13> DDR_A_CAS# CAS# ODT0 M_ODT4 <8>
117 118
VDD15 VDD16 +DIMM1_VREF_CA
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
DDR_A_MA13 119 120 M_ODT5

A13 ODT1 M_ODT5 <8>
1 1 1 1 121 122
<8> DDR_CS5_DIMM1# S1# NC2
123 124 @ RD7
VDD17 VDD18
CD15
CD16
CD17
CD18
125 126 1 2 0_0402_5%~D

+V_DDR_REF
127 NCTEST VREF_CA 128
2 2 2 2 VSS27 VSS28
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
DDR_A_D36 129 130 DDR_A_D32
DDR_A_D37 131 DQ32 DQ36 132 DDR_A_D33
133 DQ33 DQ37 134
B VSS29 VSS30 1 1 B
CD19
CD20
DDR_A_DQS#4 135 136
139 DQS4 VSS31 140 DDR_A_D38
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39 2 2
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D40
DDR_A_D45 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#5
DIMM Select +3.3V_RUN
DDR_A_D42
153
155
157
VSS36
DM5
VSS37
DQS#5
DQS5
VSS38
154
156
158
DDR_A_DQS5
DDR_A_D46
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
DQ43 DQ47
10K_0402_5%~D
10K_0402_5%~D
161 162
VSS39 VSS40
2
DDR_A_D48 163 164 DDR_A_D52

DQ48 DQ52
@ RD9
DDR_A_D49 165 166 DDR_A_D53

DQ49 DQ53
RD8
167 168
1
173 DQS6 VSS43 174 DDR_A_D50

DIMM1_SA0 DDR_A_D54 175 VSS44 DQ54 176 DDR_A_D51
DIMM1_SA1 DDR_A_D55 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_A_D61
SA0 SA1 DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D60
DQ56 DQ61
10K_0402_5%~D
2
2
10K_0402_5%~D
1 0 DIMM1 DDR_A_D57 183 184

DQ57 VSS47
RD11
@ RD10
185 186 DDR_A_DQS#7

0 0 DIMM2 189 DM7 DQS7 190
1 1 DIMM3
1
+3.3V_RUN DDR_A_D63 193 DQ58 DQ62 194 DDR_A_D59

195 DQ59 DQ63 196
0 1 DIMM4 DIMM1_SA0 197 VSS51 VSS52 198
Remove 0 ohm, due to layout space limitation.
199 SA0 EVENT# 200
VDDSPD SDA DDR_XDP_WAN_SMBDAT <13,14,15,17,18,35,43>
DIMM1_SA1 201 202
SA1 SCL DDR_XDP_WAN_SMBCLK <13,14,15,17,18,35,43>
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
1 1 +0.75V_DDR_VTT 203 204 +0.75V_DDR_VTT

VTT1 VTT2
CD21
CD22
A
205 206 A
G1 G2
2 2 TYCO_2-2013289-1~D
Link CIS OK DELL CONFIDENTIAL/PROPRIETARY

0722 Compal Electronics, Inc.
Title
DDRIII-SODIMM SLOT1
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7931P 1.0

5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com JDIMM3 (Ch B1 H=9.2 STD)
All VREF traces should JDIMM2 REV Type H=5.2 JDIMM1 (Ch A1 H=5.2 STD)

have 10 mil trace width
TOP
+V_DDR_REFA_M3
@ RD14
1 2 0_0402_5%~D +DIMM2_VREF_DQ CPU
+1.5V_MEM +1.5V_MEM
<8,12> DDR_A_DQS#[0..7]
JDIMM2 CONN@
1 2 0_0402_5%~D 1 2
<8,12> DDR_A_D[0..63] +V_DDR_REF
3 VREF_DQ
VSS2
VSS1
DQ4
4 DDR_A_D0 BOT
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
D @ RD15 DDR_A_D5 5 6 DDR_A_D4 D
<8,12> DDR_A_DQS[0..7] DQ0 DQ5 JDIMM2 (Ch A0 H=5.2 REV) JDIMM4 (Ch B0 H=5.2 STD)
1 DDR_A_D1 7 8
DQ1 VSS3
CD26
1 9 10 DDR_A_DQS#0
<8,12> DDR_A_MA[0..15] VSS4 DQS#0
CD23
11 12 DDR_A_DQS0
13 DM0 DQS0 14
2 DDR_A_D2 15 VSS5 VSS6 16 DDR_A_D7
2 DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D6
+1.5V_MEM 19 DQ3 DQ7 20
25 DQ9 DQ13 26
VSS9 VSS10
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
DDR_A_DQS#1 27 28
1 1 1 1 DQS1 RESET# DDR3_DRAMRST#_R <12,14,15>
31 32
VSS11 VSS12
CD27
CD24
CD25
CD28
DDR_A_D10 33 34 DDR_A_D15
2 2 2 2 37 DQ11 DQ15 38
43 DQ17 DQ21 44
49 DQS2 VSS17 50 DDR_A_D19
DDR_A_D22 53 DQ18 DQ23 54
+1.5V_MEM 55 DQ19 VSS19 56 DDR_A_D24
DDR_A_D29 59 DQ24 DQ29 60
VSS22 DQS#3
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
63 64 DDR_A_DQS3
65 DM3 DQS3 66
VSS23 VSS24
330U_SX_2VY~D
1 DDR_A_D26 67 68 DDR_A_D30
DQ26 DQ30
@ CD35
1 1 1 1 1 1 1 DDR_A_D27 69 70 DDR_A_D31
DQ27 DQ31
CD29
CD30
CD31
CD32
CD33
CD34
CD36
+ 71 72
VSS25 VSS26
C C
2 2 2 2 2 2 2 2
73 74
75 76
77 VDD1 VDD2 78 DDR_A_MA15
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
<8,12> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
Layout Note: DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
Place near JDIMM3.Pin 203,204 DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
M_CLK_DDR0 101 VDD9 VDD10 102 M_CLK_DDR1
105 106
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <8,12>
DDR_A_BS0 109 110 DDR_A_RAS#
<8,12> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <8,12>
+0.75V_DDR_VTT 111 112
DDR_A_WE# 113 VDD13 VDD14 114
<8,12> DDR_A_WE# WE# S0# DDR_CS0_DIMM2# <8>
DDR_A_CAS# 115 116 M_ODT0
<8,12> DDR_A_CAS# CAS# ODT0 M_ODT0 <8>
117 118
DDR_A_MA13 119 VDD15 VDD16 120 M_ODT1 +DIMM2_VREF_CA
A13 ODT1 M_ODT1 <8>
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
121 122
1 1 1 1 123 124 @ RD16
125 VDD17 VDD18 126 1 2 0_0402_5%~D
NCTEST VREF_CA +V_DDR_REF
CD37
CD38
CD39
CD40
127 128
VSS27 VSS28
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
DDR_A_D32 129 130 DDR_A_D36
2 2 2 2 DDR_A_D33 131 DQ32 DQ36 132 DDR_A_D37
133 DQ33 DQ37 134
VSS29 VSS30 1 1
CD41
CD42
DDR_A_DQS#4 135 136
B B
139 DQS4 VSS31 140 DDR_A_D34
DDR_A_D38 141 VSS32 DQ38 142 DDR_A_D35 2 2
DDR_A_D39 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D44
DDR_A_D41 149 DQ40 DQ45 150
DDR_A_D46
DDR_A_D47
155
157
159
DM5
VSS37
DQ42
DQS5
VSS38
DQ46
156
158
160
DDR_A_D42
DDR_A_D43
161 DQ43 DQ47 162
VSS39 VSS40
2
10K_0402_5%~D
10K_0402_5%~D
DDR_A_D52 163 164 DDR_A_D48

DQ48 DQ52
2
DDR_A_D53 165 166 DDR_A_D49

DQ49 DQ53
@
167 168
VSS41 VSS42
RD18
RD17
DDR_A_DQS#6 169 170

1
173 DQS6 VSS43 174 DDR_A_D54

1

DIMM2_SA0 DDR_A_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_A_D56
DIMM2_SA1 DDR_A_D61 181 VSS46 DQ60 182 DDR_A_D57
SA0 SA1 DDR_A_D60 183 DQ56 DQ61 184
DQ57 VSS47
2
2
10K_0402_5%~D
10K_0402_5%~D
0 DIMM1 185 186 DDR_A_DQS#7

1 187 VSS48 DQS#7 188 DDR_A_DQS7
RD19
DM7 DQS7
RD20
189 190
0 0 DIMM2 DDR_A_D58 191 VSS49 VSS50 192 DDR_A_D62
+3.3V_RUN DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
1 1 DIMM3
1
195 DQ59 DQ63 196

DIMM2_SA0 197 VSS51 VSS52 198
Remove 0 ohm, due to layout space limitation.
0 1 DIMM4 199 SA0 EVENT# 200
DIMM2_SA1 201 202
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
1 1 +0.75V_DDR_VTT 203 204 +0.75V_DDR_VTT

VTT1 VTT2
A A
CD43
CD44
205 206
G1 G2
2 2 TYCO_2-2013290-1
Link CIS OK
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDRIII-SODIMM SLOT2
5 4
WWW.AliSaler.Com 3
2
Size
Date:
Document Number

LA-7931P
1
Sheet 13 of 70
Rev
1.0
5 4 3 2 1
WWW.AliSaler.Com
@ RD23
JDIMM3 STD Type H=9.2
1 2 0_0402_5%~D +DIMM3_VREF_DQ JDIMM1 (Ch A1 H=5.2 STD)
+V_DDR_REFB_M3 +1.5V_MEM +1.5V_MEM
JDIMM3 CONN@ TOP
+V_DDR_REF 1 2 0_0402_5%~D 1
3 VREF_DQ VSS1
2
4 DDR_B_D0
CPU
VSS2 DQ4
0.1U_0402_16V4Z~D
@ RD24 DDR_B_D4 5 6 DDR_B_D1
<8,15> DDR_B_DQS#[0..7] DQ0 DQ5
2.2U_0402_6.3V6M~D
D 1 DDR_B_D5 7 8 D
DQ1 VSS3
CD45
1 9 10 DDR_B_DQS#0
<8,15> DDR_B_D[0..63] VSS4 DQS#0 BOT
CD46
11 12 DDR_B_DQS0
13 DM0 DQS0 14
<8,15> DDR_B_DQS[0..7] 2 VSS5 VSS6 JDIMM2 (Ch A0 H=5.2 REV) JDIMM4 (Ch B0 H=5.2 STD)
DFX issue solution. DDR_B_D2 15 16 DDR_B_D6
2 DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D7
<8,15> DDR_B_MA[0..15] DQ3 DQ7
19 20
DDR_B_D12 21 VSS7 VSS8 22 DDR_B_D8
DDR_B_D13 23 DQ8 DQ12 24 DDR_B_D9
25 DQ9 DQ13 26
DDR_B_DQS#1 27 VSS9 VSS10 28
DDR_B_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#_R
DQS1 RESET# DDR3_DRAMRST#_R <12,13,15>
All VREF traces should 31 32
+1.5V_MEM have 10 mil trace width DDR_B_D15 35 DQ10 DQ14 36 DDR_B_D11
37 DQ11 DQ15 38
DDR_B_D17 41 DQ16 DQ20 42 DDR_B_D21
DQ17 DQ21
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
43 44
1 1 1 1 DQS#2 DM2
DDR_B_DQS2 47 48
DQS2 VSS17
CD47
CD48
CD49
CD50
49 50 DDR_B_D18
DDR_B_D22 51 VSS18 DQ22 52 DDR_B_D19
2 2 2 2 DDR_B_D23 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D28
DDR_B_D29 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_B_DQS#3
63 VSS22 DQS#3 64 DDR_B_DQS3
65 DM3 DQS3 66
+1.5V_MEM DDR_B_D31 69 DQ26 DQ30 70 DDR_B_D27
71 DQ27 DQ31 72
VSS25 VSS26
C C
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
73 74
330U_SX_2VY~D
1 75 76
VDD1 VDD2
@ CD57
1 1 1 1 1 1 1 77 78 DDR_B_MA15
NC1 A15
CD51
CD52
CD53
CD54
CD55
CD56
CD58
+ DDR_B_BS2 79 80 DDR_B_MA14
<8,15> DDR_B_BS2 BA2 A14
81 82
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
2 2 2 2 2 2 2 2 DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
99 A1 A0 100
M_CLK_DDR6 101 VDD9 VDD10 102 M_CLK_DDR7
Layout Note: <8> M_CLK_DDR#6
105 CK0# CK1# 106
M_CLK_DDR#7 <8>
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
Place near JDIMM3.Pin 203,204 DDR_B_BS0 109 A10/AP BA1 110 DDR_B_RAS#
DDR_B_BS1 <8,15>
<8,15> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <8,15>
111 112
DDR_B_WE# 113 VDD13 VDD14 114
<8,15> DDR_B_WE# WE# S0# DDR_CS6_DIMM3# <8>
DDR_B_CAS# 115 116 M_ODT6
<8,15> DDR_B_CAS# CAS# ODT0 M_ODT6 <8>
117 118
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT7
A13 ODT1 M_ODT7 <8>
+DIMM3_VREF_CA
121 122
123 124 @ RD25
+0.75V_DDR_VTT 125 VDD17 VDD18 126 1 2 0_0402_5%~D
127 128
VSS27 VSS28
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
DDR_B_D36 129 130 DDR_B_D32
DDR_B_D37 131 DQ32 DQ36 132 DDR_B_D33
133 DQ33 DQ37 134
VSS29 VSS30 1 1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD63
CD64
DDR_B_DQS#4 135 136
DDR_B_DQS4 137 DQS#4 DM4 138
1 1 1 1 DQS4 VSS31
B 139 140 DDR_B_D38 B
VSS32 DQ38 2 2
CD59
CD60
CD61
CD62
DDR_B_D34 141 142 DDR_B_D39

DDR_B_D35 143 DQ34 DQ39 144
2 2 2 2 145 DQ35 VSS33 146 DDR_B_D40
DDR_B_D45 149 DQ40 DQ45 150
155 DM5 DQS5 156
DDR_B_D47 159 DQ42 DQ46 160 DDR_B_D43
161 DQ43 DQ47 162
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53
167 DQ49 DQ53 168
DDR_B_D54
DDR_B_D55
173
175
177
DQS6
VSS44
DQ50
VSS43
DQ54
DQ55
174
176
178
DDR_B_D50
DDR_B_D51
179 DQ51 VSS45 180 DDR_B_D60

VSS46 DQ60
10K_0402_5%~D
10K_0402_5%~D
DDR_B_D56 181 182 DDR_B_D61

DQ56 DQ61
2
2
RD27
DDR_B_D57 183 184

DQ57 VSS47
RD26
185 186 DDR_B_DQS#7

189 DM7 DQS7 190
1
+3.3V_RUN DDR_B_D63 193 DQ58 DQ62 194 DDR_B_D59

DIMM3_SA0 195 DQ59 DQ63 196
DIMM3_SA0 197 VSS51 VSS52 198
DIMM3_SA1 199 SA0 EVENT# 200
SA0 SA1 DIMM3_SA1 201 VDDSPD SDA 202
DDR_XDP_WAN_SMBDAT <12,13,15,17,18,35,43>
2
2
10K_0402_5%~D
10K_0402_5%~D
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
203 204
1 0 DIMM1 +0.75V_DDR_VTT VTT1 VTT2 +0.75V_DDR_VTT
1 1
@ RD28
@ RD29
0 0 205 206
A DIMM2 G1 G2 Due to +PWR_SRC trace width nearby H16 wasn’t A
CD65
CD66
1 1 DIMM3 TYCO_2-2013310-1~D enough, we have to increase it.so remove RD30 & RD31.

1
2 2
0 1 DIMM4
Link CIS OK_1006 DELL CONFIDENTIAL/PROPRIETARY

follow connector list 1005A. Compal Electronics, Inc.
Title
5 4
WWW.AliSaler.Com 3
2
Size
Date:
Document Number

LA-7931P
1
Sheet 14 of 70
Rev
1.0
5 4 3 2 1
WWW.AliSaler.Com
All VREF traces should
have 10 mil trace width JDIMM4 STD Type H=5.2
@ RD32
1 2 0_0402_5%~D +DIMM4_VREF_DQ
+V_DDR_REFB_M3 +1.5V_MEM +1.5V_MEM
<8,14> DDR_B_DQS#[0..7]
JDIMM4 CONN@
1 2 0_0402_5%~D 1 2
JDIMM1 (Ch A1 H=5.2 STD)
<8,14> DDR_B_D[0..63] +V_DDR_REF VREF_DQ VSS1
3 4 DDR_B_D4
VSS2 DQ4 TOP
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
D @ RD33 DDR_B_D0 5 6 DDR_B_D5 D
<8,14> DDR_B_DQS[0..7] DQ0 DQ5
1 DDR_B_D1 7
DQ1 VSS3
8
CPU
CD71
1 9 10 DDR_B_DQS#0
<8,14> DDR_B_MA[0..15] VSS4 DQS#0
CD72
11 12 DDR_B_DQS0
13 DM0 DQS0 14
2 DDR_B_D6 15 VSS5 VSS6 16 DDR_B_D2
2 DDR_B_D7 17
19
DQ2
DQ3
DQ6
DQ7
18
20
DDR_B_D3 BOT
DDR_B_D8 21 VSS7
DQ8
VSS8
DQ12
22 DDR_B_D12 JDIMM2 (Ch A0 H=5.2 REV) JDIMM4 (Ch B0 H=5.2 STD)
+1.5V_MEM DDR_B_D9 23 24 DDR_B_D13
25 DQ9 DQ13 26
DDR_B_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#_R
DQS1 RESET# DDR3_DRAMRST#_R <12,13,14>
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
31 32
1 1 1 1 DQ10 DQ14
DDR_B_D11 35 36 DDR_B_D15
DQ11 DQ15
CD67
CD68
CD69
CD70
37 38
2 2 2 2 DDR_B_D21 41 DQ16 DQ20 42 DDR_B_D17
43 DQ17 DQ21 44
49 DQS2 VSS17 50 DDR_B_D22
DDR_B_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D24
+1.5V_MEM DDR_B_D28 57 VSS20 DQ28 58 DDR_B_D29
DDR_B_D25 59 DQ24 DQ29 60
65 DM3 DQS3 66
VSS23 VSS24
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
DDR_B_D26 67 68 DDR_B_D30
DQ26 DQ30
330U_SX_2VY~D
1 DDR_B_D27 69 70 DDR_B_D31
DQ27 DQ31
@ CD79
1 1 1 1 1 1 1 71 72
VSS25 VSS26
CD73
CD74
CD75
CD76
CD77
CD78
CD80
+
C C
2 2 2 2 2 2 2 2 73 74
75 76
77 VDD1 VDD2 78 DDR_B_MA15
DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
<8,14> DDR_B_BS2 BA2 A14
81 82
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
93 A5 A4 94
Layout Note: DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
Place near JDIMM3.Pin 203,204 M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3
105 106
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <8,14>
DDR_B_BS0 109 110 DDR_B_RAS#
<8,14> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <8,14>
111 112
DDR_B_WE# 113 VDD13 VDD14 114
<8,14> DDR_B_WE# WE# S0# DDR_CS2_DIMM4# <8>
DDR_B_CAS# 115 116 M_ODT2
<8,14> DDR_B_CAS# CAS# ODT0 M_ODT2 <8>
+0.75V_DDR_VTT 117 118
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3
A13 ODT1 M_ODT3 <8>
+DIMM4_VREF_CA
121 122
123 124 @ RD34
125 VDD17 VDD18 126 1 2 0_0402_5%~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
127 128
VSS27 VSS28
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
1 1 1 1 DDR_B_D32 129 130 DDR_B_D36
DDR_B_D33 131 DQ32 DQ36 132 DDR_B_D37
DQ33 DQ37
CD81
CD82
CD83
CD84
133 134 1 1
VSS29 VSS30
CD85
CD86
DDR_B_DQS#4 135 136
2 2 2 2 DDR_B_DQS4 137 DQS#4 DM4 138
B B
139 DQS4 VSS31 140 DDR_B_D34
DDR_B_D38 141 VSS32 DQ38 142 DDR_B_D35 2 2
DDR_B_D39 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D44
DDR_B_D41 149 DQ40 DQ45 150
155 DM5 DQS5 156
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47
161 DQ43 DQ47 162
DDR_B_D52
DDR_B_D53
163
165
167
VSS39
DQ48
DQ49
VSS40
DQ52
DQ53
164
166
168
DDR_B_D48
DDR_B_D49

173 DQS6 VSS43 174 DDR_B_D54
VSS44 DQ54
2
2
10K_0402_5%~D
10K_0402_5%~D
DDR_B_D50 175 176 DDR_B_D55

DDR_B_D51 177 DQ50 DQ55 178
DQ51 VSS45
@
RD36
179 180 DDR_B_D56

VSS46 DQ60
RD35
DDR_B_D60 181 182 DDR_B_D57

DDR_B_D61 183 DQ56 DQ61 184
1

DIMM4_SA0 189 DM7 DQS7 190
DIMM4_SA1 +3.3V_RUN DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63
SA0 SA1 195 DQ59 DQ63 196
VSS51 VSS52
2
2
10K_0402_5%~D
10K_0402_5%~D
DIMM4_SA0 197 198

1 0 DIMM1 199 SA0 EVENT# 200 DIMM4_SMBDAT @ RD39 1 2 0_0402_5%~D
@
DIMM4_SA1 201 202 DIMM4_SMBCLK @ RD40 1 2 0_0402_5%~D

0 0 DIMM2 SA1 SCL DDR_XDP_WAN_SMBCLK <12,13,14,17,18,35,43>
RD37
RD38
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
+0.75V_DDR_VTT 203 204 +0.75V_DDR_VTT

VTT1 VTT2
1 1 DIMM3 1 1
1
A A
205 206
G1 G2
CD87
CD88
0 1 DIMM4 TYCO_2-2013289-1~D
2 2
Link CIS OK
Title
5 4
WWW.AliSaler.Com 3
2
Size
Date:
Document Number

LA-7931P
1
Sheet 15 of 70
Rev
1.0
5 4 3 2 1
WWW.AliSaler.Com +3.3V_MXM
+3.3V_MXM
+3.3V_MXM
4.7K_0402_5%~D
4.7K_0402_5%~D
1
1
+3.3V_MXM
@
10K_0402_5%~D
R1
R2
PEG_CRX_GTX_C_P[0..15]
<6> PEG_CRX_GTX_C_P[0..15]
1
1 2 MXM_CRT_DDC_DAT
2
R4
PEG_CRX_GTX_C_N[0..15] @ R3 4.3K_0402_5%
<6> PEG_CRX_GTX_C_N[0..15]
2
1 2 MXM_CRT_DDC_CLK
PEG_CTX_GRX_P[0..15] @ R5 4.3K_0402_5% GPU_SMBDAT_R 1 6 GPU_SMBDAT <49>
<6> PEG_CTX_GRX_P[0..15]
2
G
1 2 DGPU_PWR_GOOD
2
PEG_CTX_GRX_N[0..15] R8 10K_0402_5%~D Q295A
<6> PEG_CTX_GRX_N[0..15]
5
1 2 MXM_CLK_REQ# MXM_ALERT# 3 1 DGPU_ALERT# <48> DMN66D0LDW-7_SOT363-6~D
R7 10K_0402_5%~D
D
GPU_SMBCLK_R 4 3
D Q5 GPU_SMBCLK <49> D
SSM3K7002FU_SC70-3~D Q295B
+MXM_PWR_SRC Height limitation issue. +MXM_PWR_SRC

JMXM1A CONN@ 400mil(10A)
1 2 JMXM1B CONN@
3 PWR_SRC PWR_SRC 4 163 162
PWR_SRC PWR_SRC GND GND
10U_0805_25V6K~D
680P_0603_50V7K~D
68P_0402_50V8J~D
0.1U_0603_25V7K~D
5 6 PEG_CRX_GTX_C_N2 165 164 PEG_CTX_GRX_N2
7 PWR_SRC PWR_SRC 8 PEG_CRX_GTX_C_P2 167 PEX_RX2# PEX_TX2# 166 PEG_CTX_GRX_P2
PWR_SRC PWR_SRC 1 1 1 1 PEX_RX2 PEX_TX2
9 10 169 168
PWR_SRCE1 E2 PWR_SRC GND GND
C2
C3
C4
C1
11 12 PEG_CRX_GTX_C_N1 171 170 PEG_CTX_GRX_N1
13 PWR_SRC PWR_SRC 14 PEG_CRX_GTX_C_P1 173 PEX_RX1# PEX_TX1# 172 PEG_CTX_GRX_P1
15 PWR_SRC PWR_SRC 16 2 2 2 2 175 PEX_RX1 PEX_TX1 174
17 PWR_SRC PWR_SRC 18 PEG_CRX_GTX_C_N0 177 GND GND 176 PEG_CTX_GRX_N0
PWR_SRC PWR_SRC PEG_CRX_GTX_C_P0 179 PEX_RX0# PEX_TX0# 178 PEG_CTX_GRX_P0
181 PEX_RX0 PEX_TX0 180
19 20 CLK_PCIE_VGA# 183 GND GND 182 MXM_CLK_REQ#
+5V_MXM GND GND <18> CLK_PCIE_VGA# PEX_REFCLK# PEX_CLK_REQ#
21 22 CLK_PCIE_VGA 185 184 DGPU_PEX_RST#
GND GND <18> CLK_PCIE_VGA PEX_REFCLK PEX_RST#
23 24 187 186 MXM_CRT_DDC_DAT <32>
25 GND GND 26 189 GND VGA_DDC_DAT 188
GND GND RSVD VGA_DDC_CLK MXM_CRT_DDC_CLK <32> CRT
0.1U_0402_16V4Z~D
10U_0603_6.3V6M~D
27 28 2011/09/01 change. 191 190 MXM_CRT_VSYNC MXM_CRT_VSYNC <32>

29 GND GND 30 193 RSVD VGA_VSYNC 192 MXM_CRT_HSYNC
1 1 GND E3 E4 GND RSVD VGA_HSYNC MXM_CRT_HSYNC <32>
C328
31 32 195 194
+5V_MXM GND GND RSVD GND
C7
33 34 197 196 MXM_CRT_RED MXM_CRT_RED <32>

35 GND GND 36 MXM_LVDS_BCLK- 199 RSVD VGA_RED 198 MXM_CRT_GRN
2 2 GND GND <27> MXM_LVDS_BCLK- LVDS_UCLK# VGA_GREEN MXM_CRT_GRN <32>
37 38 MXM_PRESENTR# <21> <27> MXM_LVDS_BCLK+ MXM_LVDS_BCLK+ 201 200 MXM_CRT_BLU MXM_CRT_BLU <32>
39 5V PRSNT_R# 40 @ R1972 1 2 0_0402_5%~D 203 LVDS_UCLK VGA_BLUE 202
5V WAKE# PCIE_WAKE# <42,43,47,49> GND GND 2011/09/01 change.
41 42 DGPU_PWR_GOOD 205 204 MXM_LVDS_ACLK- MXM_LVDS_ACLK- <27>
43 5V PWR_GOOD 44 207 LVDS_UTX3# LVDS_LCLK# 206 MXM_LVDS_ACLK+
5V PWR_EN DGPU_PWR_EN <48> LVDS_UTX3 LVDS_LCLK MXM_LVDS_ACLK+ <27>
45 46 209 208
47 5V RSVD 48 MXM_LVDS_B2- 211 GND GND 210
GND RSVD <27> MXM_LVDS_B2- LVDS_UTX2# LVDS_LTX3#
100mil(2.5A, 5VIA) 49 50 MXM_LVDS_B2+ 213 212
51 GND RSVD 52
<27> MXM_LVDS_B2+
215 LVDS_UTX2 LVDS_LTX3 214 LVDS_Lower/odd
53 GND RSVD 54 MXM_PWR_LEVEL LVDS_Upper/even <27> MXM_LVDS_B1- MXM_LVDS_B1- 217 GND GND 216 MXM_LVDS_A2- MXM_LVDS_A2- <27>
@ R1970 1 2 0_0402_5%~D 55 GND PWR_LEVEL 56 MXM_OVERT# MXM_LVDS_B1+ 219 LVDS_UTX1# LVDS_LTX2# 218 MXM_LVDS_A2+
PEX_STD_SW# TH_OVERT# <27> MXM_LVDS_B1+ LVDS_UTX1 LVDS_LTX2 MXM_LVDS_A2+ <27>
@ R1971 1 2 0_0402_5%~D 57 58 MXM_ALERT# 221 220
59 VGA_DISABLE# TH_ALERT# 60 MXM_LVDS_B0- 223 GND GND 222 MXM_LVDS_A1-
<28> MXM_ENVDD PNL_PWR_EN TH_PWM <27> MXM_LVDS_B0- LVDS_UTX0# LVDS_LTX1# MXM_LVDS_A1- <27>
<28> MXM_PANEL_BKEN 61 62 <27> MXM_LVDS_B0+ MXM_LVDS_B0+ 225 224 MXM_LVDS_A1+ MXM_LVDS_A1+ <27>
C 63 PNL_BL_EN GPIO0 64 227 LVDS_UTX0 LVDS_LTX1 226 C
<28> MXM_BIA_PWM PNL_BL_PWM GPIO1 GND GND
65 66 <34> MXM_DPC_N0 MXM_DPC_N0 229 228 MXM_LVDS_A0- MXM_LVDS_A0- <27>
67 HDMI_CEC GPIO2 68 GPU_SMBDAT_R MXM_DPC_P0 231 DP_C_L0# LVDS_LTX0# 230 MXM_LVDS_A0+
DVI_HPD SMB_DAT <34> MXM_DPC_P0 DP_C_L0 LVDS_LTX0 MXM_LVDS_A0+ <27>
<27> MXM_LVDS_DDC_DAT 69 70 GPU_SMBCLK_R 233 232
71 LVDS_DDC_DAT SMB_CLK 72 MXM_DPC_N1 235 GND GND 234 MXM_EDP_TX0-
<27> MXM_LVDS_DDC_CLK LVDS_DDC_CLK GND
SYSTEM <34> MXM_DPC_N1 DP_C_L1# DP_D_L0# MXM_EDP_TX0- <30>
73 74 <34> MXM_DPC_P1 MXM_DPC_P1 237 236 MXM_EDP_TX0+ MXM_EDP_TX0+ <30>
75 GND OEM 76 239 DP_C_L1 DP_D_L0 238
77 OEM OEM 78 MXM_DPC_N2 241 GND GND 240 MXM_EDP_TX1-
79 OEM OEM 80 HDMI/Docking DP <34> MXM_DPC_N2
<34> MXM_DPC_P2 MXM_DPC_P2 243 DP_C_L2# DP_D_L1# 242 MXM_EDP_TX1+
MXM_EDP_TX1- <30>
MXM_EDP_TX1+ <30>
81 OEM OEM 82 245 DP_C_L2 DP_D_L1 244
83 OEM GND 84 PEG_CTX_GRX_N15 MUX <34> MXM_DPC_N3 MXM_DPC_N3 247 GND GND 246
PEG_CRX_GTX_C_N15 85 GND PEX_TX15# 86 PEG_CTX_GRX_P15 MXM_DPC_P3 249 DP_C_L3# DP_D_L2# 248
PEG_CRX_GTX_C_P15 87 PEX_RX15# PEX_TX15 88
<34> MXM_DPC_P3
251 DP_C_L3 DP_D_L2 250 eDP
89 PEX_RX15 GND 90 PEG_CTX_GRX_N14 MXM_DPC_AUX# 253 GND GND 252
GND PEX_TX14# <34,45> MXM_DPC_AUX# DP_C_AUX# DP_D_L3#
PEG_CRX_GTX_C_N14 91 92 PEG_CTX_GRX_P14 <34,45> MXM_DPC_AUX MXM_DPC_AUX 255 254
PEG_CRX_GTX_C_P14 93 PEX_RX14# PEX_TX14 94 257 DP_C_AUX DP_D_L3 256
95 PEX_RX14 GND 96 PEG_CTX_GRX_N13 259 RSVD GND 258 MXM_EDP_C_AUX- 6@ C1297 1 2 0.1U_0402_10V6K~D
GND PEX_TX13# RSVD DP_D_AUX# MXM_EDP_AUX- <30>
PEG_CRX_GTX_C_N13 97 98 PEG_CTX_GRX_P13 261 260 MXM_EDP_C_AUX+ 6@ C1298 1 2 0.1U_0402_10V6K~D MXM_EDP_AUX+ <30>
PEG_CRX_GTX_C_P13 99 PEX_RX13# PEX_TX13 100 263 RSVD DP_D_AUX 262 MXM_DPC_HPD_GATE
101 PEX_RX13 GND 102 PEG_CTX_GRX_N12 265 RSVD DP_C_HPD 264 MXM_EDP_HPD
GND PEX_TX12# RSVD DP_D_HPD MXM_EDP_HPD <30>
PEG_CRX_GTX_C_N12 103 104 PEG_CTX_GRX_P12 267 266
PEG_CRX_GTX_C_P12 105 PEX_RX12# PEX_TX12 106 269 RSVD RSVD 268 R2194 1 @ 2 0_0402_5%~D
PEX_RX12 GND RSVD RSVD +3.3V_MXM
107 108 PEG_CTX_GRX_N11 271 270 R2195 1 @ 2 0_0402_5%~D For NVDIA request.
PEG_CRX_GTX_C_N11 109 GND PEX_TX11# 110 PEG_CTX_GRX_P11 273 RSVD RSVD 272
PEG_CRX_GTX_C_P11 111 PEX_RX11# PEX_TX11 112 275 RSVD GND 274 MXM_DPB_N0
PEX_RX11 GND RSVD DP_B_L0# MXM_DPB_N0 <46>
113 114 PEG_CTX_GRX_N10 277 276 MXM_DPB_P0 MXM_DPB_P0 <46>
PEG_CRX_GTX_C_N10 115 GND PEX_TX10# 116 PEG_CTX_GRX_P10 279 RSVD DP_B_L0 278
PEG_CRX_GTX_C_P10 117 PEX_RX10# PEX_TX10 118 281 RSVD GND 280 MXM_DPB_N1
PEX_RX10 GND GND DP_B_L1# MXM_DPB_N1 <46>
119 120 PEG_CTX_GRX_N9 <29> MXM_MB_DP_N0 MXM_MB_DP_N0 283 282 MXM_DPB_P1 MXM_DPB_P1 <46>
PEG_CRX_GTX_C_N9 121 GND PEX_TX9# 122 PEG_CTX_GRX_P9 MXM_MB_DP_P0 285 DP_A_L0# DP_B_L1 284
<29> MXM_MB_DP_P0
287 DP_A_L0 GND 286 MXM_DPB_N2 MXM_DPB_N2 <46>
DMC/ Docking DP
125 PEX_RX9 GND 126 PEG_CTX_GRX_N8 MXM_MB_DP_N1 289 GND DP_B_L2# 288 MXM_DPB_P2
PEG_CRX_GTX_C_N8 127 GND PEX_TX8# 128 PEG_CTX_GRX_P8
<29> MXM_MB_DP_N1
<29> MXM_MB_DP_P1 MXM_MB_DP_P1 291 DP_A_L1# DP_B_L2 290
MXM_DPB_P2 <46> MUX
PEG_CRX_GTX_C_P8 129 PEX_RX8# PEX_TX8 130 293 DP_A_L1 GND 292 MXM_DPB_N3
PEX_RX8 GND GND DP_B_L3# MXM_DPB_N3 <46>
131 132 PEG_CTX_GRX_N7 <29> MXM_MB_DP_N2 MXM_MB_DP_N2 295 294 MXM_DPB_P3 MXM_DPB_P3 <46>
PEG_CRX_GTX_C_N7 133 GND PEX_TX7# 134 PEG_CTX_GRX_P7 MXM_MB_DP_P2 297 DP_A_L2# DP_B_L3 296
PEG_CRX_GTX_C_P7 135 PEX_RX7# PEX_TX7 136 MB DP <29> MXM_MB_DP_P2
299 DP_A_L2 GND 298 MXM_DPB_AUX# MXM_DPB_AUX# <33>
137 PEX_RX7 GND 138 PEG_CTX_GRX_N6 MXM_MB_DP_N3 301 GND DP_B_AUX# 300 MXM_DPB_AUX
GND PEX_TX6# <29> MXM_MB_DP_N3 DP_A_L3# DP_B_AUX MXM_DPB_AUX <33>
PEG_CRX_GTX_C_N6 139 140 PEG_CTX_GRX_P6 <29> MXM_MB_DP_P3 MXM_MB_DP_P3 303 302 DPC_GPU_HPD_GATE
PEG_CRX_GTX_C_P6 141 PEX_RX6# PEX_TX6 142 305 DP_A_L3 DP_B_HPD 304 MXM_MB_DP_HPD_GATE
143 PEX_RX6 GND 144 PEG_CTX_GRX_N5 MXM_MB_DP_AUX# 307 GND DP_A_HPD 306
GND PEX_TX5# <29> MXM_MB_DP_AUX# DP_A_AUX# 3V3 +3.3V_MXM
PEG_CRX_GTX_C_N5 145 146 PEG_CTX_GRX_P5 <29> MXM_MB_DP_AUX MXM_MB_DP_AUX 309 308
B PEG_CRX_GTX_C_P5 147 PEX_RX5# PEX_TX5 148 MXM_PRESENTL# 310 DP_A_AUX 3V3 B
PEX_RX5 GND <21> MXM_PRESENTL# PRSNT_L# 40mil(1A)
149
GND PEX_TX4#
150 PEG_CTX_GRX_N4 change from +3.3V_RUN to +3.3V_AVDD.
PEG_CRX_GTX_C_N4 151 152 PEG_CTX_GRX_P4 311 312
PEG_CRX_GTX_C_P4 153 PEX_RX4# PEX_TX4 154 GND GND +3.3V_AVDD
155 PEX_RX4 GND 156 PEG_CTX_GRX_N3 JAE_MM70-314-310B1-1-R300 6@ R2095
PEG_CRX_GTX_C_N3 157 GND PEX_TX3# 158 PEG_CTX_GRX_P3 MXM_EDP_AUX- 1 2 100K_0402_5%~D
Link CIS OK
161 PEX_RX3 GND MXM_EDP_AUX+ 1 2 100K_0402_5%~D
GND
6@ R2096
JAE_MM70-314-310B1-1-R300
+3.3V_MXM
change to 6@ for only 10-bit panel use.
Link CIS OK +3.3V_RUN
0.1U_0402_10V7K~D
+3.3V_MXM
0.1U_0402_10V7K~D
+3.3V_MXM
0.1U_0402_10V7K~D
1
1
0722
C1329
1
C91
2
C1328
10U_0603_6.3V6M~D
0.1U_0402_16V4Z~D
5
2
1 1
5
+3.3V_ALW +3.3V_RUN 2 1 DGPU_PWROK
P
IN1
5
0.1U_0402_10V7K~D
C332
C8
1 DGPU_PWR_GOOD MXM_MB_DP_HPD_GATE 4
P
IN1 O
100K_0402_5%~D
<21,48> DGPU_PWROK 4 1 DGPU_PWROK 2

P
O IN1 IN2 MXM_MB_DP_HPD <29>
G
1
+3.3V_MXM 2 DGPU_PWR_EN MXM_DPC_HPD_GATE 4 U639 2 2

1 IN2 O
G
U8 2 74AHC1G08GW_SOT353-5~D
MXM_DPC_HPD <34>
3
IN2
G
2
C90
R36
74AHC1G08GW_SOT353-5~D
3
2
100K_0402_5%~D
@ R2124
RV29 U640
3
750_0402_1%~D 2 74AHC1G08GW_SOT353-5~D
2
5
1
G VCC
DGPU_HOLD_RST# <21>
1
DGPU_PEX_RST# 4 B +3.3V_MXM
1
Y 2
A PLTRST_GPU# <20> +3.3V_MXM +3.3V_ALW
Meet high level for DGPU_PEX_RST# U16 +3.3V_ALW
3
on N14P
0.1U_0402_10V7K~D
MC74VHC1G09DFT2G_SC70-5
100K_0402_5%~D
10K_0402_5%~D
1
1
+3.3V_MXM
10K_0402_5%~D
1
1
0.1U_0402_10V7K~D
R2063
C1264
R10
R11
1 2
2
2
2
C1330
G
A A
2
5
DV2
MXM_DPC_HPD 2 1 2 1 MXM_OVERT# 3 1 DGPU_THERMTRIP# <25>
G VCC
MXM_DP_HDMI_HPD <48> B ACAV_IN <25,49,62,63>

5
MXM_PWR_LEVEL 4
D
RB751VM-40TE-17_SOD323-2~D 1 DGPU_PWROK Y 2
P
IN1 A GPU_PWR_LEVEL <48> Q4

DPC_GPU_HPD_GATE 4
DV3 O 2 U634 SSM3K7002FU_SC70-3~D
DPC_GPU_HPD <46>
3
IN2
G
MXM_MB_DP_HPD 2 1 D102 @ MC74VHC1G09DFT2G_SC70-5

2
100K_0402_5%~D
@ R758
U641 <26,49> DYN_TURB_GPU_PWR_ALRT# 1 2

3
RB751VM-40TE-17_SOD323-2~D 74AHC1G08GW_SOT353-5~D
DV4
RB751VM-40TE-17_SOD323-2~D DELL CONFIDENTIAL/PROPRIETARY
DPC_GPU_HPD 2 1
1
RB751VM-40TE-17_SOD323-2~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
MXM3
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LA-7931P
5 4 3 2 1
5 4 3 2 1
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Pop them until ST.
Pop them until ST. +3.3V_ALW_PCH JXDP2
1 2
+3.3V_ALW_PCH 3 GND0 GND1 4 XDP_FN16
+3.3V_ALW_PCH USB_OC0#_R PXDP@ RH51 1 2 33_0402_5%~D XDP_FN0 5 OBSFN_A0 OBSFN_C0 6 XDP_FN17
<20> USB_OC0#_R OBSFN_A1 OBSFN_C1
0.1U_0402_25V6K~D
USB_OC1#_R PXDP@ RH7 1 2 33_0402_5%~D XDP_FN1 7 8
<20> USB_OC1#_R GND2 GND3
PXDP@ CH1
USB_OC2# PXDP@ RH16 1 2 33_0402_5%~D XDP_FN2 XDP_FN0 9 10 XDP_FN8
<20> USB_OC2# OBSDATA_A0 OBSDATA_C0
1
USB_OC3# PXDP@ RH5 1 2 33_0402_5%~D XDP_FN3 XDP_FN1 11 12 XDP_FN9

RH66 <20,47> USB_OC3# USB_OC4#_R PXDP@ RH6 1 2 33_0402_5%~D XDP_FN4 13 OBSDATA_A1 OBSDATA_C1 14
<20> USB_OC4#_R 1 GND4 GND5
1K_0402_1%~D USB_OC5# PXDP@ RH14 1 2 33_0402_5%~D XDP_FN5 XDP_FN2 15 16 XDP_FN10
<20> USB_OC5# USB_OC6# PXDP@ RH8 1 2 33_0402_5%~D XDP_FN6 XDP_FN3 17 OBSDATA_A2 OBSDATA_C2 18 XDP_FN11
PCH_AZ_SYNC is sampled <20> USB_OC6# OBSDATA_A3 OBSDATA_C3
SIO_EXT_SMI# PXDP@ RH9 1 2 33_0402_5%~D XDP_FN7 19 20
at the rising edge of RSMRST# pin.
2
<20,49> SIO_EXT_SMI# SLP_ME_CSW_DEV# PXDP@ RH10 1 2 33_0402_5%~D XDP_FN8 2 21 GND6 GND7 22

So signal should be PU to the ALWAYS rail. <21,48> SLP_ME_CSW_DEV# PCH_GPIO35 PXDP@ RH12 1 2 33_0402_5%~D XDP_FN9 23 OBSFN_B0 OBSFN_D0 24
PCH_AZ_SYNC <21> PCH_GPIO35 HDD_DET#_R PXDP@ RH13 1 2 33_0402_5%~D XDP_FN10 25 OBSFN_B1 OBSFN_D1 26
BBS_BIT0_R PXDP@ RH26 1 2 33_0402_5%~D XDP_FN11 XDP_FN4 27 GND8 GND9 28 XDP_FN12
OBSDATA_B0 OBSDATA_D0
1
PCH_GPIO36 PXDP@ RH20 1 2 33_0402_5%~D XDP_FN12 XDP_FN5 29 30 XDP_FN13

RH282 @ <21> PCH_GPIO36 PCH_GPIO37 PXDP@ RH34 1 2 33_0402_5%~D XDP_FN13 31 OBSDATA_B1 OBSDATA_D1 32
D 100K_0402_5%~D <21> PCH_GPIO37 PCH_GPIO16 PXDP@ RH17 1 2 33_0402_5%~D XDP_FN14 XDP_FN6 33 GND10 GND11 34 XDP_FN14 D
<21> PCH_GPIO16 TEMP_ALERT# PXDP@ RH18 1 2 33_0402_5%~D XDP_FN15 XDP_FN7 35 OBSDATA_B2 OBSDATA_D2 36 XDP_FN15
<21,48> TEMP_ALERT# PCH_GPIO15 PXDP@ RH19 1 2 33_0402_5%~D XDP_FN16 PXDP@ RH283 1K_0402_1%~D 37 OBSDATA_B3 OBSDATA_D3 38
2
<21> PCH_GPIO15 SIO_EXT_SCI#_R PXDP@ RH53 1 2 33_0402_5%~D XDP_FN17 1 2 1.05V_0.8V_PWROK_R 39 GND12 GND13 40 +3.3V_ALW_PCH
<21> SIO_EXT_SCI#_R <49,60> 1.05V_0.8V_PWROK PWRGOOD/HOOK0 ITPCLK/HOOK4
PCH_RSMRST#_Q PXDP@ RH24 1 2 1K_0402_1%~D RSMRST#_XDP 1 2 PCH_PWRBTN#_XDP 41 42
<19,50> PCH_RSMRST#_Q <7,19> SIO_PWRBTN#_R HOOK1 ITPCLK#/HOOK5
RH21 0_0402_5%~D 43 44
PXDP@ 45 VCC_OBS_AB VCC_OBS_CD 46 RSMRST#_XDP
47 HOOK2 RESET#/HOOK6 48 XDP_DBRESET#
On Die PLL VR is supplied by HOOK3 DBR#/HOOK7 XDP_DBRESET# <7,19>
RH284 PXDP@ 0_0402_5%~D 49 50
1.5V when sampled high, 1.8 V 1 2 DDR_XDP_WAN_SMBDAT_R2 51 GND14 GND15 52 PCH_JTAG_TDO
<12,13,14,15,18,35,43> DDR_XDP_WAN_SMBDAT SDA TD0
when sampled low 1 2 DDR_XDP_WAN_SMBCLK_R2 53 54
<12,13,14,15,18,35,43> DDR_XDP_WAN_SMBCLK SCL TRST#
RH285 0_0402_5%~D 55 56 PCH_JTAG_TDI
PXDP@ PCH_JTAG_TCK 57 TCK1 TDI 58 PCH_JTAG_TMS
59 TCK0 TMS 60
GND16 GND17
SAMTE_BSH-030-01-L-D-A CONN@
+RTC_CELL
Crystal EA. Link CIS OK +3.3V_RUN
0722
1
RH38 CH2 PCH_GPIO33 1 2

330K_0402_1%~D 18P_0402_50V8J~D 100K_0402_5%~D RH355
2 1 PCH_RTCX1 IRQ_SERIRQ 1 2
8.2K_0402_5%~D RH28
2
PCH_INTVRMEN BBS_BIT0_R 1 2
1
4.7K_0402_5%~D RH52
1
YH1 RH15 HDD1_DET# 1 2

@ RH39 32.768KHZ_12.5PF_Q13FC1350000~D 10M_0402_5%~D UH4A 10K_0402_5%~D RH30
330K_0402_1%~D
2
CH3 A20 C38 LPC_LAD0 +3.3V_RUN
LPC_LAD0 <41,42,48,49>
2
18P_0402_50V8J~D RTCX1 FWH0 / LAD0 A38 LPC_LAD1
LPC_LAD1 <41,42,48,49>
2
2 1 PCH_RTCX2_R 1 2 PCH_RTCX2 C20 FWH1 / LAD1 B37 LPC_LAD2
LPC
RTCX2 FWH2 / LAD2 LPC_LAD2 <41,42,48,49>
@ RH286 0_0402_5%~D C37 LPC_LAD3 SPKR 1 2
FWH3 / LAD3 LPC_LAD3 <41,42,48,49>
+RTC_CELL RH22 1 2 20K_0402_5%~D PCH_RTCRST# D20 10K_0402_5%~D RH35 @
RTCRST# D36 LPC_LFRAME#
INTVRMEN- Integrated SUS FWH4 / LFRAME# LPC_LFRAME# <41,42,48,49>
RH23 1 2 20K_0402_5%~D SRTCRST# G22 No Reboot Strap
1.1V VRM Enable SRTCRST# E36
RH11 1 2 1M_0402_5%~D INTRUDER# K22 LDRQ0# K36 LPC_LDRQ1#
High - Enable Internal VRs Low = Default
RTC
INTRUDER# LDRQ1# / GPIO23 LPC_LDRQ1# <48>
SPKR
Low - Enable External VRs PCH_INTVRMEN C17 V5 IRQ_SERIRQ High = No Reboot
INTVRMEN SERIRQ IRQ_SERIRQ <41,48,49>
C C
1 2 1 2 AM3
1 2 1 2 SATA0RXN PSATA_PRX_DTX_N0_C <35>
PCH_AZ_BITCLK N34 AM1
HDA_BCLK SATA0RXP PSATA_PRX_DTX_P0_C <35>
AP7 HDD1
SATA 6G
PCH_AZ_SYNC L34 SATA0TXN AP5 PSATA_PTX_DRX_N0_C <35>
@ @ HDA_SYNC SATA0TXP PSATA_PTX_DRX_P0_C <35>
ME1 SHORT PADS~D CMOS1 SHORT PADS~D T10 AM10
<47> SPKR SPKR SATA1RXN
1 2 1 2 AM8
CH5 1U_0402_6.3V6K~D CH4 1U_0402_6.3V6K~D PCH_AZ_RST# K34 SATA1RXP AP11
HDA_RST# SATA1TXN AP10
CMOS place near DIMM SATA1TXP
PCH_AZ_CODEC_SDIN0 E34 AD7
<47> PCH_AZ_CODEC_SDIN0 HDA_SDIN0 SATA2RXN SATA_NVRAM_PRX_DTX_N2_C <43>
AD5
SATA2RXP SATA_NVRAM_PRX_DTX_P2_C <43>
CMOS_CLR1 CMOS setting G34 AH5 NVRAM
HDA_SDIN1 SATA2TXN AH4 SATA_NVRAM_PTX_DRX_N2_C <43>
+3.3V_ALW_PCH C34 SATA2TXP SATA_NVRAM_PTX_DRX_P2_C <43>
Shunt Clear CMOS HDA_SDIN2 AB8
SATA_ODD_PRX_DTX_N3_C <36>
IHDA
1 2 A34 SATA3RXN AB10
Open Keep CMOS @ RH287 1K_0402_1%~D HDA_SDIN3 SATA3RXP AF3
SATA_ODD_PRX_DTX_P3_C <36>
SATA3TXN SATA_ODD_PTX_DRX_N3_C <36> ODD
AF1
1 2 PCH_AZ_SDOUT A36 SATA3TXP SATA_ODD_PTX_DRX_P3_C <36>
ME_CLR1 TPM setting <48> ME_FWP
RH50 1K_0402_1%~D HDA_SDO Y7
ESATA_PRX_DTX_N4_C <39>
SATA
+3.3V_ALW_PCH SATA4RXN Y5
Shunt Clear ME RTC Registers PCH_GPIO33 C36 SATA4RXP AD3
ESATA_PRX_DTX_P4_C <39>
HDA_DOCK_EN# / GPIO33 SATA4TXN ESATA_PTX_DRX_N4_C <39> E-SATA
Open Keep ME RTC Registers AD1
SATA4TXP ESATA_PTX_DRX_P4_C <39>
1
JTAG@ N32
RH288 HDA_DOCK_RST# / GPIO13 Y3
SATA5RXN SATA_PRX_DKTX_N5_C <46>
0_0603_5%~D Y1
SATA5RXP SATA_PRX_DKTX_P5_C <46>
AB3 DOCK
JTAG@ RH59 2 1 51_0402_1%~D PCH_JTAG_TCK J3 SATA5TXN AB1 SATA_PTX_DKRX_N5_C <46>
2
JTAG_TCK SATA5TXP SATA_PTX_DKRX_P5_C <46>

+3.3V_ALW_PCH_JTAG JTAG@ RH44 2 1 200_0402_1%~D PCH_JTAG_TMS H7 Y11 +1.05V_RUN
JTAG_TMS SATAICOMPO
JTAG
JTAG@ RH45 2 1 200_0402_1%~D PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
JTAG_TDI SATAICOMPI RH40 37.4_0402_1%~D
JTAG@ RH43 2 1 200_0402_1%~D PCH_JTAG_TDO H1
JTAG_TDO AB12 +1.05V_RUN
1 2 PCH_AZ_SDOUT SATA3RCOMPO
<47> PCH_AZ_CODEC_SDOUT Pop them until ST.
JTAG@ 100_0402_1%~D
JTAG@ 100_0402_1%~D
JTAG@ 100_0402_1%~D
RH29 33_0402_5%~D AB13 SATA3_COMP 1 2

1 2 PCH_AZ_SYNC_Q SATA3COMPI RH42 49.9_0402_1%~D
<47> PCH_AZ_CODEC_SYNC
RH27 33_0402_5%~D
1 2 PCH_AZ_RST# PCH_SPI_CLK T3 AH1 RBIAS_SATA3 1 2
B <47> PCH_AZ_CODEC_RST# SPI_CLK SATA3RBIAS B
RH41 33_0402_5%~D RH46 750_0402_1%~D
1
1 2 PCH_AZ_BITCLK PCH_SPI_CS0# Y14

<47> PCH_AZ_CODEC_BITCLK SPI_CS0#
RH48
RH49
RH47
RH25 33_0402_5%~D
PCH_SPI_CS1# T1
SPI_CS1#
27P_0402_50V8J~D
1 P3 SATA_ACT#
SPI
SATALED# SATA_ACT# <51>
@ CH101
PCH_SPI_DO V4 V14 HDD_DET#_R 1 2

SPI_MOSI SATA0GP / GPIO21 HDD1_DET# <35>
@ RH290 0_0402_5%~D
2 PCH_SPI_DIN U3 P1 BBS_BIT0_R
SPI_MISO SATA1GP / GPIO19
Follow conn list 1223A.
BD82PPSM-QNHN-A0_BGA989~D
CONN@
JSPI1
2 1 SPI_PCH_CS1# 1
+5V_RUN 0_0402_5%~D RH345 PCH_SPI_CS1# 2 1
2 1 SPI_PCH_DO 3 2
0_0402_5%~D RH346 PCH_SPI_DO 4 3
2 1 SPI_PCH_DIN 5 4
QH7 BIOS ROM Select Component 0_0402_5%~D RH347 PCH_SPI_DIN 6 5
6
2
G
SSM3K7002FU_SC70-3~D 2 1 SPI_PCH_CLK 7
0_0402_5%~D RH348 PCH_SPI_CLK 8 7
1 2 PCH_AZ_SYNC_Q 3 1 PCH_AZ_SYNC X76(Main) X76(2nd) 2 1 SPI_PCH_CS0# 9 8
RH31 1M_0402_5%~D 0_0402_5%~D RH349 PCH_SPI_CS0# 10 9
S
X7640631L01 X7640631L03 +3.3V_SPI 11 10

12 11
+3.3V_M 12
+3.3V_SPI 13
WINBOND EON C788 2 1 14 13
1 2 0_0402_5%~D RH350 15 14
INTEL HDA_SYNC isolation circuit 16 15
U52
SA000039A2L SA000046400 200 MIL SO8 0.1U_0402_25V6K~D 16
17
(W25Q64FVSSIG) (EN25Q64-104HIP) 32Mb Flash ROM 18 GND
GND
SA00003K80L SA00004LI00 U53 X76@ TYCO_1-2041070-6~D
U53 SPI_PCH_CS1# 1 2 SPI_PCH_CS1#_R 1 8
(W25Q32BVSSIG) (EN25Q32B-104HIP) R936 47_0402_5%~D 2 CS# VCC 7 SPI_HOLD#
SPI_PCH_DIN 1
R895
SPI_WP#_SEL_R
2 SPI_DIN32
33_0402_5%~D
3
4
DO
WP#
GND
HOLD#
CLK
DI
6
5
SPI_CLK32 1
R897
SPI_DO32 1
2 SPI_PCH_CLK
33_0402_5%~D
2 SPI_PCH_DO
Link CIS OK
A
+3.3V_SPI
C787
W25Q32BVSSIG_SO8~D
Create X76 BOM for 2nd source.
R900 33_0402_5%~D
0109 A
1 2
@ R2065 @ C1265
1
0.1U_0402_25V6K~D 33_0402_5%~D 10P_0402_50V8J~D

200 MIL SO8
1
R890 SPI_CLK32 2 1 1 2
3.3K_0402_5%~D R891
64Mb Flash ROM 3.3K_0402_5%~D
U52 X76@ @ R2066 @ C1266
2
1
SPI_PCH_CS0# 2 SPI_PCH_CS0#_R 1 8 33_0402_5%~D 10P_0402_50V8J~D
2
R963 47_0402_5%~D /CS VCC SPI_CLK64 2 1 1 2

SPI_PCH_DIN 1
R894
2 SPI_DIN64
33_0402_5%~D
2
DO /HOLD
7 SPI_HOLD# DELL CONFIDENTIAL/PROPRIETARY
1 2 SPI_WP#_SEL_R 3 6 SPI_CLK64 1 2 SPI_PCH_CLK
<48> SPI_WP#_SEL
@ R898 0_0402_5%~D /WP CLK R899 33_0402_5%~D
4 5 SPI_DO64 1 2 SPI_PCH_DO PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
GND DIO TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
R901 33_0402_5%~D
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PCH (1/8)
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W25Q64FVSSIG_SO8~D NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
Create X76 BOM for 2nd source. LA-7931P
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
WWW.AliSaler.Com +3.3V_ALW_PCH
2
SML1_SMBCLK 2 1
2.2K_0402_5%~D RH298
MEM_SMBCLK 6 1 SML1_SMBDATA 2 1
DDR_XDP_WAN_SMBCLK <12,13,14,15,17,35,43>
2.2K_0402_5%~D RH299
QH5A DDR_HVREF_RST_PCH 1 2
5
DMN66D0LDW-7_SOT363-6~D 1K_0402_1%~D RH300
PCH_GPIO74 1 2
MEM_SMBDATA 3 4 10K_0402_5%~D RH301
MEM_SMBCLK 1 2
QH5B 2.2K_0402_5%~D RH302
D DMN66D0LDW-7_SOT363-6~D MEM_SMBDATA 1 2 D
2.2K_0402_5%~D RH303
UH4B PCH_SMB_ALERT# 1 2
10K_0402_5%~D RH304
PCIE_PRX_WANTX_N1 BG34
<43> PCIE_PRX_WANTX_N1 PERN1
WWAN/ PCIE_PRX_WANTX_P1 BJ34 E12 PCH_SMB_ALERT#
<43> PCIE_PRX_WANTX_P1 PERP1 SMBALERT# / GPIO11
PCIE_PTX_WANRX_N1 AV32
NVRAM (Mini Card 2)---> <43> PCIE_PTX_WANRX_N1 PCIE_PTX_WANRX_P1 AU32 PETN1 H14 MEM_SMBCLK +3.3V_LAN
<43> PCIE_PTX_WANRX_P1 PETP1 SMBCLK
PCIE_PRX_WLANTX_N2 BE34 C9 MEM_SMBDATA
<42> PCIE_PRX_WLANTX_N2 PERN2 SMBDATA
PCIE_PRX_WLANTX_P2 BF34 LAN_SMBCLK 1 2
<42> PCIE_PRX_WLANTX_P2 PERP2
WLAN (Mini Card 1)---> PCIE_PTX_WLANRX_N2 BB32 2.2K_0402_5%~D RH305
<42> PCIE_PTX_WLANRX_N2 PCIE_PTX_WLANRX_P2 AY32 PETN2 LAN_SMBDATA 1 2
<42> PCIE_PTX_WLANRX_P2 PETP2 A12 DDR_HVREF_RST_PCH 2.2K_0402_5%~D RH306
SMBUS
PCIE_PRX_EXPTX_N3 BG36 SML0ALERT# / GPIO60 DDR_HVREF_RST_PCH <7>
<47> PCIE_PRX_EXPTX_N3 PERN3
PCIE_PRX_EXPTX_P3 BJ36 C8 LAN_SMBCLK
<47> PCIE_PRX_EXPTX_P3 PERP3 SML0CLK LAN_SMBCLK <37>
EXPRESS Card---> PCIE_PTX_EXPRX_N3 AV34
<47> PCIE_PTX_EXPRX_N3 PCIE_PTX_EXPRX_P3 AU34 PETN3 G12 LAN_SMBDATA
<47> PCIE_PTX_EXPRX_P3 PETP3 SML0DATA LAN_SMBDATA <37>
BF36
BE36 PERN4
AY34 PERP4 C13 PCH_GPIO74
BB34 PETN4 SML1ALERT# / PCHHOT# / GPIO74
PETP4 E14 SML1_SMBCLK
SML1CLK / GPIO58 SML1_SMBCLK <49>
PCIE_PRX_WPANTX_N5 BG37
PCI-E*
<42> PCIE_PRX_WPANTX_N5 PERN5
PCIE_PRX_WPANTX_P5 BH37 M16 SML1_SMBDATA
<42> PCIE_PRX_WPANTX_P5 PERP5 SML1DATA / GPIO75 SML1_SMBDATA <49>
PP (Mini Card 3)---> PCIE_PTX_WPANRX_N5 AY36
<42> PCIE_PTX_WPANRX_N5 PCIE_PTX_WPANRX_P5 BB36 PETN5
<42> PCIE_PTX_WPANRX_P5 PETP5
BJ38
BG38 PERN6
AU36 PERP6 M7 PCH_CL_CLK1
Controller
C PETN6 CL_CLK1 PCH_CL_CLK1 <42> C
AV36
PETP6
PCIE_PRX_GLANTX_N7 BG40 T11 PCH_CL_DATA1
Link
<37> PCIE_PRX_GLANTX_N7 PERN7 CL_DATA1 PCH_CL_DATA1 <42>
PCIE_PRX_GLANTX_P7 BJ40
<37> PCIE_PRX_GLANTX_P7 PERP7
10/100/1G LAN ---> PCIE_PTX_GLANRX_N7 AY40
<37> PCIE_PTX_GLANRX_N7 PCIE_PTX_GLANRX_P7 BB40 PETN7 P10 PCH_CL_RST1#
<37> PCIE_PTX_GLANRX_P7 PETP7 CL_RST1# PCH_CL_RST1# <42>
PCIE_PRX_MMITX_N8 BE38
<47> PCIE_PRX_MMITX_N8 PERN8
PCIE_PRX_MMITX_P8 BC38 +3.3V_ALW_PCH 2 RH80 1 GFX_CLK_REQ#
<47> PCIE_PRX_MMITX_P8 PERP8
MMI ---> PCIE_PTX_MMIRX_N8 AW38 10K_0402_5%~D
<47> PCIE_PTX_MMIRX_N8 PCIE_PTX_MMIRX_P8 AY38 PETN8
<47> PCIE_PTX_MMIRX_P8 PETP8
1
M10 GFX_CLK_REQ# D
@ RH3072 1 0_0402_5%~D PCIE_MINI1# Y40 PEG_A_CLKRQ# / GPIO47 2 QH2
<43> CLK_PCIE_MINI1# CLKOUT_PCIE0N <48,52> RUN_GFX_ON
WWAN/ @ RH3082 1 0_0402_5%~D PCIE_MINI1 Y39 G SSM3K7002FU_SC70-3~D
<43> CLK_PCIE_MINI1 RH81 2 1 10K_0402_5%~D CLKOUT_PCIE0P AB37 CLK_PCIE_VGA#
+3.3V_ALW_PCH S
3
NVRAM (Mini Card 2)---> MINI1CLK_REQ# J2 CLKOUT_PEG_A_N AB38 CLK_PCIE_VGA CLK_PCIE_VGA# <16>
<43> MINI1CLK_REQ# PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_VGA <16>
CLOCKS
@ RH82 2 1 0_0402_5%~D PCIE_LAN# AB49 AV22 CLK_CPU_DMI#
<37> CLK_PCIE_LAN# @ RH83 2 1 0_0402_5%~D PCIE_LAN AB47 CLKOUT_PCIE1N CLKOUT_DMI_N AU22 CLK_CPU_DMI CLK_CPU_DMI# <7>
<37> CLK_PCIE_LAN CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <7>
10/100/1G LAN --->
LANCLK_REQ# M1 CLK_BUF_DMI# 1 2
<37> LANCLK_REQ# PCIECLKRQ1# / GPIO18 AM12 CLK_BUF_DMI RH74 1 2 10K_0402_5%~D
CLKOUT_DP_N AM13 RH75 10K_0402_5%~D
@ RH85 2 1 0_0402_5%~D PCIE_CARD# AA48 CLKOUT_DP_P
<47> CLK_PCIE_CARD# @ RH86 2 1 0_0402_5%~D PCIE_CARD AA47 CLKOUT_PCIE2N CLK_BUF_BCLK 1 2
MMI ---> <47> CLK_PCIE_CARD CLKOUT_PCIE2P
+3.3V_RUN RH87 1 2 10K_0402_5%~D BF18 CLK_BUF_DMI# RH91 10K_0402_5%~D
CARDCLK_REQ# V10 CLKIN_DMI_N BE18 CLK_BUF_DMI
<47> CARDCLK_REQ# PCIECLKRQ2# / GPIO20 CLKIN_DMI_P
CLK_BUF_DOT96# 1 2
@ RH88 2 1 0_0402_5%~D PCIE_MINI3# Y37 BJ30 CLK_BUF_BCLK CLK_BUF_DOT96 RH76 1 2 10K_0402_5%~D
B <42> CLK_PCIE_MINI3# CLKOUT_PCIE3N CLKIN_GND1_N B
PP (Mini Card 3)---> @ RH90 2 1 0_0402_5%~D PCIE_MINI3 Y36 BG30 CLK_BUF_BCLK RH77 10K_0402_5%~D
<42> CLK_PCIE_MINI3 CLKOUT_PCIE3P CLKIN_GND1_P
+3.3V_ALW_PCH RH152 2 1 10K_0402_5%~D
MINI3CLK_REQ# A8 CLK_BUF_CKSSCD# 1 2
<42> MINI3CLK_REQ# PCIECLKRQ3# / GPIO25 G24 CLK_BUF_DOT96# CLK_BUF_CKSSCD RH78 1 2 10K_0402_5%~D
CLKIN_DOT_96N E24 CLK_BUF_DOT96 RH79 10K_0402_5%~D
@ RH92 2 1 0_0402_5%~D PCIE_EXP# Y43 CLKIN_DOT_96P
<47> CLK_PCIE_EXP# CLKOUT_PCIE4N
Express card---> @ RH93 2 1 0_0402_5%~D PCIE_EXP Y45 CLK_PCH_14M 1 2
<47> CLK_PCIE_EXP CLKOUT_PCIE4P
+3.3V_ALW_PCH RH94 2 1 10K_0402_5%~D AK7 CLK_BUF_CKSSCD# RH183 10K_0402_5%~D
EXPCLK_REQ# L12 CLKIN_SATA_N AK5 CLK_BUF_CKSSCD
<47> EXPCLK_REQ# PCIECLKRQ4# / GPIO26 CLKIN_SATA_P
@ RH95 2 1 0_0402_5%~D PCIE_MINI2# V45 K45 CLK_PCH_14M

<42> CLK_PCIE_MINI2# CLKOUT_PCIE5N REFCLK14IN
@ RH96 2 1 0_0402_5%~D PCIE_MINI2 V46 CLOCK TERMINATION for FCIM and need close to PCH
<42> CLK_PCIE_MINI2 CLKOUT_PCIE5P
WLAN (Mini Card 1)---> +3.3V_ALW_PCH RH97 2 1 10K_0402_5%~D
MINI2CLK_REQ# L14 H45 CLK_PCI_LOOPBACK
<42> MINI2CLK_REQ# PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LOOPBACK <20>
AB42 V47 XTAL25_IN 2 1

AB40 CLKOUT_PEG_B_N XTAL25_IN V49 XTAL25_OUT @ RH309 0_0402_5%~D
CLKOUT_PEG_B_P XTAL25_OUT
1
+3.3V_ALW_PCH RH98 1 2 10K_0402_5%~D PEG_B_CLKRQ# E6 RH99
PEG_B_CLKRQ# / GPIO56 1M_0402_5%~D
Y47 XCLK_RCOMP RH1001 2 90.9_0402_1%~D +1.05V_RUN YH2
V40 XCLK_RCOMP 25MHZ_10PF_Q22FA2380049900~D
2
V42 CLKOUT_PCIE6N 3 1
CLKOUT_PCIE6P OUT IN Crystal EA.
+3.3V_ALW_PCH RH3681 2 10K_0402_5%~D PCIECLKRQ6# T13 4 2
PCIECLKRQ6# / GPIO45 GND GND
10P_0402_50V8J~D
10P_0402_50V8J~D
2 2
V38 K43 PCI_TPM_TCM RH311 2 1 22_0402_5%~D
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 CLK_PCI_TPM_TCM <41>
CH18
CH19
V37
FLEX CLOCKS
CLKOUT_PCIE7P F47 SIO_14M RH313 2 1 22_0402_5%~D

CLKOUTFLEX1 / GPIO65 CLK_SIO_14M <48> 1 1
+3.3V_ALW_PCH RH3691 2 10K_0402_5%~D PCIECLKRQ7# K12
A PCIECLKRQ7# / GPIO46 H47 CLK_80H RH314 2 1 22_0402_5%~D A
CLKOUTFLEX2 / GPIO66 PCLK_80H <42>
@ RH280 1 2 0_0402_5%~D CLK_BCLK_ITP# AK14
PCIE REQ power rail: <7> CLK_CPU_ITP#
@ RH281 1 2 0_0402_5%~D CLK_BCLK_ITP AK13 CLKOUT_ITPXDP_N K49 JETWAY_14M @ RH315 2 1 22_0402_5%~D
<7> CLK_CPU_ITP CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 JETWAY_CLK14M <41>
Suspend: 0 3 4 5 6 7
Core: 1 2 BD82PPSM-QNHN-A0_BGA989~D DELL CONFIDENTIAL/PROPRIETARY
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LA-7931P
5 4 3 2 1
5 4 3 2 1
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+3.3V_ALW_PCH
+RTC_CELL MAX14885EETL has internal 3K pu for
1 2 SUS_STAT#/LPCPD#
PCH_CRT_DDC_CLK and PCH_CRT_DDC_DAT
330K_0402_1%~D
@ RH318 10K_0402_5%~D
2
1 2 ME_SUS_PWR_ACK DSWODVREN - On Die DSW VR Enable
RH127
RH144 10K_0402_5%~D
1 2 PCH_PCIE_WAKE# Enabled (DEFAULT)
RH142 10K_0402_5%~D PCH_DPWROK 1 2 PCH_RSMRST#_R +3.3V_RUN
1 2 SIO_SLP_LAN# @ RH113 0_0402_5%~D HIGH: RH127 STUFFED,
1
@ RH319 10K_0402_5%~D RH129 UNSTUFFED
D 1 2 PCH_RI# RESET_OUT# 1 2 SYS_PWROK PCH_CRT_DDC_CLK 2 1 D
RH140 10K_0402_5%~D @ RH321 0_0402_5%~D DSWODVREN 2.2K_0402_5%~D RH317 @
Disabled
330K_0402_1%~D
ME_SUS_PWR_ACK_R 1 2 SUSACK#_R PCH_CRT_DDC_DAT 1 2
2
@ RH129
@ RH323 0_0402_5%~D LOW: RH129 STUFFED, 2.2K_0402_5%~D RH316 @
+3.3V_RUN RH127 UNSTUFFED
1 2 CLKRUN#
RH137 8.2K_0402_5%~D
1
UH4C
Intel request DDPB can not support eDP
DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 UH4D

<6> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <6>
DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1 PANEL_BKEN_PCH J47 AP43
<6> DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <6> <28> PANEL_BKEN_PCH L_BKLTEN SDVO_TVCLKINN
DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 ENVDD_PCH M45 AP45
<6> DMI_CTX_PRX_N2 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 <6> <28,48> ENVDD_PCH L_VDD_EN SDVO_TVCLKINP
DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3
<6> DMI_CTX_PRX_N3 DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 <6>
BC12 FDI_CTX_PRX_N4 BIA_PWM_PCH P45 AM42
FDI_RXN4 FDI_CTX_PRX_N4 <6> <28> BIA_PWM_PCH L_BKLTCTL SDVO_STALLN
DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5 AM40
<6> DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <6> SDVO_STALLP
DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6 LDDC_CLK_PCH T40
<6> DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 <6> <27> LDDC_CLK_PCH L_DDC_CLK
DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7 LDDC_DATA_PCH K47 AP39
<6> DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 <6> <27> LDDC_DATA_PCH L_DDC_DATA SDVO_INTN
DMI_CTX_PRX_P3 BJ20 AP40
C <6> DMI_CTX_PRX_P3 DMI3RXP SDVO_INTP C
BG14 FDI_CTX_PRX_P0 T45
FDI_RXP0 FDI_CTX_PRX_P0 <6> L_CTRL_CLK
DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1 P39
<6> DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 <6> L_CTRL_DATA
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2
<6> DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 <6>
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 1 2 LVD_IBG AF37 P38
<6> DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P3 <6> LVD_IBG SDVO_CTRLCLK
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 RH344 2.37K_0402_1%~D AF36 M39
<6> DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 <6> LVD_VBG SDVO_CTRLDATA
BG12 FDI_CTX_PRX_P5 Minimum speacing of 20mils for LVD_IBG
DMI
FDI
FDI_RXP5 FDI_CTX_PRX_P5 <6>
DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6 AE48
<6> DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 <6> LVD_VREFH
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 AE47 AT49
<6> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <6> LVD_VREFL DDPB_AUXN
DMI_CRX_PTX_P2 AY18 AT47
<6> DMI_CRX_PTX_P2 DMI2TXP DDPB_AUXP
DMI_CRX_PTX_P3 AU18 AT40
<6> DMI_CRX_PTX_P3 DMI3TXP DDPB_HPD
AW16 FDI_INT LCD_ACLK-_PCH AK39
+1.05V_RUN FDI_INT FDI_INT <6> <27> LCD_ACLK-_PCH LVDSA_CLK#
LCD_ACLK+_PCH AK40 AV42
LVDS
<27> LCD_ACLK+_PCH LVDSA_CLK DDPB_0N
BJ24 AV12 FDI_FSYNC0 AV40
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <6> DDPB_0P
LCD_A0-_PCH AN48 AV45
<27> LCD_A0-_PCH LVDSA_DATA#0 DDPB_1N
1 2 DMI_COMP_R BG25 BC10 FDI_FSYNC1 LCD_A1-_PCH AM47 AV46
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <6> <27> LCD_A1-_PCH LVDSA_DATA#1 DDPB_1P
RH111 49.9_0402_1%~D LCD_A2-_PCH AK47 AU48
Digital Display Interface

<27> LCD_A2-_PCH LVDSA_DATA#2 DDPB_2N
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0 AJ48 AU47
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <6> LVDSA_DATA#3 DDPB_2P
RH112 750_0402_1%~D AV47
BB10 FDI_LSYNC1 LCD_A0+_PCH AN47 DDPB_3N AV49
FDI_LSYNC1 FDI_LSYNC1 <6> <27> LCD_A0+_PCH LVDSA_DATA0 DDPB_3P
LCD_A1+_PCH AM49
<27> LCD_A1+_PCH LVDSA_DATA1
LCD_A2+_PCH AK49
<27> LCD_A2+_PCH LVDSA_DATA2
AJ47 P46
A18 DSWODVREN LVDSA_DATA3 DDPC_CTRLCLK P42
DSWVRMEN DDPC_CTRLDATA
LCD_BCLK-_PCH AF40
<27> LCD_BCLK-_PCH
System Power Management
1 2 SUSACK#_R C12 E22 PCH_DPWROK LCD_BCLK+_PCH AF39 LVDSB_CLK# AP47

<48> SUSACK# SUSACK# DPWROK PCH_DPWROK <48> <27> LCD_BCLK+_PCH LVDSB_CLK DDPC_AUXN
@ RH114 0_0402_5%~D AP49
LCD_B0-_PCH AH45 DDPC_AUXP AT38
<27> LCD_B0-_PCH LVDSB_DATA#0 DDPC_HPD
1 2 SYS_RESET# K3 B9 PCH_PCIE_WAKE# LCD_B1-_PCH AH47
<7,17> XDP_DBRESET# SYS_RESET# WAKE# PCH_PCIE_WAKE# <49> <27> LCD_B1-_PCH LVDSB_DATA#1
@ RH359 0_0402_5%~D LCD_B2-_PCH AF49 AY47
<27> LCD_B2-_PCH LVDSB_DATA#2 DDPC_0N
AF45 AY49
1 2 SYS_PWROK_R P12 N3 CLKRUN# LVDSB_DATA#3 DDPC_0P AY43
B <7,48> SYS_PWROK SYS_PWROK CLKRUN# / GPIO32 CLKRUN# <41,48,49> DDPC_1N B
@ RH116 0_0402_5%~D LCD_B0+_PCH AH43 AY45
<27> LCD_B0+_PCH LVDSB_DATA0 DDPC_1P
LCD_B1+_PCH AH49 BA47
<27> LCD_B1+_PCH LVDSB_DATA1 DDPC_2N
1 2 PCH_PWROK L22 G8 SUS_STAT#/LPCPD# T56 PAD~D@ LCD_B2+_PCH AF47 BA48
<49> RESET_OUT# PWROK SUS_STAT# / GPIO61 <27> LCD_B2+_PCH LVDSB_DATA2 DDPC_2P
@ RH117 0_0402_5%~D AF43 BB47
LVDSB_DATA3 DDPC_3N BB49
PM_APWROK_R L10 N14 SUSCLK T57 PAD~D@ DDPC_3P
APWROK SUSCLK / GPIO62
T58 PAD~D@ PCH_CRT_BLU N48 M43
<32> PCH_CRT_BLU CRT_BLUE DDPD_CTRLCLK
1 2 PM_DRAM_PWRGD_R B13 D10 SIO_SLP_S5# PCH_CRT_GRN P49 M36
<7> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 SIO_SLP_S5# <49> <32> PCH_CRT_GRN CRT_GREEN DDPD_CTRLDATA
@ RH320 0_0402_5%~D PCH_CRT_RED T49
<32> PCH_CRT_RED CRT_RED
T59 PAD~D@
1 2 PCH_RSMRST#_R C21 H4 SIO_SLP_S4# AT45
<17,50> PCH_RSMRST#_Q RSMRST# SLP_S4# SIO_SLP_S4# <48,52,55> DDPD_AUXN
@ RH120 0_0402_5%~D PCH_CRT_DDC_CLK T39 AT43
CRT
<32> PCH_CRT_DDC_CLK CRT_DDC_CLK DDPD_AUXP
PCH_CRT_DDC_DAT M40 BH41
<32> PCH_CRT_DDC_DAT CRT_DDC_DATA DDPD_HPD
1 2 ME_SUS_PWR_ACK_R K16 F4 SIO_SLP_S3#
<49> ME_SUS_PWR_ACK SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# SIO_SLP_S3# <11,35,47,48,52,56>
@ RH121 0_0402_5%~D BB43
RH123 1 2 20_0402_1%~D HSYNC M47 DDPD_0N BB45
<7,17> SIO_PWRBTN#_R <32> PCH_CRT_HSYNC CRT_HSYNC DDPD_0P
1 2 SIO_PWRBTN#_R E20 G10 SIO_SLP_A# RH124 1 2 20_0402_1%~D VSYNC M49 BF44
<49> SIO_PWRBTN# PWRBTN# SLP_A# SIO_SLP_A# <48,52,57> <32> PCH_CRT_VSYNC CRT_VSYNC DDPD_1N
@ RH122 0_0402_5%~D BE44
T62 PAD~D@ DDPD_1P BF42
AC_PRESENT H20 G16 SIO_SLP_SUS# CRT_IREF T43 DDPD_2N BE42
<49> AC_PRESENT ACPRESENT / GPIO31 SLP_SUS# SIO_SLP_SUS# <48> DAC_IREF DDPD_2P
T42 BJ42
CRT_IRTN DDPD_3N
1K_0402_0.5%~D
T63 PAD~D@ 1 2 PCH_CRT_BLU BG42
DDPD_3P
1
+3.3V_ALW_PCH 1 2 PCH_BATLOW# E10 AP14 H_PM_SYNC RH131 150_0402_1%~D
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <7>
RH126
RH139 8.2K_0402_5%~D BD82PPSM-QNHN-A0_BGA989~D
1 2 PCH_CRT_GRN
PCH_RI# A10 K14 SIO_SLP_LAN# RH132 150_0402_1%~D
RI# SLP_LAN# / GPIO29 SIO_SLP_LAN# <37,48>
2
1 2 PCH_CRT_RED
BD82PPSM-QNHN-A0_BGA989~D RH133 150_0402_1%~D
+3.3V_ALW2
CH112 1 2 ENVDD_PCH
A 1 2 RH134 100K_0402_5%~D A
5
UC4 0.1U_0402_25V6K~D
1
P
<48,52,57> SIO_SLP_A# IN1 4 PM_APWROK_R

<49> PM_APWROK
2
IN2
O DELL CONFIDENTIAL/PROPRIETARY
G
3
prevent material shortage for Thai flood. TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
1 2 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PCH (3/8)
@ RH367 0_0402_5%~D NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

5 4 3 2 1
5 4 3 2 1
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AY7
RSVD1 AV7
+3.3V_RUN BG26 RSVD2 AU3
BJ26 TP1 RSVD3 BG4
BH25 TP2 RSVD4
1 2 PCI_PIRQA# BJ16 TP3 AT10
RH324 8.2K_0402_5%~D BG16 TP4 RSVD5 BC8
AH38 TP5 RSVD6
1 2 PCI_PIRQB# AH37 TP6 AU2
RH325 8.2K_0402_5%~D AK43 TP7 RSVD7 AT4
AK45 TP8 RSVD8 AT3
D 1 2 PCI_PIRQC# C18 TP9 RSVD9 AT1 D
RH326 8.2K_0402_5%~D N30 TP10 RSVD10 AY3
H3 TP11 RSVD11 AT5
1 2 PCI_PIRQD# AH12 TP12 RSVD12 AV3
RH329 8.2K_0402_5%~D AM4 TP13 RSVD13 AV1
AM5 TP14 RSVD14 BB1
1 2 PCI_REQ1# Y13 TP15 RSVD15 BA3
RH327 10K_0402_5%~D K24 TP16 RSVD16 BB5
L24 TP17 RSVD17 BB3
1 2 LCD_CBL_DET# AB46 TP18 RSVD18 BB7
RH330 10K_0402_5%~D AB45 TP19 RSVD19 BE8
TP20 RSVD20 BD4
RSVD
1 2 PCH_GPIO54 RSVD21 BF6
RH328 10K_0402_5%~D RSVD22
B21 AV5
1 2 PCH_GPIO3 M20 TP21 RSVD23 AV10
RH332 10K_0402_5%~D AY16 TP22 RSVD24
BG46 TP23 AT8
1 2 CAM_MIC_CBL_DET# TP24 RSVD25
RH331 10K_0402_5%~D AY5
RSVD26 BA2
1 2 PCH_GPIO52 BE28 RSVD27
<40> USB3RN1 USB3Rn1
RH360 10K_0402_5%~D BC30 AT12
<40> USB3RN2 USB3Rn2 RSVD28
BE32 BF3
BJ32 USB3Rn3 RSVD29
<46> USB3RN4 USB3Rn4
BC28
<40> USB3RP1 USB3Rp1
BE30
<40> USB3RP2 USB3Rp2
BF32
USB30
BG32 USB3Rp3 C24 USBP0-
<46> USB3RP4 USB3Rp4 USBP0N USBP0- <40>
<40> USB3TN1
AV26
USB3Tn1 USBP0P
A24 USBP0+
USBP0+ <40> ----->Right Side
BB26 C25 USBP1-
<40> USB3TN2 USB3Tn2 USBP1N USBP1- <40>
C
AU28
USB3Tn3 USBP1P
B25 USBP1+
USBP1+ <40> ----->Right Side C
AY30 C26 USBP2-
<46> USB3TN4 USB3Tn4 USBP2N USBP2- <47>
<40> USB3TP1
AU26
USB3TP1 USBP2P
A26 USBP2+
USBP2+ <47> ----->Left Side
AY26 K28 USBP3-
<40> USB3TP2 USB3Tp2 USBP3N USBP3- <46>
PCI_GNT3# AV28
USB3Tp3 USBP3P
H28 USBP3+
USBP3+ <46> ----->MLK DOCK
AW30 E28 USBP4-
<46> USB3TP4 USB3Tp4 USBP4N USBP4- <46>
----->DOCK
1K_0402_1%~D
D28 USBP4+
USBP4P USBP4+ <46>
1
@ RH333
C28 USBP5-
USBP5N USBP5- <43>
USBP5P
A28 USBP5+
USBP5+ <43> ----->WWAN/UWB
C29 USBP6-
USBP6N USBP6- <47>
USBP6P
B29 USBP6+ USBP6+ <47> ----->Left Side
PCI_PIRQA# K40 N28 USBP7-
USBP7- <41>
2
PIRQA# USBP7N
PCI_PIRQB# K38
PIRQB# USBP7P
M28 USBP7+
USBP7+ <41> ----->USH
PCI_PIRQC# H38 L30 USBP8-
PCI
PIRQC# USBP8N USBP8- <42>
PCI_PIRQD# G38
PIRQD# USBP8P
K30 USBP8+
USBP8+ <42> ----->WLAN/WIMAX +3.3V_ALW_PCH
G30 USBP9-
USBP9N USBP9- <39>
PCI_REQ1# C46
REQ1# / GPIO50 USBP9P
E30 USBP9+
USBP9+ <39> ----->ESATA RPH1
A16 swap override Strap/Top-Block PCH_GPIO52 C44 C30 USBP10- USB_OC0#_R 4 5
USB
REQ2# / GPIO52 USBP10N USBP10- <47>
PCH_GPIO54 E40
REQ3# / GPIO54 USBP10P
A30 USBP10+
USBP10+ <47> ----->Express Card USB_OC1#_R 3 6
Swap Override jumper L32 USBP11- USB_OC3# 2 7
USBP11N USBP11- <50>
BBS_BIT1 D47
GNT1# / GPIO51 USBP11P
K32 USBP11+ USBP11+ <50> ----->Blue Tooth USB_OC4#_R 1 8
E42 G32 USBP12-
GNT2# / GPIO53 USBP12N USBP12- <28>
Low = A16 swap PCI_GNT3# F46
GNT3# / GPIO55 USBP12P
E32 USBP12+
USBP12+ <28> ----->Camera 10K_1206_8P4R_5%~D
PCI_GNT#3 C32 RPH2
USBP13N A32 USB_OC5# 4 5
High = Default USBP13P
LCD_CBL_DET# G42 USB_OC6# 3 6
<28> LCD_CBL_DET# PIRQE# / GPIO2
PCH_GPIO3 G40 SIO_EXT_SMI# 2 7
CAM_MIC_CBL_DET# C42 PIRQF# / GPIO3 C33 USBRBIAS 1 2 USB_OC2# 1 8
<28> CAM_MIC_CBL_DET# PIRQG# / GPIO4 USBRBIAS#
1 2 FFS_PCH_INT D44 RH151
<35> HDD_FALL_INT PIRQH# / GPIO5
@ RH334 0_0402_5%~D 22.6_0402_1%~D 10K_1206_8P4R_5%~D
@ RH343 1 2 0_0402_5%~D B33 Route single-end 50-ohms and max 500-mils length.
<16> PLTRST_GPU# USBRBIAS
@ RH335 1 2 0_0402_5%~D PAD~D T104 @ K10
<41> PLTRST_USH#
@ RH336 1 2 0_0402_5%~D PME# Minimum spacing to other signals: 15 mils
B <47> PLTRST_MMI# B
@ RH337 1 2 0_0402_5%~D PCH_PLTRST# C6 A14 USB_OC0#_R @ RH339 1 2 0_0402_5%~D
<7> PLTRST_XDP# PLTRST# OC0# / GPIO59 USB_OC0# <40>
@ RH338 1 2 0_0402_5%~D K20 USB_OC1#_R @ RH341 1 2 0_0402_5%~D
<37> PLTRST_LAN# OC1# / GPIO40 USB_OC1# <47>
B17 USB_OC2#
OC2# / GPIO41 USB_OC2# <17>
RH160 2 1 22_0402_5%~D PCI_5048 H49 C16 USB_OC3#
<48> CLK_PCI_5048 CLKOUT_PCI0 OC3# / GPIO42 USB_OC3# <17,47>
RH102 2 1 22_0402_5%~D PCI_MEC H43 L16 USB_OC4#_R @ RH356 1 2 0_0402_5%~D
<49> CLK_PCI_MEC CLKOUT_PCI1 OC4# / GPIO43 USB_OC4# <39>
RH103 2 1 22_0402_5%~D PCI_DOCK J48 A16 USB_OC5#
<46> CLK_PCI_DOCK CLKOUT_PCI2 OC5# / GPIO9 USB_OC5# <17>
K42 D14 USB_OC6#
CLKOUT_PCI3 OC6# / GPIO10 USB_OC6# <17>
RH105 2 1 22_0402_5%~D PCI_LOOPBACKOUT H40 C14 SIO_EXT_SMI#
<18> CLK_PCI_LOOPBACK CLKOUT_PCI4 OC7# / GPIO14 SIO_EXT_SMI# <17,49>
USB_OC0#_R <17>
USB_OC1#_R <17>
USB_OC4#_R <17>
12P_0402_50V8J 1 2 @ C1324 CLK_PCI_5048

12P_0402_50V8J 1 2 @ C1325 CLK_PCI_MEC
12P_0402_50V8J 1 2 @ C1326 CLK_PCI_DOCK
12P_0402_50V8J 1 2 @ C1327 CLK_PCI_LOOPBACK Boot BIOS Strap
SATA_SLPD
BBS_BIT1 (BBS_BIT0) Boot BIOS Location
BBS_BIT1
For RF layout request
0 0 LPC
1
+3.3V_RUN @ RH342
CH102 0 1 Reserved (NAND) 1K_0402_1%~D
1 2
2
0.1U_0402_25V6K~D 1 0 PCI
A A
5
UH3 1 1 SPI
1
*
P
<7> PCH_PLTRST# IN1 4

2
IN2
O PCH_PLTRST#_EC <41,42,43,47,48,49>
G
3
prevent material shortage for Thai flood. TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
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LA-7931P
5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com +3.3V_ALW_PCH
CONTACTLESS_DET# 1 2
+3.3V_RUN
10K_0402_5%~D RH256
2
SIO_A20GATE 1 2
RH54 10K_0402_5%~D RH158
4.7K_0402_5%~D SIO_RCIN# 1 2
UH4F 10K_0402_5%~D RH203
<17> SIO_EXT_SCI#_R
SIO_EXT_SCI# 2 1
1
SLP_ME_CSW_DEV# SIO_EXT_SCI# 1 2 T7 C40 CONTACTLESS_DET# 10K_0402_5%~D RH263
<49> SIO_EXT_SCI# CONTACTLESS_DET# <41>
@ RH259 0_0402_5%~D BMBUSY# / GPIO0 TACH4 / GPIO68 USH_DET# 2 1
1
USH_DET# A42 B41 DGPU_PWROK 100K_0402_5%~D RH164
<41> USH_DET# TACH1 / GPIO1 TACH5 / GPIO69 DGPU_PWROK <16,48>
RH353 @ PCH_GPIO36 1 2
D DP_MUX_PRIORITY H36 C41 MXM_PRESENTR# 10K_0402_5%~D RH171 @ D
1K_0402_1%~D TACH2 / GPIO6 TACH6 / GPIO70 MXM_PRESENTR# <16>
PCH_GPIO37 1 2
MXM_PRESENTL# E38 A40 PCH_GPIO71 PAD~D T109 @ 1K_0402_1%~D RH173 @
<16> MXM_PRESENTL#
2
TACH3 / GPIO7 TACH7 / GPIO71 TEMP_ALERT# 1 2

SIO_EXT_WAKE# C10 10K_0402_5%~D RH266
<48> SIO_EXT_WAKE# GPIO8 PCH_GPIO22 1 2
PM_LANPHY_ENABLE C4 10K_0402_5%~D RH181
<37> PM_LANPHY_ENABLE LAN_PHY_PWR_CTRL / GPIO12 MXM_PRESENTL# 1 2
PCH_GPIO15 G2 P4 SIO_A20GATE 10K_0402_5%~D RH178
<17> PCH_GPIO15 GPIO15 A20GATE SIO_A20GATE <49>
Note: PCH has internal pull up 20k ohm on PCH_GPIO17 2 1
AU16 8.2K_0402_5%~D RH269
E3_PAID_TS_DET# (GPIO27) PCH_GPIO16 U2 PECI DP_MUX_PRIORITY 2 1
<17> PCH_GPIO16 SATA4GP / GPIO16 P5 SIO_RCIN# 10K_0402_5%~D RH163
RCIN# SIO_RCIN# <49>
PCH_GPIO16 2 1
PCH_GPIO17 D40 AY11 H_CPUPWRGD +1.05V_RUN_VTT 8.2K_0402_5%~D RH272
GPIO
TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD <7>
SLP_ME_CSW_DEV# PLL ON DIE VR ENABLE PCH_GPIO35 2 1
CPU/MISC
PCH_GPIO22 T5 AY10 PCH_THRMTRIP#_R 2 1 8.2K_0402_5%~D @ RH361
SCLOCK / GPIO22 THRMTRIP# RH262 56_0402_5%~D MXM_PRESENTR# 1 2
ENABLED - HIGH DEFAULT @ T107PAD~D PCH_GPIO24 E8 T14 INIT3_3V# PAD~D T106 @ 100K_0402_5%~D RH362
GPIO24 INIT3_3V#
0.1U_0402_25V6K~D
DISABLED - LOW 1
PCH_GPIO27 E16 AY1 DF_TVS power Saving.
GPIO27 DF_TVS
CH97
SLP_ME_CSW_DEV# P8
<17,48> SLP_ME_CSW_DEV# GPIO28 2
AH8
DGPU_HOLD_RST# K1 TS_VSS1
<16> DGPU_HOLD_RST# STP_PCI# / GPIO34 AK11
PCH_GPIO35 K4 TS_VSS2
<17> PCH_GPIO35 GPIO35 AH10
+3.3V_ALW_PCH PCH_GPIO36 V8 TS_VSS3
<17> PCH_GPIO36 SATA2GP / GPIO36 AK10
PCH_GPIO37 M5 TS_VSS4
<17> PCH_GPIO37 SATA3GP / GPIO37
2 1 SIO_EXT_WAKE#
C RH177 10K_0402_5%~D TPM_ID0 N2 P37 NC_1 PAD~D T108 @ C
1 2 PCH_GPIO15 SLOAD / GPIO38 NC_1
RH354 1K_0402_1%~D TPM_ID1 M3
2 1 KB_DET# SDATAOUT0 / GPIO39
RH170 10K_0402_5%~D FFS_INT2 V13 BG2 VSS_NCTF_15
<35> FFS_INT2 SDATAOUT1 / GPIO48 VSS_NCTF_15
2 1 PCH_GPIO27
@ RH175 10K_0402_5%~D TEMP_ALERT# V3 BG48 VSS_NCTF_16
<17,48> TEMP_ALERT# SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
PCH has internal pull up 20k ohm on (GPIO27) KB_DET# D6 BH3 VSS_NCTF_17
2 1 PCH_GPIO36
<50> KB_DET# GPIO57 VSS_NCTF_17 Layout note:
RH174 10K_0402_5%~D BH47 VSS_NCTF_18 Trace wide 10mil & length 30mil
2 1 PCH_GPIO37 VSS_NCTF_18
RH172 10K_0402_5%~D VSS_NCTF_1 A4 BJ4 VSS_NCTF_19
All NCTF pins should have thick
2 1 PCH_GPIO17 VSS_NCTF_1 VSS_NCTF_19 traces at 45°from the pad.
@ RH273 1K_0402_1%~D VSS_NCTF_2 A44 BJ44 VSS_NCTF_20
2 1 PCH_GPIO16 VSS_NCTF_2 VSS_NCTF_20
@ RH274 1K_0402_1%~D VSS_NCTF_3 A45 BJ45 VSS_NCTF_21
VSS_NCTF_3 VSS_NCTF_21
VSS_NCTF_4 A46 BJ46 VSS_NCTF_22
NCTF
VSS_NCTF_7 B3 C2 VSS_NCTF_25
VSS_NCTF_8 B47 C48 VSS_NCTF_26
Layout note: VSS_NCTF_9 BD1 D1 VSS_NCTF_27

Trace wide 10mil & length 30mil VSS_NCTF_10 BD49 D49 VSS_NCTF_28
B All NCTF pins should have thick VSS_NCTF_11 BE1 E1 VSS_NCTF_29 B
traces at 45°from the pad. VSS_NCTF_11 VSS_NCTF_29
VSS_NCTF_12 BE49 E49 VSS_NCTF_30
PLACE RH150 CLOSE TO THE BRANCHING POINT
VSS_NCTF_13 BF1 F1 VSS_NCTF_31 ( TO CPU and NVRAM CONNECTOR)
VSS_NCTF_14 BF49 F49 VSS_NCTF_32
VSS_NCTF_14 VSS_NCTF_32 +VCCDFTERM
2.2K_0402_5%~D
1
RH149 need to close to CPU
RH149
2
+3.3V_RUN +3.3V_RUN @ RH150 1 2 0_0402_5%~D DF_TVS_R 1 2 DF_TVS
<7> H_SNB_IVB#
RH358 1K_0402_1%~D
2
RH267 1@ RH268 3@
10K_0402_5%~D 20K_0402_5%~D TPM_ID0 TPM_ID1
TCM 0 0 DMI & FDI Termination Voltage
1
TPM_ID0 TPM_ID1 No TPM, No TCM 0 1

Set to Vss when LOW
2
TBD DF_TVS
RH270 2@ RH271 4@ Set to Vcc when HIGH
10K_0402_5%~D 2.2K_0402_5%~D TPM 1 1
A A
1
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LA-7931P
5 4 3 2 1
5 4 3 2 1
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need change to SHI00003Y0L, after footprint ok.
+3.3V_RUN
LH1
+VCCADAC 1 2
4.7UH_LQM18FN4R7M00D_20%~D
0.01U_0402_16V7K~D
0.1U_0402_10V7K~D
1 1 1
POWER
CH34
CH35
+1.05V_RUN UH4G CH36
22U_0805_6.3V6M~D
2 2 2
AA23 U48
PCH Power Rail Table
D AC23 VCCCORE[1] VCCADAC D
VCCCORE[2]
S0 Iccmax
AD21 Voltage Rail Voltage Current (A)
VCCCORE[3]
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CRT
1 1 1 1 AD23 U47
AF21 VCCCORE[4] VSSADAC
VCCCORE[5]
CH30
CH32
CH33
CH31
VCC CORE
AF23 +3.3V_RUN V_PROC_IO 1.05 0.001
AG21 VCCCORE[6]
2 2 2 2 AG23 VCCCORE[7]
AG24 VCCCORE[8] AK36
VCCCORE[9] VCCALVDS
V5REF 5 0.001
AG26
AG27 VCCCORE[10] AK37 +1.8V_RUN
AG29 VCCCORE[11] VSSALVDS
VCCCORE[12]
V5REF_Sus 5 0.001
AJ23 LH8
AJ26 VCCCORE[13] AM37 +1.8V_RUN_LVDS 2 1
LVDS
VCCCORE[14] VCCTX_LVDS[1]
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
22U_0805_6.3V6M~D
AJ27 100NH_HCI1608F-R10J-M_5%_0603~D Vcc3_3 3.3 0.228
VCCCORE[15]
CH103
AJ29 AM38
AJ31 VCCCORE[16] VCCTX_LVDS[2]
VCCCORE[17] 1 1 1 TAIYO EOL, change to TAI‐TECH,
CH105
+1.05V_RUN AP36 VccADAC3 3.3 0.063
VCCTX_LVDS[3] footprint is TAIYO_HK1608R10J‐T_L0603_2P.
CH104
AP37
AN19 VCCTX_LVDS[4] 2 2 2
VCCIO[28]
VccADPLLA 1.05 0.08
+1.05V_RUN
@ RH247
1 2 +VCCAPLLEXP BJ22 VccADPLLB 1.05 0.08
1UH_LB2012T1R0M_20%~D VCCAPLLEXP
10U_0603_6.3V6M~D
1 V33 +3.3V_RUN
VCC3_3[6]
0.1U_0402_10V7K~D
@ AN16 VccCore 1.05 1.7
HVCMOS
VCCIO[15]
1
CH40
AN17
2 VCCIO[16]
CH43
V34 VccDMI 1.1 0.047
VCC3_3[7]
AN21 2
+1.05V_RUN VCCIO[17]
VccIO 1.05 3.711
C AN26 +VCCAFDI_VRM C
VCCIO[18]
AN27 AT16 VccASW 1.05 0.903
VCCIO[19] VCCVRM[3]
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D AP21
1 1 1 1 1 VCCIO[20]
VccSPI 3.3 0.01
CH44
CH45
CH46
CH47
CH48
AP23 AT20 +1.05V_RUN_VTT
VCCIO[21] VCCDMI[1]
2 2 2 2 2 AP24 1 2 CH49 VccDSW3_3 3.3 0.001
DMI
VCCIO[22] 1U_0402_6.3V6K~D
VCCIO
AP26 AB36 +1.05V_RUN_VCCCLKDMI @ RH205 2 1 0_0603_5%~D +1.05V_RUN
VCCIO[23] VCCCLKDMI
1U_0402_6.3V6K~D
10U_0603_6.3V6M~D
1 1 VCCDFTERM 1.8 0.002
@ CH106
AT24
VCCIO[24]
CH50
VccRTC 3.3 2 (mA)
AN33 2 2
VCCIO[25]
AN34 AG16 VccSus3_3 3.3 0.095
+3.3V_RUN VCCIO[26] VCCDFTERM[1] +VCCDFTERM
BH29 AG17 2 1 +3.3V_RUN VccSusHDA 3.3 0.01

VCC3_3[3] VCCDFTERM[2]
0.1U_0402_10V7K~D
@ RH276 0_0805_5%~D
DFT / SPI
0.1U_0402_10V7K~D
1 @ PJP70
+VCCAFDI_VRM AJ16 1 1 2 +1.8V_RUN VccVRM 1.5 0.167
VCCDFTERM[3]
CH51
CH52
AP16 PAD-OPEN1x1m
2 VCCVRM[2] AJ17
VCCDFTERM[4]
VccClkDMI 1.05 0.07
2
+VCCAPLL_FDI BG6
VccAFDIPLL
VccSSC 1.05 0.095
+1.05V_RUN AP17
B VCCIO[27] V1 +VCCSPI @ RH202 2 1 0_0603_5%~D B
VCCSPI +3.3V_M VccDIFFCLKN 1.05 0.055
1U_0402_6.3V6K~D
FDI
+1.05V_RUN_VTT AU20
VCCDMI[2]
1 VccALVDS 3.3 0.001
CH54
+1.05V_RUN VccTX_LVDS 1.8 0.04
2
1 2 +VCCAPLL_FDI
@ RH195 0.022_0805_1%
+1.5V_RUN +VCCAFDI_VRM
@ RH211 2 1 0_0603_5%~D
A A
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LA-7931P
5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com +5V_ALW +5V_ALW_PCH

+PWR_SRC_S QH4
+1.05V_RUN
100K_0402_5%~D
+1.05V_RUN 1 3
S
1
0.1U_0402_10V7K~D
1 2 +VCCACLK
+3.3V_ALW_PCH
RH363
20K_0402_5%~D
@ RH200 0.022_0805_1%
POWER
1
1U_0402_6.3V6K~D
UH4J 1
G
2
+3.3V_ALW2
CH98
1 2 0_0402_5%~D 1
0.1U_0402_10V7K~D
RH278
@ RH201 AD49 N26
2
VCCACLK VCCIO[29]
CH56
1 2 1 +5V_ALW_PCH_ENABLE
D @ RH253 0_0402_5%~D P26 2 D
2
VCCIO[30] 2
CH55
1M_0402_5%~D
3300P_0402_50V7K~D
+VCCDSW3_3 T16
VCCDSW3_3
1
D
0.1U_0402_10V7K~D
@ RH364
P28 1
2 VCCIO[31]
QH8
CH110
2
<52> ALW_ON_3.3V#
+PCH_VCCDSW V12 T27 G
+1.05V_RUN DCPSUSBYP VCCIO[32]
@ CH57
1 S
3
@ LH3 T29 +3.3V_ALW_PCH 2
2
1 2 +3.3V_RUN_VCC_CLKF33 T38 VCCIO[33]
VCC3_3[5] +3.3V_ALW_PCH
10U_0603_6.3V6M~D
10UH_LBR2012T100M_20%~D
2
0.1U_0402_10V7K~D
T23
+1.05V_RUN +VCCAPLL_CPY_PCH BH23 VCCSUS3_3[7]
VCCAPLLDMI2 1
CH59
1 T24
VCCSUS3_3[8]
@ CH58
0.1U_0402_10V7K~D
AL29
VCCIO[14] V23
VCCSUS3_3[9] 2 1
1U_0402_6.3V6K~D
USB
2
CH60
+VCCSUS1 AL24 V24
DCPSUS[3] VCCSUS3_3[10]
@ CH61
1 2
P24
VCCSUS3_3[6]
AA19
2 VCCASW[1] T26 +5V_ALW_PCH +3.3V_ALW_PCH
VCCIO[34] +1.05V_RUN
AA21
VCCASW[2]
2
AA24 M26 +PCH_V5REF_SUS
VCCASW[3] V5REF_SUS RH208 DH2
+1.05V_M AA26 10_0402_1%~D RB751S40T1_SOD523-2~D
+3.3V_RUN VCCASW[4]
Clock and Miscellaneous

AN23 +VCCA_USBSUS +3.3V_ALW_PCH
AA27 DCPSUS[4]
1
VCCASW[5]
0.1U_0402_10V7K~D
AN24 +PCH_V5REF_SUS
VCCSUS3_3[1]
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
0.1U_0402_10V7K~D
1 2 +3.3V_RUN_VCC_CLKF33 AA29 1
RH215 0.022_0805_1% VCCASW[6]
1 1 1 1 1 1
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
CH64
CH65
1 1 AA31
VCCASW[7] +3.3V_ALW_PCH
CH67
CH68
CH69
CH66
CH63
Note: If EMI concern, pop with 2
CH74
@ AC26 P34 +PCH_V5REF_RUN

SHI00008S0L, 10UH +‐20% 2 2 2 2 2 VCCASW[8] V5REF 2
C 2 2 C
CH73
1U_0603_10V7K~D
AC27
VCCASW[9] N20
VCCSUS3_3[2]
CH70
AC29 1
PCI/GPIO/LPC
VCCASW[10] N22
AC31 VCCSUS3_3[3] +5V_RUN +3.3V_RUN
VCCASW[11] P20 +3.3V_RUN
VCCSUS3_3[4] 2
0.1U_0402_10V7K~D
AD29
VCCASW[12]
2
P22
VCCSUS3_3[5]
CH72
AD31 1 RH213 DH3
VCCASW[13] 10_0402_1%~D RB751S40T1_SOD523-2~D
+1.05V_RUN W21 AA16
VCCASW[14] VCC3_3[1]
1
LH6 W23 W16 2 +3.3V_RUN +PCH_V5REF_RUN
1U_0603_10V7K~D
1 2 +1.05V_RUN_VCCA_A_DPL
10UH_LBR2012T100M_20%~D W24 T34 1
0.1U_0402_10V7K~D
LH7 1
+3.3V_RUN
CH71
1 2 +1.05V_RUN_VCCA_B_DPL W26
VCCASW[17]
220U_B2_2.5VM_R35M~D
220U_B2_2.5VM_R35M~D
CH75
10UH_LBR2012T100M_20%~D
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_10V7K~D
1 1 W29
VCCASW[18] 2
1 1
CH94
CH92
CH95
CH93
+ + W31 AJ2
VCCASW[19] VCC3_3[2] 1
+1.05V_RUN CRB 0.7 RH208,RH213 trace width 20mil.
CH76
W33
2 2 2 2 VCCASW[20] AF13
VCCIO[5] 2
0.1U_0402_10V7K~D
+VCCA_USBSUS
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
+VCCRTCEXT N16
DCPRTC AH13
1 VCCIO[12] 1 1
CH78
@ CH62
+VCCAFDI_VRM
CH77
Y49 AH14
VCCVRM[4] VCCIO[13]
2 2 2
+1.05V_RUN AF14
+1.05V_RUN_VCCA_A_DPL BD47 VCCIO[6]
VCCADPLLA AK1
1
SATA
CH79 +1.05V_RUN_VCCA_B_DPL BF47 VCCAPLLSATA +VCCAFDI_VRM
B B
1U_0402_6.3V6K~D VCCADPLLB
AF11 +1.05V_RUN
2 AF17 VCCVRM[1]
18 mil AF33 VCCIO[7]
CH81 AF34 VCCDIFFCLKN[1] AC16
VCCDIFFCLKN[2] VCCIO[2]
1U_0402_6.3V6K~D
1 2 AG34
AF33, AF34 and AG34 rout trace width = 18 mil, VCCDIFFCLKN[3] AC17
VCCIO[3] 1
1U_0402_6.3V6K~D AG33 rout trace width = 10 mil and isolated each other.
CH82
AG33 AD17
VCCSSC VCCIO[4]
1U_0402_6.3V6K~D
10 mil 2
+1.05V_M
0.1U_0402_10V7K~D
1
+VCCSST V16 +1.05V_M
DCPSST
CH96
1U_0402_6.3V6K~D
1 2 +1.05V_M_VCCSUS
@ RH248 0.022_0805_1% 1 +1.05V_M_VCCSUS
2
CH84
1 T17 T21
DCPSUS[1] VCCASW[22]
@ CH83
V19
DCPSUS[2]
MISC
+1.05V_RUN_VTT 2 V21
2 VCCASW[23]
BJ8
CPU
V_PROC_IO T19
VCCASW[21]
+RTC_CELL +3.3V_ALW_PCH
4.7U_0603_6.3V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1 1 1
CH85
CH86
CH87
A22 P32
VCCRTC VCCSUSHDA
0.1U_0402_10V7K~D
RTC
HDA
2 2 2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1U_0402_6.3V6K~D
1
1 1 1
CH91
CH88
CH89
CH90
2
2 2 2
A A
5 4
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2
Size
Date:
Document Number

LA-7931P
1
Sheet 23 of 70
Rev
1.0
5 4 3 2 1
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UH4I
AY4 H46
AY42 VSS[159] VSS[259] K18
AY46 VSS[160] VSS[260] K26
AY8 VSS[161] VSS[261] K39
B11 VSS[162] VSS[262] K46
UH4H B15 VSS[163] VSS[263] K7
D H5 B19 VSS[164] VSS[264] L18 D
VSS[0] B23 VSS[165] VSS[265] L2
AA17 AK38 B27 VSS[166] VSS[266] L20
AA2 VSS[1] VSS[80] AK4 B31 VSS[167] VSS[267] L26
AB11 VSS[5] VSS[84] AL16 F45 VSS[171] VSS[271] M12
AB14 VSS[6] VSS[85] AL17 BB12 VSS[172] VSS[272] P16
AB39 VSS[7] VSS[86] AL19 BB16 VSS[173] VSS[273] M18
AC19 VSS[12] VSS[91] AL27 BB30 VSS[178] VSS[278] M34
AC33 VSS[16] VSS[95] AL48 BC14 VSS[182] VSS[282] M46
AC34 VSS[17] VSS[96] AM11 BC18 VSS[183] VSS[283] M8
AC48 VSS[18] VSS[97] AM14 BC2 VSS[184] VSS[284] N18
AD10 VSS[19] VSS[98] AM36 BC22 VSS[185] VSS[285] P30
AD11 VSS[20] VSS[99] AM39 BC26 VSS[186] VSS[286] N47
AD19 VSS[23] VSS[102] AM46 BC36 VSS[189] VSS[289] T33
AD26 VSS[25] VSS[104] AN2 BC42 VSS[191] VSS[291] P43
AD27 VSS[26] VSS[105] AN29 BC48 VSS[192] VSS[292] P47
AD33 VSS[27] VSS[106] AN3 BD46 VSS[193] VSS[293] P7
AD34 VSS[28] VSS[107] AN31 BD5 VSS[194] VSS[294] R2
AD36 VSS[29] VSS[108] AP12 BE22 VSS[195] VSS[295] R48
C AD37 VSS[30] VSS[109] AP19 BE26 VSS[196] VSS[296] T12 C
AD38 VSS[31] VSS[110] AP28 BE40 VSS[197] VSS[297] T31
AD39 VSS[32] VSS[111] AP30 BF10 VSS[198] VSS[298] T37
AD40 VSS[34] VSS[113] AP38 BF16 VSS[200] VSS[300] W34
AD46 VSS[38] VSS[117] AP8 BF26 VSS[204] VSS[304] V11
AD8 VSS[39] VSS[118] AR2 BF28 VSS[205] VSS[305] V17
AE2 VSS[40] VSS[119] AR48 BD3 VSS[206] VSS[306] V26
AE3 VSS[41] VSS[120] AT11 BF30 VSS[207] VSS[307] V27
AF10 VSS[42] VSS[121] AT13 BF38 VSS[208] VSS[308] V29
AF12 VSS[43] VSS[122] AT18 BF40 VSS[209] VSS[309] V31
AD14 VSS[44] VSS[123] AT22 BF8 VSS[210] VSS[310] V36
AD16 VSS[45] VSS[124] AT26 BG17 VSS[211] VSS[311] V39
AF16 VSS[46] VSS[125] AT28 BG21 VSS[212] VSS[312] V43
AF19 VSS[47] VSS[126] AT30 BG33 VSS[213] VSS[313] V7
AF24 VSS[48] VSS[127] AT32 BG44 VSS[214] VSS[314] W17
AF26 VSS[49] VSS[128] AT34 BG8 VSS[215] VSS[315] W19
AF27 VSS[50] VSS[129] AT39 BH11 VSS[216] VSS[316] W2
AF38 VSS[53] VSS[132] AT7 BH19 VSS[219] VSS[319] Y12
AF4 VSS[54] VSS[133] AU24 H10 VSS[220] VSS[320] Y38
AF42 VSS[55] VSS[134] AU30 BH27 VSS[221] VSS[321] Y4
AF46 VSS[56] VSS[135] AV16 BH31 VSS[222] VSS[322] Y42
AF8 VSS[59] VSS[138] AV30 BH39 VSS[225] VSS[325] BG29
AG19 VSS[60] VSS[139] AV38 BH43 VSS[226] VSS[328] N24
AG2 VSS[61] VSS[140] AV4 BH7 VSS[227] VSS[329] AJ3
B AG31 VSS[62] VSS[141] AV43 D3 VSS[228] VSS[330] AD47 B
AG48 VSS[63] VSS[142] AV8 D12 VSS[229] VSS[331] B43
AH11 VSS[64] VSS[143] AW14 D16 VSS[230] VSS[333] BE10
AH3 VSS[65] VSS[144] AW18 D18 VSS[231] VSS[334] BG41
AH36 VSS[66] VSS[145] AW2 D22 VSS[232] VSS[335] G14
AH39 VSS[67] VSS[146] AW22 D24 VSS[233] VSS[337] H16
AH40 VSS[68] VSS[147] AW26 D26 VSS[234] VSS[338] T36
AH7 VSS[71] VSS[150] AW34 D34 VSS[237] VSS[343] C22
AJ19 VSS[72] VSS[151] AW36 D38 VSS[238] VSS[344] AP13
AJ21 VSS[73] VSS[152] AW40 D42 VSS[239] VSS[345] M14
AJ24 VSS[74] VSS[153] AW48 D8 VSS[240] VSS[346] AP3
AJ33 VSS[75] VSS[154] AV11 E18 VSS[241] VSS[347] AP1
AJ34 VSS[76] VSS[155] AY12 E26 VSS[242] VSS[348] BE16
AK12 VSS[77] VSS[156] AY22 G18 VSS[243] VSS[349] BC16
AK3 VSS[78] VSS[157] AY28 G20 VSS[244] VSS[350] BG28
VSS[79] VSS[158] G26 VSS[245] VSS[351] BJ28
BD82PPSM-QNHN-A0_BGA989~D G28 VSS[246] VSS[352]
G36 VSS[247]
G48 VSS[248]
H12 VSS[249]
H18 VSS[250]
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
H32 VSS[255]
H34 VSS[256]
F3 VSS[257]
VSS[258]
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PCH (8/8)
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7931P
5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com +3.3V_M
1
8.2K_0402_5%~D
CPU FAN
R396
2
Place Q26 under CPU for OTP sensor. CONN@
Place C339 close to the Q26 as possible Place Q15 under Butterfly's CH A (BOT side).
100P_0402_50V8J~D
REM_DIODE1_P_4002 REM_DIODE4_P_4002 JFAN1
100P_0402_50V8J~D
FAN1_TACH_FB 1 THERMATRIP1#
1
1
+5V_RUN
@ C288
2 C 1 1 2
2
1
+1.05V_RUN_VTT
@ C339
PMST3904_SOT323-3~D
0.1U_0402_25V6K~D
2 C FAN1_PWM 3 1
3
C327
D B 2 C335 4 D
4
1
E B 2200P_0402_50V7K~D C
3
1 2 2
10U_0805_10V6K~D
0.1U_0402_25V6K~D
Q28
E 5 1 R399 2 2
3
Q26 Q15 6 GND1 2.2K_0402_5%~D B 2
1 1 GND2
C329
C364
MMBT3904WT1G_SC70-3~D REM_DIODE1_N_4002 MMBT3904WT1G_SC70-3~D REM_DIODE4_N_4002 E
3
ACES_50271-0040N-001
2 2 Link CIS OK <7> H_THERMTRIP#
Put Q17 on the Bot side for Skin temperature Place Q33 under Stack_SODIMM on TOP side.
REM_DIODE2_P_4002 REM_DIODE5_P_4002 0301
100P_0402_50V8J~D
100P_0402_50V8J~D
1 1
1
1
@ C340
@ C349
C 2 C
2 E
B
2
E
B
2
2
C347
2200P_0402_50V7K~D MXM FAN Follow conn list 0301A. +3.3V_MXM
+3.3V_M
3
3
1
8.2K_0402_5%~D
Q17 Q33
MMBT3904WT1G_SC70-3~D REM_DIODE2_N_4002 MMBT3904WT1G_SC70-3~D REM_DIODE5_N_4002 CONN@
1
@ R2071 2 1 JFAN2
2.2K_0402_5%~D
R397
0_0603_5%~D FAN2_TACH_FB 1
1
1
+5V_RUN
10K_0402_5%~D
D98 2
2
R401
FAN2_PWM 1 2 FAN2_PWM_D 3
3
R400
4
2
RB751S40T1_SOD523-2~D 4
Place Q14 near Docking CONN on BOT side Place Q16 under Butterfly's CH B (BOT side).
100P_0402_50V8J~D
10U_0805_10V6K~D
0.1U_0402_25V6K~D
REM_DIODE3_P_4002 REM_DIODE8_P_4002 5 THERMATRIP3#
2
GND1
100P_0402_50V8J~D
0.1U_0402_25V6K~D
1 1 6 1
GND2
@ C294
C330
C370
PMST3904_SOT323-3~D
1 1
1
C343
C C ACES_50271-0040N-001 C
@ C272
Q115
2 2 THERMB3 2
2 E
B
2 E
B 2 2 Link CIS OK B
E
2
Q14
0301
3
3
MMBT3904WT1G_SC70-3~D
REM_DIODE3_N_4002 REM_DIODE8_N_4002
Q16
MMBT3904WT1G_SC70-3~D
C C
<16> DGPU_THERMTRIP#
+3.3V_M
U18
2 1 BC_INT#_EMC4002 10
<49> BC_DAT_EMC4002 SMDATA/BC-LINK_DATA
R385 10K_0402_5%~D 11 39
<49> BC_CLK_EMC4002 SMCLK/BC-LINK_CLK VIN1
2 1 EMC4022_GPIO2 48
R404 10K_0402_5%~D VCP1 45 VCP2 R388 1 2 4.7K_0402_5%~D +3.3V_RUN
VCP2 MAX8731_IINP <62>
2 1 FAN2_PWM
R2058 10K_0402_5%~D 1 2 REM_DIODE1_P_4002 36 44 REM_DIODE4_P_4002 FAN2_PWM_D 2 1
C334 2200P_0402_50V7K~D REM_DIODE1_N_4002 35 DP1/VREF_T DP4/DN8 43 REM_DIODE4_N_4002 10K_0402_5%~D R403
DN1/THERM DN4/DP8 FAN2_TACH_FB 2 1
1 2 REM_DIODE2_P_4002 38 47 REM_DIODE5_P_4002 REM_DIODE8_N_4002 10K_0402_5%~D R405
C344 2200P_0402_50V7K~D REM_DIODE2_N_4002 37 DP2 DP5/DN9 46 REM_DIODE5_N_4002 REM_DIODE8_P_4002 FAN1_PWM 2 1
DN2 DN5/DP9 10K_0402_5%~D R407
1 2 REM_DIODE3_P_4002 41 1 FAN1_TACH_FB 2 1
C346 2200P_0402_50V7K~D REM_DIODE3_N_4002 40 DP3/DN7 DP6/VREF_T2 2 10K_0402_5%~D R408
DN3/DP7 DN6/VIN2
+3.3V_M @ R289 2 1 0_0603_5%~D +3VM_THRM 4

VDD 12 BC_INT#_EMC4002
ATF_INT#/BC-LINK_IRQ# BC_INT#_EMC4002 <49>
1U_0402_6.3V6K~D
0.1U_0402_25V6K~D
1 +RTC_CELL 21 26 POWER_SW#
RTC_PWR3V POWER_SW# 27
1 ACAVAIL_CLR ACAV_IN <16,49,62,63>
+3.3V_M
C348
1U_0402_6.3V6K~D
20 FAN1_PWM
THERMTRIP_SIO/PWM1/GPIO5
C341
1 25 THERM_STP# <54>
2 R389 1 2 10K_0402_5%~D VDD_PWRGD 18 SYS_SHDN#
2 VDD_PWRGD
C336
<49> PCH_PWRGD# R391 1 2 1K_0402_1%~D 3V_PWROK# 17 1 2 +RTC_CELL

3V_PWROK# @ R390 47K_0402_1%~D
B
2 THERMATRIP1# 22 2 1 B
THERMATRIP2# 23 THERMTRIP1# 10K_0402_5%~D R402
THERMATRIP3# 24 THERMTRIP2# 19 2 1
THERMTRIP3# LDO_SHDN# +3.3V_M
10K_0402_5%~D @ R395
VSET_4002 42 34
VSET LDO_POK
+3VM_THRM 2 1 +ADDR_XEN 3 33 LDO_SET R392 1 2 1K_0402_1%~D
R393 4.7K_0402_5%~D ADDR_MODE/XEN LDO_SET
6 32
5 VDDH1 VDDH2 31
VDDH1 VDDH2
+3.3V_M 9 28
VDDL1 VDDL2
8.2K_0402_5%~D
7 29
VSET_4002 8 FAN_OUT1 LDO_OUT/FAN_OUT2 30
FAN_OUT1 LDO_OUT/FAN_OUT2
1
+RTC_CELL
R398
0.1U_0402_25V6K~D
FAN1_TACH_FB 15 16 FAN2_TACH_FB C287

TACH1/GPIO3 TACH2/GPIO4
1
1.33K_0402_1%~D
EMC4022_GPIO2 14 13 FAN2_PWM 2 1
CLK_IN/GPIO2 PWM2/GPIO1
1
R406
0.1U_0402_25V6K~D
2
VSS
5
C333
U10
THERMATRIP2# 1
P
<49> DOCK_PWR_SW#
2
2 EMC4002-HZH C_QFN48_7X7~D IN1 4 POWER_SW#

49
O
0.1U_0402_25V6K~D
1 <49> POWER_SW_IN# 2
IN2
G
change VSET from 88 ℃ to 93 ℃.
C350
3
2
prevent material shortage for Thai flood.
Rest=1330 ohm, Tp=93 degree
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT FAN control
5 4
WWW.AliSaler.Com 3
2
Size
Date:
Document Number

LA-7931P
1
Sheet 25 of 70
Rev
1.0
5 4 3 2 1
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D D
Monitor Charger current +3.3V_ALW
DYN_TURB_SYS_PWR_ALRT# 2 1
10K_0402_5%~D R35
CHARGE_ALERT 2 1
10K_0402_5%~D R20 @
@ U5
LCD_SMBCLK 1 10 LCD_SMBDAT
<28,49> LCD_SMBCLK SMCLK SMDATA LCD_SMBDAT <28,49>
2 9 CHARGE_ALERT
N/C ALERT#
3 8
<62> EMC1700_SENSE_N SENSE- THERM# DYN_TURB_SYS_PWR_ALRT# <48>
RESISTOR SMBUS 4 7
<62> EMC1700_SENSE_P SENSE+ GND
(5%) ADDRESS
0 1001_100(r/w) +3.3V_ALW 5 6 @ R2143 1 2 0_0402_5%~D
VDD ADDR_SEL H_PROCHOT# <7,49,60,62>
100 1001_101(r/w) EMC1701-2-AIZL-TR_MSOP10
1
1U_0402_6.3V6K~D
0.1U_0402_16V4Z~D
20K_0402_5%~D
@ R1975
1 1
@ C17
@ C363
C
180 1001_110(r/w) C
300 1001_111(r/w) 2 2
2
430 1001_000(r/w)
560 1001_001(r/w)
750 1001_010(r/w) Remove current sensor function.
1270 1001_011(r/w)
1600 0101_000(r/w)
2000 0101_001(r/w)
2700 0101_010(r/w)
3600 0101_011(r/w)
5600
9100
0101_100(r/w)
0101_100(r/w)
Monitor PWR_SRC_MXM +3.3V_ALW
20000 0101_101(r/w)
Open 0011_000(r/w) DYN_TURB_GPU_PWR_ALRT# 2 1
10K_0402_5%~D R14
PWR_SRC_ALERT 2 1
10K_0402_5%~D R19 @
B @ U6 B
LCD_SMBCLK 1 10 LCD_SMBDAT
SMCLK SMDATA
2 9 PWR_SRC_ALERT
N/C ALERT#
3 8
<52> MXM_SENSE_N SENSE- THERM# DYN_TURB_GPU_PWR_ALRT# <16,49>
4 7
<52> MXM_SENSE_P SENSE+ GND
+3.3V_ALW 5 6
VDD ADDR_SEL
EMC1701-2-AIZL-TR_MSOP10
1
1U_0402_6.3V6K~D
0.1U_0402_16V4Z~D
2.7K_0402_5%~D
@ R1974
1 1
@ C16
@ C361
2 2
Remove current sensor function.
A A

Current Sensor

5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com
D D
+3.3V_RUN
+3.3V_RUN
5@ 0.1U_0402_16V4Z~D
5@ C1145
@
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 1
Channel B
C1146
@ C1159
1 1
Channel A
C1149
2 2 U13 5@
U11 5@ 2 2
31
31 <16> MXM_LVDS_BCLK+ 30 D0_A+
<16> MXM_LVDS_ACLK+ D0_A+ <16> MXM_LVDS_BCLK- D0_A-
30 26 35
<16> MXM_LVDS_ACLK- D0_A- <16> MXM_LVDS_B2+ D1_A+ VDD
26 35 25
<16> MXM_LVDS_A2+
<16> MXM_LVDS_A2-
25
22
D1_A+
D1_A-
VDD
From MXM <16> MXM_LVDS_B2-
<16> MXM_LVDS_B1+
22
21
D1_A-
D2_A+
From MXM <16> MXM_LVDS_A1+

<16> MXM_LVDS_A1-
<16> MXM_LVDS_A0+
21
18
D2_A+
D2_A-
D3_A+ D0+
36 SW_LVDS_ACLK+
SW_LVDS_ACLK+ <28>
<16> MXM_LVDS_B1-
<16> MXM_LVDS_B0+
<16> MXM_LVDS_B0-
18
17
D2_A-
D3_A+
D3_A-
D0+
D0-
36
1
SW_LVDS_BCLK+
SW_LVDS_BCLK- SW_LVDS_BCLK+ <28>
SW_LVDS_BCLK- <28>
17 1 SW_LVDS_ACLK- 5 2 SW_LVDS_B2+
<16> MXM_LVDS_A0- D3_A- D0- SW_LVDS_ACLK- <28> 1A_A D1+ SW_LVDS_B2+ <28>
5 2 SW_LVDS_A2+ 13 3 SW_LVDS_B2-
<16> MXM_LVDS_DDC_CLK 1A_A D1+ SW_LVDS_A2+ <28> 2A_A D1- SW_LVDS_B2- <28>
13 3 SW_LVDS_A2- 33 7 SW_LVDS_B1+
<16> MXM_LVDS_DDC_DAT 2A_A D1- SW_LVDS_A2- <28> 3A_A D2+ SW_LVDS_B1+ <28>
33 7 SW_LVDS_A1+ 8 SW_LVDS_B1-
3A_A D2+ 8 SW_LVDS_A1- SW_LVDS_A1+ <28> D2- 9 SW_LVDS_B0+ SW_LVDS_B1- <28>
D2- 9 SW_LVDS_A0+ SW_LVDS_A1- <28> D3+ 10 SW_LVDS_B0- SW_LVDS_B0+ <28>
D3+ 10 SW_LVDS_A0- SW_LVDS_A0+ <28> 29 D3- 4 SW_LVDS_B0- <28>
D3- SW_LVDS_A0- <28> <19> LCD_BCLK+_PCH D0_B+ 1A
29 4 LDDC_CLK_SW 28 12
<19> LCD_ACLK+_PCH D0_B+ 1A LDDC_CLK_SW <28> <19> LCD_BCLK-_PCH D0_B- 2A
28 12 LDDC_DATA_SW 24 34
C <19> LCD_ACLK-_PCH D0_B- 2A LDDC_DATA_SW <28> <19> LCD_B2+_PCH D1_B+ 3A C
24 34 23
<19> LCD_A2+_PCH
<19> LCD_A2-_PCH
<19> LCD_A1+_PCH
23
20
D1_B+
D1_B-
D2_B+
3A
From PCH <19> LCD_B2-_PCH
<19> LCD_B1+_PCH
<19> LCD_B1-_PCH
20
19
D1_B-
D2_B+
D2_B-
19 16
<19> LCD_A1-_PCH D2_B- <19> LCD_B0+_PCH D3_B+
16 15
From PCH <19> LCD_A0+_PCH
<19> LCD_A0-_PCH
<19> LDDC_CLK_PCH
15
6
D3_B+
D3_B-
1A_B SEL
27 DGPU_SELECT#
DGPU_SELECT# <28,32,48>
<19> LCD_B0-_PCH
6
14
D3_B-
1A_B
2A_B
SEL
27 DGPU_SELECT#
14 32
<19> LDDC_DATA_PCH 2A_B 3A_B
32
3A_B
37
37 TPAD 11
TPAD 11 GND
GND TS3DV20812RHHR_VQFN36_6X6~D
SEL Chanel Source
TS3DV20812RHHR_VQFN36_6X6~D
SEL Chanel Source
0 DO=A GPU
0 DO=A GPU
1 DO=B PCH
1 DO=B PCH
+3.3V_MXM
1 2 MXM_LVDS_DDC_CLK
@ R1122 2.2K_0402_5%~D
1 2 MXM_LVDS_DDC_DAT
@ R1121 2.2K_0402_5%~D
Solve +3.3V_MXM backdrive when disable RUN_GFX_ON.
B B
+3.3V_RUN
1 2 LDDC_CLK_PCH
5@ R1124 2.2K_0402_5%~D
1 2 LDDC_DATA_PCH
5@ R1123 2.2K_0402_5%~D
A A

Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT LVDS SW
5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com +3.3V_RUN
LCD Power
+LCDVDD
Q18
SI3456DDV-T1-GE3_TSOP6~D +3.3V_ALW
1
130_0402_1%~D
LDDC_CLK @ C1318 1 2 5P_0402_50V8C~D
LVDS_ACLK- @ C1319 1 2 5P_0402_50V8C~D 1 2 LDDC_CLK_SW +LCDVDD
D
+PWR_SRC_S
R413
0.1U_0402_25V6K~D
LVDS_ACLK+ @ C1320 1 2 5P_0402_50V8C~D R159 2.2K_0402_5%~D 6
S
LVDS_BCLK- @ C1321 1 2 5P_0402_50V8C~D 1 2 LDDC_DATA_SW 4 5
LVDS_BCLK+ @ C1322 1 2 5P_0402_50V8C~D R160 2.2K_0402_5%~D 2 1
2
For 6‐bit LCD panel
470K_0402_5%~D
C292
1
1
Place near to JLVDS1
G
+3.3V_ALW
R412
closed to JLVDS1 Solve 300mW
3
2
+LCVDVDD_CHG
For RF layout request PWR consumption
10K_0402_5%~D
CONN@
2
1
JLVDS1 issue.
R414
1 +BL_PWR_SRC
1 +3.3V_RUN
D 2
2 solve LVDS cable burn out issue. D
4.7M_0402_5%~D
0.022U_0402_25V7K~D
3
3
3
4 LVDS_GND C248 1 2
2
4
1
5 PAD~D T73 @
5 <27,32,48> DGPU_SELECT# 1
R1632
6 0.1U_0402_10V7K~D
6 LCD_CBL_DET# <20>
Q19A
Q19B
C293
7 2 5
7
5
8 +LCDVDD
8 9 D100 2
OE#
P
+3.3V_RUN
2
9 10 BIA_PWM_LVDS 1 2 4 2
10 +CAMERA_VDD Y A MXM_BIA_PWM <16>
11
11 DMIC_CLK <47>
G
12 RB751VM-40TE-17_SOD323-2~D U3 change to new manufacturing
12 DMIC0 <47>
1
10K_0402_5%~D
13 TC7SH125FU_SSOP5
3
13 technology for cost down.
R1137
14 USBP12_D-
14 15 USBP12_D+
15 16 CAM_MIC_CBL_DET#
prevent material shortage for Thai flood. 5@ D53
16 CAM_MIC_CBL_DET# <20>
17 PWM_LVDS@ R2072 2 1 BIA_PWM_LVDS 2 1
<19,48> ENVDD_PCH
2
17 18 0_0603_5%~D DISP_ON
18
1
19 LCD_TST D101 RB751VM-40TE-17_SOD323-2~D
19 LCD_TST <48>
20 LDDC_CLK R1991 1 5@ 2 0_0402_5%~D 1 2 D6
20 LDDC_CLK_SW <27> BIA_PWM_EC <49>
21 LDDC_DATA R1992 1 5@ 2 0_0402_5%~D
21 LDDC_DATA_SW <27>
22 RB751VM-40TE-17_SOD323-2~D 2
22 <48> LCD_VCC_TEST_EN
23 LVDS_A0- R1993 1 5@ 2 0_0402_5%~D 1 2 Q20
23 24 1 2 SW_LVDS_A0- <27>
LVDS_A0+ R1994 5@ 0_0402_5%~D D66 PDTC124EU_SC70-3~D
24 SW_LVDS_A0+ <27>
25 LVDS_A1- R1995 1 5@ 2 0_0402_5%~D 1 2 3
25 SW_LVDS_A1- <27> BIA_PWM_PCH <19> <16> MXM_ENVDD
26 LVDS_A1+ R1996 1 5@ 2 0_0402_5%~D
26 SW_LVDS_A1+ <27>
27 LVDS_A2- R1997 1 5@ 2 0_0402_5%~D RB751VM-40TE-17_SOD323-2~D
SW_LVDS_A2- <27>
3
27 28 LVDS_A2+ R1998 1 5@ 2 0_0402_5%~D BAT54CW_SOT323-3~D
28 29 1 2 SW_LVDS_A2+ <27>
LVDS_ACLK- R1999 5@ 0_0402_5%~D
29 SW_LVDS_ACLK- <27>
30 LVDS_ACLK+ R2000 1 5@ 2 0_0402_5%~D change to new manufacturing
30 SW_LVDS_ACLK+ <27>
31
31 32 LVDS_B0- R2001 1 5@ 2 0_0402_5%~D technology for cost down. D67
32 SW_LVDS_B0- <27>
33 LVDS_B0+ R2002 1 5@ 2 0_0402_5%~D 1 2
33 34 1 2 SW_LVDS_B0+ <27> PANEL_BKEN_PCH <19>
LVDS_B1- R2003 5@ 0_0402_5%~D
34 SW_LVDS_B1- <27>
35 LVDS_B1+ R2004 1 5@ 2 0_0402_5%~D RB751VM-40TE-17_SOD323-2~D
35 SW_LVDS_B1+ <27>
41 36 LVDS_B2- R2005 1 5@ 2 0_0402_5%~D
G1 36 SW_LVDS_B2- <27>
42 37 LVDS_B2+ R2006 1 5@ 2 0_0402_5%~D
43
44
G2
G3
37
38
38
39
LVDS_BCLK- R2007
LVDS_BCLK+ R2008
1
1
5@
5@
2
2
0_0402_5%~D
0_0402_5%~D
SW_LVDS_B2+ <27>
SW_LVDS_BCLK- <27> Panel backlight power control by EC
G4 39 SW_LVDS_BCLK+ <27>
45 40 D64
G5 40 DISP_ON 1 2 Q21
MXM_PANEL_BKEN <16>
C ACES_50398-04071-001 +PWR_SRC FDC654P-G_SSOT-6~D C
+BL_PWR_SRC +LCDVDD +3.3V_RUN
100K_0402_5%~D
RB751VM-40TE-17_SOD323-2~D
40mil
1
6
D
40mil +BL_PWR_SRC
Link CIS OK
0.1U_0603_50V7K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
R1138
4 5
S
1000P_0402_50V7K~D
2
2 1 1 1
C298
C243
G
1
1
C249
D69
0914
1
3
1 2 R422 C296
1 2 2 PANEL_BKEN_EC <48>
C297
100K_0402_5%~D 0.1U_0603_50V7K~D
RB751VM-40TE-17_SOD323-2~D 2
2
2
PWR_SRC_ON
For 10‐bit LCD panel Q22
Webcam Circuit 1 2 1 3
S
CONN@ R423 47K_0402_5%~D
JLVDS2 +3.3V_RUN
1
G
+BL_PWR_SRC
2
1 2 +CAMERA_VDD Q24
2 3 PMV65XP_SOT23-3~D
3 <49> EN_INVPWR
4 LVDS_GND solve LVDS cable burn out issue.
4 5 1 3
S
5 FDC654P: P CHANNAL
0.1U_0402_25V6K~D
10U_0805_10V6K~D
6
6 LCD_CBL_DET# <20>
0.1U_0402_25V6K~D
7
7 8 1 1
G
+LCDVDD
2
8
C299
C300
9 +3.3V_RUN 1
9
C301
10 +CAMERA_VDD
10 11
11 12 DMIC_CLK <47> 2 2
12 DMIC0 <47> 2
13
13 <48> CCD_OFF
14 USBP12_D-
14 15 USBP12_D+
15 16 CAM_MIC_CBL_DET#
16 17 PWM_LVDS
CAM_MIC_CBL_DET# <20> Wrong CPN for prefix number.
17 18 DISP_ON
18 19 LCD_TST L10
B 19 LCD_TST <48> B
20 LDDC_CLK R2011 1 6@ 2 0_0402_5%~D DLW21SN121SQ2L_4P~D
20 EDP_CLK <30>
21 LDDC_DATA R2009 1 6@ 2 0_0402_5%~D 4 3 USBP12_D-
21 22 EDP_DATA <30> <20> USBP12- 4 3
22 23 LVDS_A0- R2010 1 6@ 2 0_0402_5%~D
23 EDP_LVDS_A0- <30>
24 LVDS_A0+ R2012 1 6@ 2 0_0402_5%~D 1 2 USBP12_D+
24 EDP_LVDS_A0+ <30> <20> USBP12+ 1 2
25 LVDS_A1- R2013 1 6@ 2 0_0402_5%~D
26 LVDS_A1+ R2014 1 6@ 2 0_0402_5%~D
26 27 1 2 EDP_LVDS_A1+ <30> 1 2
LVDS_A2- R2015 6@ 0_0402_5%~D
28 LVDS_A2+ R2016 1 6@ 2 0_0402_5%~D @ R427 0_0402_5%~D
28 EDP_LVDS_A2+ <30>
2
PESD5V0U2BT_SOT23-3~D
29 LVDS_ACLK- R2017 1 6@ 2 0_0402_5%~D
29 EDP_LVDS_ACLK- <30>
30 LVDS_ACLK+ R2018 1 6@ 2 0_0402_5%~D 1 2
30 EDP_LVDS_ACLK+ <30>
31 @ R428 0_0402_5%~D
31 32 LVDS_B0- R2019 1 6@ 2 0_0402_5%~D
32 EDP_LVDS_B0- <30>
D87
33 LVDS_B0+ R2020 1 6@ 2 0_0402_5%~D
33 EDP_LVDS_B0+ <30>
34 LVDS_B1- R2021 1 6@ 2 0_0402_5%~D
34 EDP_LVDS_B1- <30>
35 LVDS_B1+ R2022 1 6@ 2 0_0402_5%~D
36 LVDS_B2- R2023 1 6@ 2 0_0402_5%~D
36 37 1 2 EDP_LVDS_B2- <30>
LVDS_B2+ R2024 6@ 0_0402_5%~D
EDP_LVDS_B2+ <30>
1
37 38 LVDS_BCLK- R2025 1 6@ 2 0_0402_5%~D D13
38 EDP_LVDS_BCLK- <30>
39 LVDS_BCLK+ R2026 1 6@ 2 0_0402_5%~D DMIC_CLK 3
39 EDP_LVDS_BCLK+ <30>
40 1
40 41 DMIC0 2
41 42 EDP_LVDS_A3- <30>
42 EDP_LVDS_A3+ <30>
43 for JLVDS1 connector change then GND shield shift
43 44 PESD5V0U2BT_SOT23-3~D
44 45 (different from original).because JLVDS1 and JLVDS2
45 46 co-lay,we need modify them.
46 47
47 48
49
49 EDP_LVDS_A4+ <30> +3.3V_RUN
50
50 51 CONN@
51 52 EDP_LVDS_B3- <30> +LCDVDD JLVDS3
53 1 2
53 54 3 1 2 4
54 EDP_LVDS_B4- <30> 3 4
55 5 6
55 56
EDP_LVDS_B4+ <30>
7 5 6 8 For EMI request.
56 9 7 8 10
11 9 10 12 LCD_SMBCLK
11 12 LCD_SMBCLK <26,49>
A 57 13 14 LCD_SMBDAT A
GND_57 13 14 LCD_SMBDAT <26,49>
58 15 16 1 1
GND_58 15 16
100P_0402_50V8J~D
100P_0402_50V8J~D
59 +BL_PWR_SRC 17 18
GND_59 17 18
@ C1341
@ C1342
60 19 20
GND_60 61 19 20
GND_61 62 21 22 2 2
GND_62 63 GND GND
GND_63 64 ACES_50238-0207N-002
GND_64 65
GND_65
GND_66
66 DELL CONFIDENTIAL/PROPRIETARY
JAE_FI-M56S1-R1500-DT
Link CIS OK_0802 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Title
LVDS & CAM & TS
Link CIS OK TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
CONN list_0511
5 4 WWW.AliSaler.Com 3
2
LA-7931P
1
Sheet 28 of 70
1.0
5 4 3 2 1
WWW.AliSaler.Com
DP v1.2 Redriver +3.3V_RUN
MXM_MB_DP_SW_AUX# R1976 1 2 100K_0402_5%

+3.3V_RUN +3.3V_RUN +3.3V_RUN +3.3V_RUN
MXM_MB_DP_SW_AUX R1978 1 2 100K_0402_5%

1
0.1U_0402_25V6K~D
@ R1977 @ R1983 @ R1988 1 1 DP_MB_P14 R1985 1 2 5.1M_0603_1%~D
C1200
D 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% D
C1201 DP_HPD R1987 1 2 1M_0402_5%
0.01U_0402_16V7K~D
2
2
PEQ_DP CFG0_RE CFG1_RE 2 2
1
1
@ R1979 @ R1984 @ R1989
12
25
32
36
1
6
4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% U627
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
2
2
MXM_MB_DP_P0 C1304 1 2 0.1U_0402_10V6K~D IN0P 38 23 OUT0P C1202 1 2 0.1U_0402_10V6K~D MXM_MB_DP_P0_C
<16> MXM_MB_DP_P0 IN0p OUT0p
MXM_MB_DP_N0 C1305 1 2 0.1U_0402_10V6K~D IN0N 39 22 OUT0N C1203 1 2 0.1U_0402_10V6K~D MXM_MB_DP_N0_C
<16> MXM_MB_DP_N0 IN0n OUT0n
<16> MXM_MB_DP_N1 IN1n OUT1n
Programmable input equalization levels; Internal pull down at ~150k ohm, 3.3V MXM_MB_DP_N2 C1302 1 2 0.1U_0402_10V6K~D IN2N 45 16 OUT2N C1207 1 2 0.1U_0402_10V6K~D MXM_MB_DP_N2_C
I/O. <16> MXM_MB_DP_N2 IN2n OUT2n
L: default, LEQ, compensate channel loss up to 12dB @ HBR2 <16> MXM_MB_DP_P3 IN3p OUT3p
H: HEQ, compensate channel loss up to 15dB @ HBR2 <16> MXM_MB_DP_N3 IN3n OUT3n
M: LLEQ, compensate channel loss up to 5dB @ HBR2
3 40 CFG1_RE
I2C_ADDR CFG1
PEQ_DP 4 46
CFG0_RE 5 SCL_CTL/PEQ NC 1
R1980 2 10K_0402_5%~D
SDA_CTL/CFG0 +3.3V_RUN
Configuration pin for automatic EQ and AUX interception; Internal pull down at ~150k ohm, 3.3V 35 C1210 1 2 2.2U_0603_10V7K~D
I/O. RST#
L: default, automatic EQ enable & AUX interception enable
H: automatic EQ disable & AUX interception enable
PD# : Internal pull up 150k ohm. 26
PD# CAD_SNK
10 DPB_MB_CA_DET R1981 1 2 1M_0402_5%~D
M: automatic EQ disable & AUX interception disable, no pre-emphasis, 600mVpp swing R1982 1 2 4.99K_0402_1% 7 11 DP_SW_HPD
REXT HPD_SINK
8
CAD_SRC
C MXM_MB_DP_HPD 9 28 MXM_MB_DP_SW_AUX C
<16> MXM_MB_DP_HPD HPD_SRC AUX_SNKP
Configuration pin for auto test and input offset cancellation, 3.3V IO, internal pull up at ~150K 27 MXM_MB_DP_SW_AUX#
H: default, auto test disable & input offset cancellation enable AUX_SNKN
L: auto test enable & input offset cancellation enable MXM_MB_DP_AUX 33
M: auto test disable & input offset cancellation disable MXM_MB_DP_AUX# 34 SCL_DDC +5V_RUN
SDA_DDC 2
CEXT 15
NC2 1
2
C1215
2.2U_0603_10V7K~D
G
MXM_MB_DP_AUX C1213 1 2 0.1U_0402_10V6K~D AUX_SRCP 30 21
<16> MXM_MB_DP_AUX AUX_SRCP NC3
MXM_MB_DP_AUX# C1214 1 2 0.1U_0402_10V6K~D AUX_SRCN 29 37
<16> MXM_MB_DP_AUX# AUX_SRCN NC4 43 DP_SW_HPD 3 1 DP_HPD
NC5 2
D
Q323
GND1
GND2
GND3
EPAD
BSS138-G_SOT23-3
Vgs <=1.5 V
PS8330BQFN48GTR2-A0_QFN48_7X7
Solve DP‐>HDMI/DP‐>S‐DVI dongle no function on NV units.
18
24
31
49
According to new EIA rule and change package to GTR2 prevent the back drive
+3.3V_RUN
MXM DP_A Dongle DDC current damaging redriver.
2.2K_0402_5%~D
+5V_RUN
R2198
Place close JDP ESD request change main source to SC300002F0L.

100K_0402_5%~D
2
1
+3.3V_ALW2 @ D88 @ D89

R2199
MXM_MB_DP_P0_C 1 10 MXM_MB_DP_P0_C MXM_MB_DP_P1_C 1 10 MXM_MB_DP_P1_C

6
100K_0402_5%~D
MXM_MB_DP_N0_C 2 9 MXM_MB_DP_N0_C MXM_MB_DP_N1_C 2 9 MXM_MB_DP_N1_C

Q340A
B B
2
1
DP_A_MXM_AUX_Q 2 MXM_MB_DP_N3_C 4 7 MXM_MB_DP_N3_C MXM_MB_DP_N2_C 4 7 MXM_MB_DP_N2_C

R2200
MXM_MB_DP_P3_C 5 6 MXM_MB_DP_P3_C MXM_MB_DP_P2_C 5 6 MXM_MB_DP_P2_C

1
JDP1 CONN@
Q339B
3 3 +3.3V_RUN_DP 20
2
5 19 DP_PWR
8 8 DP_HPD 18 RTN
MXM_MB_DP_SW_AUX# 17 HP_DET
4
IP4292CZ10-TBR_XSON10_2.5X1~D IP4292CZ10-TBR_XSON10_2.5X1~D 16 AUX_CH-

GND
6
MXM_MB_DP_AUX MXM_MB_DP_SW_AUX 15
+3.3V_RUN DP_MB_P14 14 AUX_CH+
GND
Q339A
DPB_MB_CA_DET 13
CA_DET
2.2K_0402_5%~D
DPB_MB_CA_DET 2 MXM_MB_DP_N3_C 12 21
LANE3- GND
1
11 22
LANE3_shield GND
R2201
MXM_MB_DP_P3_C 10 23
1
LANE3+ GND
0.01U_0402_16V7K~D
1 MXM_MB_DP_N2_C 9 24
8 LANE2- GND
LANE2_shield
C1343
MXM_MB_DP_P2_C 7
2
MXM_MB_DP_N1_C 6 LANE2+
2 +3.3V_RUN_DP 5 LANE1-
D90 LANE1_shield
3 F6 W=40mils MXM_MB_DP_P1_C 4
LANE1+
3
NC
+3.3V_RUN 2 1 1 2 MXM_MB_DP_N0_C 3
2 LANE0-
LANE0_shield
Q340B
0.1U_0402_25V6K~D
C1217
10U_0603_6.3V6M~D
C1218
0.1U_0402_25V6K~D
C1219
22U_0805_6.3V6M~D
C1220
1.1A_6V_SMD1812P110TF MXM_MB_DP_P0_C 1
5 BAT1000-7-F_SOT23-3~D LANE0+
1 1 1 1
2 1 FOX_3V1121C-N1YD7-7H
For debug issue that (DF543750)DP‐>HDMI/DP‐>S‐DVI dongle @ R1990 0_1206_5%
4
no function on NV units
Add TMDS DDC pull up schematic on DP port
2 2 2 2
Link CIS OK_0722
A A
MXM_MB_DP_AUX#
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL DP Redriver & DP CONN
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD LA-7931P 1.0
5 4 3 2 1
WWW.AliSaler.Com
5 4 3 2 1
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prevent current leakage.
+3.3V_AVDD
+1.2V_AVDD
6@ R2036
6@ R2037
U629B 6@
1
6@ R2035
4.7K_0402_5%~D
4.7K_0402_5%~D
1
0.1U_0402_10V6K~D
6@ C1221
240_0402_1%
1 L9 N13
M8 O0_LVTX_CH5N O0_LVTX_CH0N P13 EDP_LVDS_A0- <28>
D D
O0_LVTX_CH5P O0_LVTX_CH0P EDP_LVDS_A0+ <28>
U629C 6@ M12 N12
2
2 L11 O0_LVTX_CH6N O0_LVTX_CH1N P12 EDP_LVDS_A1- <28>
2
O0_LVTX_CH6P O0_LVTX_CH1P EDP_LVDS_A1+ <28>
C13 EDP_CLK M11
AUX_I2C_SCL/GPIO_15 EDP_CLK <28> O0_LVTX_CH2N EDP_LVDS_A2- <28>
C10 B14 EDP_DATA N11
DPRX_REXT AUX_I2C_SDA_GPIO_16 EDP_DATA <28> O0_LVTX_CH2P EDP_LVDS_A2+ <28>
L10
D10 B13 O0_LVTX_CLKN M10 EDP_LVDS_ACLK- <28>
O0 & O1 LVDS Output

<16> MXM_EDP_HPD DPRX_HPD_OUT/GPIO_26 I2C_SCL/GPIO_21 D11 O0_LVTX_CLKP EDP_LVDS_ACLK+ <28>
prevent AUX swing overshoot I2C_SDA/GPIO_22 M9
6@ R2188 1 2 10_0402_1%~D MXM_EDP_AUX-_R 6@ C1291 1 2 0.1U_0402_10V6K~D
MXM_EDP_AUX-_CB9 O0_LVTX_CH3N N9 EDP_LVDS_A3- <28>
<16> MXM_EDP_AUX- DPRX_AUXN +5V_RUN O0_LVTX_CH3P EDP_LVDS_A3+ <28>
6@ R2187 1 2 10_0402_1%~D MXM_EDP_AUX+_R 6@ C1292 1 2 0.1U_0402_10V6K~D
MXM_EDP_AUX+_CC9 G10
<16> MXM_EDP_AUX+ DPRX_AUXP I2C_MST_SCL/GPIO_2 F11 N8
I2C_MST_SDA/GPIO_3 O0_LVTX_CH4N EDP_LVDS_A4- <28>
2
P8
6@ C1293 1 2 0.1U_0402_10V6K~D MXM_EDP_TX0-_C B8 6@ R2076 O0_LVTX_CH4P EDP_LVDS_A4+ <28>
<16> MXM_EDP_TX0- DPRX_ML_L0N
6@ C1294 1 2 0.1U_0402_10V6K~D MXM_EDP_TX0+_C A8 4.7K_0402_5%~D
<16> MXM_EDP_TX0+ DPRX_ML_L0P
6@ C1295 1 2 0.1U_0402_10V6K~D MXM_EDP_TX1-_C B7 G14
<16> MXM_EDP_TX1- DPRX_ML_L1N O1_LVTX_CH0N
SYS, Audio & DPRX

6@ C1296 1 2 0.1U_0402_10V6K~D MXM_EDP_TX1+_C A7 G13
<16> MXM_EDP_TX1+
1
C6 DPRX_ML_L1P @ R2077 O1_LVTX_CH0P
B6 DPRX_ML_L2N A1 EDP_BOOT6 1 2 0_0402_5%~D H14
D5 DPRX_ML_L2P UART_TX/BOOT6/GPIO_13 E4 UART_RX 1 2 0_0402_5%~D O1_LVTX_CH1N H13
C5 DPRX_ML_L3N UART_RX/GPIO_14 @ R2078 O1_LVTX_CH1P
DPRX_ML_L3P J13
B12 EDP_BOOT7 O1_LVTX_CH2N J12
AUX_UART_TX/BOOT7/GPIO_23 A12 O1_LVTX_CH2P
AUX_UART_RX/GPIO_24
Pin E4 : General Purpose Schmitt O1_LVTX_CLKN
K11
K12
O1_LVTX_CLKP
27M_XO A3
TCLK
trigger Input / Tri‐state H11
O1_LVTX_CH5N O1_LVTX_CH3N
L13
J10 L12
Output 14 [5V Tolerant] J11
O1_LVTX_CH5P O1_LVTX_CH3P
M14
K10 O1_LVTX_CH6N O1_LVTX_CH4N M13
C O1_LVTX_CH6P O1_LVTX_CH4P C
27M_XI A2 B1 EDP_BOOT2
XTAL I2S_0/BOOT2/GPIO_8 G5 EDP_BOOT3
I2S_1/BOOT3/GPIO_9 F4 EDP_BOOT4 STDP4010_LFBGA164~D
I2S_2/BOOT4/GPIO_10 E3 EDP_BOOT5
E5 I2S_3/BOOT5/GPIO_11
meet RGB panel sequencing RESETn meet RGB panel sequencing
C2 EDP_BOOT1
+3.3V_AVDD I2S_BCLK/BOOT1/GPIO_7 +3.3V_AVDD
SPI_DI D13 D3 EDP_BOOT0 6@ R2039
SPI_DI/HOST_D1/GPO_19 I2S_WCLK/BOOT0/GPIO_6
1
6@ R2038
SPI_DO E11 EDP_MODE 2 1 4.7K_0402_5%~D

SPI_DO/HOST_D0/GPO_20
2.7K_0402_5%~D
SPI_CLK E12 D2 U629A 6@

SPI_CS# F12 SPI_CLK/HOST_CLK/GPIO_18 I2S_MCLK/GPIO_4 @ R2079
SPI_CSn/HOST_CS/GPIO_17 C1 EDP_MODE EDP_MODE 2 1 4.7K_0402_5%~D L6 N7
CLK_OUT/GPIO_5 M7 E0_LVTX_CH5N E0_LVTX_CH0N P7 EDP_LVDS_B0- <28>
2
G4 E0_LVTX_CH5P E0_LVTX_CH0P EDP_LVDS_B0+ <28>

IR_IN/GPIO_12 G11 L4 M6
D12 NC1 G12 M3 E0_LVTX_CH6N E0_LVTX_CH1N N6 EDP_LVDS_B1- <28>
IRQ/GPIO_25 NC2 C11 E0_LVTX_CH6P E0_LVTX_CH1P EDP_LVDS_B1+ <28>
1 NC3
47P_0402_50V8J~D
6@ C1222
A13 L5
NC4 B4 E0_LVTX_CH2N M5 EDP_LVDS_B2- <28>
NC5 E0_LVTX_CH2P EDP_LVDS_B2+ <28>
2 M4
E0_LVTX_CLKN N4 EDP_LVDS_BCLK- <28>
E0 & E1 LVDS Output

D4 E0_LVTX_CLKP EDP_LVDS_BCLK+ <28>
VBUFC_RPLL E6 N3
PLACE THESE PARTS NEAR STDP4010 GPIO_0 E0_LVTX_CH3N P3 EDP_LVDS_B3- <28>
F3 C3 6@ R2080 1 2 10K_0402_5%~D MXM_EDP_AUX+ E0_LVTX_CH3P EDP_LVDS_B3+ <28>
vendor suggest. TESTMODE0 GPIO_1 N2
E0_LVTX_CH4N P2 EDP_LVDS_B4- <28>
G3 E0_LVTX_CH4P EDP_LVDS_B4+ <28>
6@ TESTMODE1
Y7 27MHZ_12PF_X3G027000FC1H~D M2
27M_XI 1 3 1 2 27M_XO STDP4010_LFBGA164~D E1_LVTX_CH0N M1
IN OUT R2050 0_0402_5%~D E1_LVTX_CH0P
B B
2 4 6@ L3
GND GND E1_LVTX_CH1N L2
E1_LVTX_CH1P
2
6@ 6@ K4
C1225 C1226 E1_LVTX_CH2N K3
15P_0402_50V8J~D E1_LVTX_CH2P
12P_0402_50V8J~D
1
J3
E1_LVTX_CLKN J2
E1_LVTX_CLKP
meet RGB panel sequencing H4 H2
J5 E1_LVTX_CH5N E1_LVTX_CH3N H1
E1_LVTX_CH5P E1_LVTX_CH3P
+3.3V_AVDDL +3.3V_AVDDL +3.3V_AVDD K5 G2
J4 E1_LVTX_CH6N E1_LVTX_CH4N G1
E1_LVTX_CH6P E1_LVTX_CH4P
4.7U_0603_6.3V6K~D
0.1U_0402_10V6K~D
+3.3V_AVDD
6@ C1223
6@ C1224
1 1
1
10K_0402_5%~D
6@ R2040
STDP4010_LFBGA164~D
1
10K_0402_5%~D
6@ R2041
6@ R2073 2 1 1M_0402_5%~D MXM_EDP_AUX+
2 2
BootStraps
6@ R2043 1 2 4.7K_0402_5%~D EDP_BOOT7
2
6@ R2044 1 2 4.7K_0402_5%~D EDP_BOOT6 U630 6@
6@ R2045 1 2 4.7K_0402_5%~D EDP_BOOT5 SPI_CS# 1 8
6@ R2042 1 2 4.7K_0402_5%~D EDP_BOOT4 SPI_DI 2 CS# VCC 7
6@ R2046 1 2 4.7K_0402_5%~D EDP_BOOT3 3 SO HOLD# 6 SPI_CLK
6@ R2047 1 2 4.7K_0402_5%~D EDP_BOOT2 4 WP# SCLK 5 SPI_DO
6@ R2048 1 2 4.7K_0402_5%~D EDP_BOOT1 GND SI
6@ R2049 1 2 4.7K_0402_5%~D EDP_BOOT0 MX25L1005AMC-12G_SO8
6@ R2074 2 1 1M_0402_5%~D MXM_EDP_AUX- 1Mb Flash ROM

R2075 1 2 100K_0402_5% MXM_EDP_HPD
A A
eDP to LVDS(1)
5 4
WWW.AliSaler.Com 3
2
Size
Date:
Document Number

LA-7931P
1
Sheet 30 of 70
Rev
1.0
5 4 3 2 1
WWW.AliSaler.Com
Find 60 R 600 mA @100Mhz
+3.3V_AVDD +3.3V_AVDDL
6@L53
2 1
BLM18PG330SN1D_0603
22U_0805_6.3V6M~D
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
0.01U_0402_25V7K~D
6@ C1239
D D
6@ C1236
6@ C1237
6@ C1238
1 1 1 1
2 2 2 2 +1.2V_RUN U629D 6@
E7 A14
C12 PVDD1 PVSS3 C14
K6 PVDD1 PVSS3 C4
PVDD1 PVSS3
22U_0805_6.3V6M~D
6@ C1245
0.1U_0402_10V6K~D
6@ C1246
0.1U_0402_10V6K~D
6@ C1247
0.1U_0402_10V6K~D
6@ C1248
0.1U_0402_10V6K~D
6@ C1249
K9 F6
E8 PVDD1 PVSS3 F7
1 1 1 1 1 PVDD1 PVSS3 F8
PVSS3 F9
PVSS3 G6
2 2 2 2 2 F5 PVSS3 G7
PVDD22 PVSS3 G8
PVSS3 G9
PVSS3 H6
+1.2V_AVDD PVSS3 H7
F10 PVSS3 H8
meet RGB panel sequencing PVDD21 PVSS3 H9
PVSS3 J6
+3.3V_AVDD PVSS3
22U_0805_6.3V6M~D
6@ C1240
0.1U_0402_10V6K~D
6@ C1241
0.1U_0402_10V6K~D
6@ C1242
0.1U_0402_10V6K~D
6@ C1243
0.1U_0402_10V6K~D
6@ C1244
J7
PWR & GND

B3 PVSS3 J8
VDD_RPLL PVSS3 J9
1 1 1 1 1 PVSS3
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
+3.3V_AVDDL
22U_0805_6.3V6M~D
6@ C1227
6@ C1228
6@ C1229
2 2 2 2 2
1 1 1
D6
L7 VDDA_3V3
C AVDD_LVTX_33 C
2 2 2
E9
+1.2V_AVDD DPRX_VSSA D7
DPRX_VSSA D8
B11 DPRX_VSSA E10
C7 DPRX_VDDA_1V2 DPRX_VSSA
C8 DPRX_VDDA_1V2
D9 DPRX_VDDA_1V2
Find 60 R 600 mA @100Mhz DPRX_VDDA_1V2 B2
+1.2V_AVDD +1.2V_VDD_RPLL VSS_RPLL
meet RGB panel sequencing 6@L54
2 1
+1.2V_RUN +1.2V_AVDD +3.3V_RUN +3.3V_AVDD BLM18PG330SN1D_0603 K7
AVSS_LVTX
22U_0805_6.3V6M~D
6@ C1250
0.1U_0402_10V6K~D
0.01U_0402_25V7K~D
6@ C1252
6@L55 6@L56
6@ C1251
2 1 2 1
BLM18PG330SN1D_0603 BLM18PG330SN1D_0603 1 1 1
+LCDVDD
10U_0603_6.3V6M~D
4.7U_0603_6.3V6K~D
P14
@ L57 AVSS_OUT_LVTX P1
AVSS_OUT_LVTX
6@ C1267
6@ C1268
1 1 2 1 F2
BLM18PG330SN1D_0603 2 2 2 N1 AVSS_OUT_LVTX F13
N14 AVDD_OUT_LVTX_33 AVSS_OUT_LVTX H5
L8 AVDD_OUT_LVTX_33 AVSS_OUT_LVTX K8
2 2 H3 AVDD_OUT_LVTX_33 AVSS_OUT_LVTX H10
H12 AVDD_OUT_LVTX_33 AVSS_OUT_LVTX
AVDD_OUT_LVTX_33
STDP4010_LFBGA164~D
Find 60 R 600 mA @100Mhz

+3.3V_AVDD +3.3V_AVDD_LVTX
6@L52
B 2 1 B
BLM18PG330SN1D_0603
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
22U_0805_6.3V6M~D
6@ C1230
6@ C1231
6@ C1232
6@ C1233
6@ C1234
6@ C1235
1 1 1 1 1 1
Change U631 solution to new p/n: SA00005EU00
2 2 2 2 2 2
meet RGB panel sequencing +1.2V_RUN
U631 6@
+3.3V_AVDD 1 6
POK VOUT
6@ R2051
10U_0805_6.3V6M
3
VIN
1
6@ C1253
4 7
10K_0402_5%
VCNTL FB 1
10U_0805_6.3V6M
GND
GND
6@ C1254
1 2 5
EN NC
2
2
APL5932BKAI-TRG_SO8
8
9
2
6@ R2053
1
20K_0402_5%
2
A A
eDP to LVDS(2)

5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com +5V_RUN +3.3V_RUN
1U_0402_6.3V6K~D
U19 1 1
MAX14885E
C1181
7 29 C1182
<16> MXM_CRT_RED REDA VCC 1U_0603_10V7K~D
17
<19> PCH_CRT_RED REDB 2 2
21
8 VCC
<16> MXM_CRT_GRN GRNA
18 11
Channel A --> GPU <19> PCH_CRT_GRN GRNB VL
9
<16> MXM_CRT_BLU BLUA
19
<19> PCH_CRT_BLU BLUB
D 33 RED_CRT D
5 RED1 24
<16> MXM_CRT_DDC_CLK SCLA RED2 RED_DOCK <46>
15
<19> PCH_CRT_DDC_CLK SCLB 32 GREEN_CRT
6 GRN1 23
<16> MXM_CRT_DDC_DAT
<19> PCH_CRT_DDC_DAT
16 SDAA
SDAB
GRN2
31
GREEN_DOCK <46> Port 1 --> MB Port RGB
BLUE_CRT
Channel B --> PCH +3.3V_RUN 1 2 CRT_EN 2
EN
BLU1
BLU2
22
BLUE_DOCK <46>
R421 100K_0402_5%~D
3 35 CLK_DDC2_CRT
<16> MXM_CRT_HSYNC SHA SCL1
13 26
<19> PCH_CRT_HSYNC SHB SCL2 CLK_DDC2_DOCK <46>
<16> MXM_CRT_VSYNC
4
14 SVA SDA1
34
25
DAT_DDC2_CRT Port 2 --> Docking Port RGB
<19> PCH_CRT_VSYNC SVB SDA2 DAT_DDC2_DOCK <46>
1 37 HSYNC_BUF
<48> EDID_SELECT# S00 SH1
CRT_SWITCH 40 28
<48> CRT_SWITCH S01 SH2 HSYNC_DOCK <46>
39
<27,28,48> DGPU_SELECT# S10
CRT_SWITCH 38 36 VSYNC_BUF
S11 SV1 27
SV2 VSYNC_DOCK <46>
30
20 GND 12
10 GND NC
CRT_SWITCH 0 0 1 1 GND
41
GPAD
DGPU_SELECT# 0 1 0 1 MAX14885EETL+T_TQFN40_5X5~D
EDID_SELECT# 0 1 0 1
A --> Port 1 B --> Port 1 A --> Port 2 B --> Port 2

C C
ESD request reserve it.
2
@ @
D91
D92
+5V_RUN
2
3
1
1
D9
NC
+5V_RUN_CRT BAT1000-7-F_SOT23-3~D
RED_CRT L1 1 2 BLM18BB470SN1D_2P~D RED_CRT_L
1
GREEN_CRT L2 1 2 BLM18BB470SN1D_2P~D GREEN_CRT_L
+CRT_VCC
0.5A_8VDC_SMD1812P200TF
1U_0402_6.3V6K~D
BLUE_CRT L3 1 2 BLM18BB470SN1D_2P~D BLUE_CRT_L
T61
2
22P_0402_50V8J~D
22P_0402_50V8J~D
22P_0402_50V8J~D
0_1206_5%~D
1
1
2
PAD~D
10P_0402_50V8J~D
10P_0402_50V8J~D
10P_0402_50V8J~D
150_0402_1%~D
150_0402_1%~D
150_0402_1%~D
@R49
1 1 1
F5
C14
1 1 1 @
C20
C23
C22
R53
R54
R55
C21
C12
C13
2
CRT_11
1
2 2 2 CONN@
2
1
2 2 2 JCRT1
6
B 11 B
EMI Request. EMI Request. 1
7
DAT_DDC2_CRT 12
2
8 G 16
13 17
G
3 18
G
+CRT_VCC 9 19
G
14
M_ID2# 4
10
CLK_DDC2_CRT 15
5
DAT_DDC2_CRT
SUYIN_070449HR015M221ZR
CLK_DDC2_CRT
Link CIS OK
0.1U_0402_16V4Z~D
1
+5V_RUN_CRT
0722
C15
2
1K_0402_5%~D
1K_0402_5%~D
1
1
@ R50
@ R52
2
L4
HSYNC_BUF 1 2 1 2 HSYNC_L
R43 0_0402_5%~D BLM18AG121SN1D_0603~D
A A
L5
VSYNC_BUF 1 2 1 2 VSYNC_L
R44 0_0402_5%~D BLM18AG121SN1D_0603~D
22P_0402_50V8J~D
22P_0402_50V8J~D
1 1 DELL CONFIDENTIAL/PROPRIETARY
@ C18
@ C19

2 2 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
VGA
WWW.AliSaler.Com

5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com
D D
+3.3V_RUN
AUX/DDC GPU for DPC to E‐DOCK 1 2
C1307
0.1U_0402_25V6K~D
U20
1 14
C
@ R2089 1 2 0_0402_5%~D DPC_DOCK_AUX 2 1 DPC_DOCK_AUX_C 2 BE0 VCC 13 C
<16> MXM_DPB_AUX A0 BE3
C1308 0.1U_0402_10V7K~D
3 12 DPC_DOCK_AUX
<45,46> DPC_DOCK_SW_AUX B0 A3
4 11
@ R2090 1 2 0_0402_5%~D DPC_DOCK_AUX# 2 1 DPC_DOCK_AUX#_C 5 BE1 B3 10
<16> MXM_DPB_AUX# A1 BE2
C1309 0.1U_0402_10V7K~D
6 9 DPC_DOCK_AUX#
<45,46> DPC_DOCK_SW_AUX# B1 A2
7 8
GND B2
PI3C3125LEX_TSSOP14~D
CA_DET Output
A2=B2
HDMI/DVI 1 A3=B3 +5V_RUN
A0=B0 2 1
DP 0 A1=B1 C1310
0.1U_0402_25V6K~D
1
U636
NC
DPC_CA_DET 2 4 DPC_CA_DET#
<45,46> DPC_CA_DET A Y
G
R2128
1 2 NC7ST04P5X_SC70-5~D
3
1M_0402_5%~D prevent material shortage for Thai flood.
B B
A A
Docking DP/DMC MUX
WWW.AliSaler.Com

5 4 3 2 1
5 4 3 2 1
Meet AMD HDMI 297 MHz EA setting.
TMDS_RT 2 1
+3.3V_RUN
4.7K_0402_5%~D R71
DP_CFG0 2 1
4.7K_0402_5%~D R64 @
4.7U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
Choice DDC active buffer mode. TMDS_DDCBUF 2 1
1 1 1 1 1 4.7K_0402_5%~D R68
C410
C405
C437
C402
PEQ 2 1
C766
4.7K_0402_5%~D R70 @
DP_CFG1 2 1
2 2 2 2 2 4.7K_0402_5%~D R72 @
Choice Auto-Switching Mode. MODE 2 1
U9 4.7K_0402_5%~D R58
14 40 DPD_GPU_LANE_P0 TMDS_PRE 2 1
28 VDD33 DP_D0p 39 DPD_GPU_LANE_N0 DPD_GPU_LANE_P0 <46> 4.7K_0402_5%~D R65
D 41 VDD33 DP_D0n DPD_GPU_LANE_N0 <46> D
VDD33 Meet AMD HDMI 297 MHz EA setting.
56 37 DPD_GPU_LANE_P1
VDD33 DP_D1p 36 DPD_GPU_LANE_N1 DPD_GPU_LANE_P1 <46> TMDS_RT 2 1
DP_CFG0 44 DP_D1n DPD_GPU_LANE_N1 <46> 4.7K_0402_5%~D R57 @
DOCKED# 45 DP_CFG0/SCL_CTL 34 DPD_GPU_LANE_P2 DP_CFG0 2 1
38 SW/SDA_CTL DP_D2p 33 DPD_GPU_LANE_N2 DPD_GPU_LANE_P2 <46> 4.7K_0402_5%~D R61 @
I2C_CTL_EN DP_D2n DPD_GPU_LANE_N2 <46> For Docking DP port D TMDS_DDCBUF 2 1
0.1U_0402_10V6K~D 2 1 C253 MXM_DPC_P0_C 3 31 DPD_GPU_LANE_P3 4.7K_0402_5%~D R66 @
<16> MXM_DPC_P0 IN_D0p DP_D3p DPD_GPU_LANE_P3 <46>
0.1U_0402_10V6K~D 2 1 C247 MXM_DPC_N0_C 4 30 DPD_GPU_LANE_N3 PEQ 2 1
<16> MXM_DPC_N0 IN_D0n DP_D3n DPD_GPU_LANE_N3 <46> 4.7K_0402_5%~D R69 @
0.1U_0402_10V6K~D 2 1 C242 MXM_DPC_P1_C 6 55 DPD_DOCK_AUX DP_CFG1 2 1
<16> MXM_DPC_P1 IN_D1p DP_AUXp_SCL DPD_DOCK_AUX <45,46>
0.1U_0402_10V6K~D 2 1 C252 MXM_DPC_N1_C 7 54 DPD_DOCK_AUX# 4.7K_0402_5%~D R73 @
<16> MXM_DPC_N1 IN_D1n DP_AUXn_SDA DPD_DOCK_AUX# <45,46>
MODE 2 1
0.1U_0402_10V6K~D 2 1 C251 MXM_DPC_P2_C 9 32 DPD_GPU_HPD 4.7K_0402_5%~D R63
<16> MXM_DPC_P2 IN_D2p DP_HPD DPD_GPU_HPD <46>
0.1U_0402_10V6K~D 2 1 C254 MXM_DPC_N2_C 10 Meet AMD HDMI 297 MHz EA setting. TMDS_PRE 2 1
<16> MXM_DPC_N2 IN_D2n 42 DPD_CA_DET 4.7K_0402_5%~D R67
DP_CA_DET DPD_CA_DET <45,46>
0.1U_0402_10V6K~D 2 1 C245 MXM_DPC_P3_C 12 DPD_CA_DET 2 1
<16> MXM_DPC_P3 IN_D3p
0.1U_0402_10V6K~D 2 1 C246 MXM_DPC_N3_C 13 29 DP_CFG1 1M_0402_5%~D R491
<16> MXM_DPC_N3 IN_D3n DP_CFG1
0.1U_0402_10V6K~D 2 1 C389 MXM_DPC_AUX_C 52 19 TMDSE_RP_P0
<16,45> MXM_DPC_AUX IN_AUXp TMDS_CH0p
Change from 100k to 10kohm 0.1U_0402_10V6K~D 2 1 C390 MXM_DPC_AUX#_C 51 18 TMDSE_RP_N0
<16,45> MXM_DPC_AUX# IN_AUXn TMDS_CH0n
to meet the input high-level voltage. 50 22 TMDSE_RP_P1
49 IN_DDC_SCL TMDS_CH1p 21 TMDSE_RP_N1
+3.3V_RUN IN_DDC_SDA TMDS_CH1n
11 25 TMDSE_RP_P2
IN_CA_DET TMDS_CH2p
10K_0402_5%~D
24 TMDSE_RP_N2
TMDS_CH2n For HDMI
1
MXM_DPC_HPD 5 MODE = L: Control Switching Mode, HDMI ID disable
<16> MXM_DPC_HPD IN_HPD
R518
16 TMDSE_RP_CLK
TMDS_CLKp 15 TMDSE_RP_CLK# = H: Automatic Switching Mode, HDMI ID disable
TMDS_CLKn
CEXT 1 48 HDMI_SCL_SINK
= M: Automatic Switching Mode, HDMI ID enable
2
CEXT TMDS_SCL 47 HDMI_SDA_SINK

TMDS_DDCBUF 2 TMDS_SDA
TMDS_DDCBUF 17 HDMI_HPD_SINK
TMDS_PRE = L: no pre‐emphasis
DOCKED# PEQ 8 TMDS_HPD = H: 1.5dB pre‐emphasis
PEQ 23 TMDS_RT
REXT3 CEXT REXT3 27 TMDS_RT 20 TMDS_PRE
= M: 3.0dB pre‐emphasis
Q328 REXT TMDS_PRE
1
SSM3K7002FU_SC70-3~D D 46 26
PD GND
4.99K_0402_1%~D
2 35 TMDS_RT = L: Standard open drain driver
<37,48> DOCKED GND
2
2.2U_0402_6.3V6M
G MODE 53 43
C MODE GND 57 = H: Open drain driver with termination resistors C
S 1
3
Thermal/GND
R74
C86
PS8336BQFN56GTR-A0_QFN56_7X7
TMDS_DDCBUF = L: DDC pass through
1
2
= H: DDC active buffer
= M: DDC pass through with 40 kohm pull up resistor
For Control Switching: PEQ = L: default, LEQ, compensate channel loss up to 12dB @ HBR2
SW = L: DP output is selected = H: HEQ, compensate channel loss up to 15dB @ HBR2
SW = H: TMDS output is selected = M: LLEQ, compensate channel loss up to 5dB @ HBR2
DP_CFG1 = L: default, auto test disable & input offset cancellation enable
= H: auto test enable & input offset cancellation enable
= M: auto test disable & input offset cancellation disable
DP_CFG0 = L: default, automatic EQ enable & AUX interception enable
EMI request.(for PT2) = H: automatic EQ disable & AUX interception enable
= M: automatic EQ disable & AUX interception disable, no pre‐emphasis, 800mVpp swing
@ R451 1 2 EMI request reserve C(3.3pF) for HDMI signals.
0_0402_5%~D +5V_RUN
L19
TMDSE_RP_CLK 4 3 TMDSE_CON_CLK
2
3
4 3
D12
NC
BAT1000-7-F_SOT23-3~D
TMDSE_RP_CLK# 1 2 TMDSE_CON_CLK#
1 2
3.3P_0402_50V8C~D
3.3P_0402_50V8C~D
DLW21SN900HQ2L_0805_4P~D
1
+5V_RUN_HDMI
1 @ 1 @
C1334
C1333
0.5A_8VDC_SMD1812P200TF
1 2
@ R452 0_0402_5%~D
B 2 2
HDMI CONN B
2
0_1206_5%~D
@ R453 1 2
@ R45
0_0402_5%~D
F4
+VDISPLAY_VCC
L23
1
TMDSE_RP_P0 4 3 TMDSE_CON_P0
4 3
0.1U_0402_10V7K~D
10U_0805_10V4Z~D
TMDSE_RP_N0 1 2 TMDSE_CON_N0 1 1
1 2
3.3P_0402_50V8C~D
3.3P_0402_50V8C~D
RB751V-40GTE-17_SOD323-2~D
+5V_RUN
C337
C338
1 @ 1 @
2 2
C1335
C1336
1 2
2
@ R454 0_0402_5%~D
1
2 2
@ R1169
@
0_0402_5%~D
D70
@ R455 1 2 JHDMI1 CONN@

0_0402_5%~D HDMI_HPD_SINK 1 2 HDMI_HPD_SINK_R 19
2
R1164 10K_0402_5%~D 18 HP_DET

1
17 +5V
L24 R460 1 2 1.5K_0402_5%~D HDMI_SDA_SINK HDMI_SDA_SINK 16 DDC/CEC_GND
TMDSE_RP_P1 4 3 TMDSE_CON_P1 +5V_HDMI_DDC R461 1 2 1.5K_0402_5%~D HDMI_SCL_SINK HDMI_SCL_SINK 15 SDA
4 3 14 SCL
HDMI_CEC 13 Reserved
TMDSE_RP_N1 1 2 TMDSE_CON_N1 TMDSE_CON_CLK# 12 CEC
1 2 CK-
3.3P_0402_50V8C~D
3.3P_0402_50V8C~D
11
DLW21SN900HQ2L_0805_4P~D TMDSE_CON_CLK 10 CK_shield
@ @ TMDSE_CON_N0 9 CK+
1 1 D0-
+3.3V_RUN
C1337
C1338
8
1 2 TMDSE_CON_P0 7 D0_shield
@ R456 0_0402_5%~D TMDSE_CON_N1 6 D0+
2 2 HDMI_CEC 1 2 5 D1-
10K_0402_5%~D R1165 TMDSE_CON_P1 4 D1_shield 20
@ R459 1 2 HDMI_HPD_SINK 1 2 TMDSE_CON_N2 3 D1+ GND 21
0_0402_5%~D 100K_0402_5%~D R1128 2 D2- GND 22
TMDSE_CON_P2 1 D2_shield GND 23
D2+ GND
L25 FOX_QJ1119L-BT11-7H
A TMDSE_RP_P2 4 3 TMDSE_CON_P2 A
4 3
TMDSE_RP_N2 1
1 2
2 TMDSE_CON_N2 Link CIS OK
3.3P_0402_50V8C~D
3.3P_0402_50V8C~D
1 @ 1 @ 0722
C1339
C1340
HDMI 46@
1 2 Part Number Description
@ R458 0_0402_5%~D
2 2
RO0000002HM HDMI W/Logo:RO0000002HM DELL CONFIDENTIAL/PROPRIETARY
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT HDMI CONN
WWW.AliSaler.Com
pop R451~R456,R458,R459 and non-pop L19,L23,L24,L25 for HDMI EA.(for PT1) PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7931P 1.0

5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
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R501
1
2 DDR_XDP_WAN_SMBDAT
10K_0402_5%~D
2 DDR_XDP_WAN_SMBCLK HDD PWR
R502 10K_0402_5%~D
1 2 HDD_FALL_INT
R503 100K_0402_5%~D +5V_ALW
+PWR_SRC_S
+5V_HDD
100K_0402_5%~D
+3.3V_ALW2
1
100K_0402_5%~D
1
R499
1
2
5
6
+3.3V_RUN
@ R506
1
100K_0402_5%~D
D
Free Fall Sensor
100K_0402_5%~D
R500
D +3.3V_RUN G @ Q27 D
2
1
+HDD_EN_5V 3 SI3456DDV-T1-GE3_TSOP6~D
2
R513
S
@ 1M_0402_5%~D
0.1U_0603_50V7K~D
FFS_INT2_Q +5V_HDD +5V_RUN
4
3
10U_0603_6.3V6M~D
0.1U_0402_25V6K~D @ PJP33
1
1 1 2
2
1 2
Q300B
R2125
C393
1 1
10U_0805_10V6K~D
100K_0402_5%~D
U88 5 JUMP_43X79
1
C392
C391
Q29B
LNG3DM 1 SHORT DEFAULT
6
2
R504
10 5
2
2 2 RES
C394
1 13
VDD_IO RES
6
Q300A
14 15
4
VDD RES 16 1 2 2 2
<47,48,52,56> RUN_ON
2
RES
Q29A
HDD_FALL_INT 11 @ R1621 0_0402_5%~D
<20> HDD_FALL_INT INT 1
100K_0402_5%~D
FFS_INT2 9 5 2
1
INT 2 GND <21> FFS_INT2
1
@ R505
12 @ R1624 1 2 0_0402_5%~D
GND <11,19,47,48,52,56> SIO_SLP_S3#
7
1
6 SDO/SA0
<12,13,14,15,17,18,43> DDR_XDP_WAN_SMBDAT SDA / SDI / SDO
4
<12,13,14,15,17,18,43> DDR_XDP_WAN_SMBCLK SCL/SPC 2
2
8 NC 3
CS NC
LNG3DMTR_LGA16_3X3~D
C
For SATA Gen2, Gen3 EA setting C
+3.3V_RUN
+3.3V_RUN B_PRE1 2 1 X761@

4.7K_0402_5%~D R1173
HDD Redriver Select Component A_PRE1 2 1 X761@
4.7K_0402_5%~D R1201
TEST 2 1 @
X76(Main) X76(2nd)
0.01U_0402_16V7K~D
0.1U_0402_16V4Z~D
4.7K_0402_5%~D R1175
X7641231L01 X7641231L02 HDD Repeater 1 1 A_PRE0 2
4.7K_0402_5%~D
1 X761@
R1202
C420
C419
B_PRE0 2 1 X761@
PARADE(Main) MAXIM(2nd) 4.7K_0402_5%~D R1204
U26 X76@ 2 2
SA00004WF00 SA00002EY1L @ C24 1 2 1U_0402_6.3V6K~D SATA_EN 7 6 REXT 2 1 @
EN VDD 16 4.99K_0402_1%~D R1206
C423 2 1 0.01U_0402_16V7K~D PSATA_PTX_DRX_P0 1 VDD
U26 V V <17> PSATA_PTX_DRX_P0_C
C422 2 1 0.01U_0402_16V7K~D PSATA_PTX_DRX_N0 2 A_INp 10 MAXIM_PWR
<17> PSATA_PTX_DRX_N0_C A_INn NC 20 REXT
C418 2 1 0.01U_0402_16V7K~D PSATA_PRX_DTX_P0 5 REXT
<17> PSATA_PRX_DTX_P0_C C421 2 1 0.01U_0402_16V7K~D PSATA_PRX_DTX_N0 4 B_OUTp 9 A_PRE0
R1173 V <17> PSATA_PRX_DTX_N0_C B_OUTn A_PRE0 8 B_PRE0
B_PRE1 17 B_PRE0
A_PRE1 19 B_PRE1 15 PSATA_PTX_DRX_P0_RP +3.3V_RUN
A_PRE1 A_OUTp 14 PSATA_PTX_DRX_N0_RP
R1201 V TEST 18 A_OUTn MAXIM_PWR 1 2 X762@
3 TEST 11 PSATA_PRX_DTX_P0_RP 0_0402_5%~D R2180
13 GND B_INp 12 PSATA_PRX_DTX_N0_RP REXT 1 2 X762@
21 GND B_INn 0_0402_5%~D R2181
R1175 EPAD SATA_EN 1 2 X762@
PS8520BTQFN20GTR2_TQFN20_4X4 0_0402_5%~D R2182
R1202 V B_PRE1 1 2 X762@

0_0402_5%~D R2183
B R1204 V
Main: SA00004WF00 (PS8520) TEST 1
0_0402_5%~D
2 X762@
R2184 B
2nd: SA00002EY1L (MAX4951) 2nd source for SATA redriver

R1206
For HDD Temp. (Add X762@ for 2nd source option.)
R2180 V JSATA1 CONN@
1
PSATA_PTX_DRX_P0_RP C383 2 1 0.01U_0402_16V7K~D SATA_PTX_DRX_P0 2 GND
PSATA_PTX_DRX_N0_RP C384 2 1 0.01U_0402_16V7K~D SATA_PTX_DRX_N0 3 RX+
R2181 V 4 RX-
PSATA_PRX_DTX_N0_RP C385 2 1 0.01U_0402_16V7K~D SATA_PRX_DTX_N0 5 GND
PSATA_PRX_DTX_P0_RP C386 2 1 0.01U_0402_16V7K~D SATA_PRX_DTX_P0 6 TX-
7 TX+
R2182 V GND
+3.3V_RUN 8
9 3.3V
10 3.3V
R2183 V 11 3.3V
HDD1_DET# 12 GND
<17> HDD1_DET# 13 GND
14 GND
R2184 V +5V_HDD
15 5V
+3.3V_RUN +5V_HDD 16 5V
17 5V
FFS_INT2_Q 18 GND 23
Reserved GND1
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1000P_0402_50V7K~D
0.1U_0402_25V6K~D
19 24
20 GND GND2
21 12V
1 1 1 1 12V
22
12V
C404
C403
C395
C406
SUYIN_127043HB022M26GZL
2 2 2 2
A
Link CIS OK A
Pleace near HDD CONN Pleace near HDD CONN
HDD CONN
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5 4 3 2 1
5 4 3 2 1
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D D
+5VMOD Source
+PWR_SRC_S +5V_ALW
1
470K_0402_5%~D
+3.3V_ALW2
R515
100K_0402_5%~D
1
2
5
6
R516
D Q30
2
G SI3456DDV-T1-GE3_TSOP6~D
+MOD_EN 3
S
3
0.022U_0603_50V7~D
+5V_MOD +5V_RUN
4
4.7M_0402_5%~D
@ PJP32
1
Q301B
1 1 2
1 2
R2126
10U_0805_10V6K~D
MODC_EN# 5
1
C416
100K_0402_5%~D
1 JUMP_43X79
6
R517
4
2
C417
2
Q301A
C C
2 2
<48> MODC_EN
2
1
100K_0402_5%~D
1
R514
Solve 300mW
PWR consumption
2
issue.
+3.3V_ALW
1 2 ZODD_WAKE#
R796 10K_0402_5%~D ODD CONN
JODD1 CONN@
2 1 SATA_ODD_PTX_DRX_P3 1
<17> SATA_ODD_PTX_DRX_P3_C GND
C433 0.01U_0402_16V7K~D 2
2 1 SATA_ODD_PTX_DRX_N3 3 RX+
<17> SATA_ODD_PTX_DRX_N3_C RX-
C434 0.01U_0402_16V7K~D 4
2 1 SATA_ODD_PRX_DTX_N3 5 GND
<17> SATA_ODD_PRX_DTX_N3_C C432 0.01U_0402_16V7K~D 6 TX-
2 1 SATA_ODD_PRX_DTX_P3 7 TX+
<17> SATA_ODD_PRX_DTX_P3_C C430 0.01U_0402_16V7K~D GND
B 8 B
<49> DEVICE_DET# 9 DP
+5V_MOD +5V
10
1 2 11 +5V
<48> ZODD_WAKE# MD
R792 0_0402_5%~D 12 14
13 GND GND1 15
GND GND2
FOX_LN21131-D009-9H
+5V_MOD
Link CIS OK
0722
1000P_0402_50V7K~D
0.1U_0402_16V4Z~D
1 1
C428
C429
2 2
Pleace near ODD CONN
A A
ODD CONN

5 4 3 2 1
5 4 3 2 1
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+3.3V_LAN +3.3V_RUN
10K_0402_5%~D
1 2 TP_LAN_JTAG_TMS
1
@ R545 10K_0402_5%~D +1.0V_LAN +1.05V_M
R547
1 2 TP_LAN_JTAG_TCK
@ R546 10K_0402_5%~D L29
REGCTL_PNP10 1 2 1 2
4.7UH_CBC2012T4R7M_20%~D @ R548 0_0805_5%~D
10U_0603_6.3V6M~D
0.1U_0402_10V7K~D
U31
@ R1187 Idc max=330mA 1 1
C462
C463
1 2 LANCLK_REQ#_R 48 13 LAN_TX0+
<18> LANCLK_REQ# 0_0402_5%~D 36 CLK_REQ_N MDI_PLUS0 14 LAN_TX0-
<20> PLTRST_LAN# PE_RST_N MDI_MINUS0
CLK_PCIE_LAN 44 17 LAN_TX1+ 2 2
<18> CLK_PCIE_LAN PE_CLKP MDI_PLUS1
CLK_PCIE_LAN# 45 18 LAN_TX1-
<18> CLK_PCIE_LAN#
PCIE
PE_CLKN MDI_MINUS1
MDI
D
2 1 PCIE_PRX_GLANTX_P7_C D
<18> PCIE_PRX_GLANTX_P7
C458 0.1U_0402_10V7K~D 38 20 LAN_TX2+
2 1 PCIE_PRX_GLANTX_N7_C 39 PETp MDI_PLUS2 21 LAN_TX2-
<18> PCIE_PRX_GLANTX_N7 PETn MDI_MINUS2
C459 0.1U_0402_10V7K~D
+3.3V_LAN 1 2 PCIE_PTX_GLANRX_P7_C 41 23 LAN_TX3+
<18> PCIE_PTX_GLANRX_P7 PERp MDI_PLUS3
C460 0.1U_0402_10V7K~D 42 24 LAN_TX3-
1 2 PCIE_PTX_GLANRX_N7_C PERn MDI_MINUS3
<18> PCIE_PTX_GLANRX_N7 Place R548, C462, C463 and L29 close to U31
1
C461 0.1U_0402_10V7K~D
R549 @ R551 1 2 0_0402_5%~D LAN_SMBCLK_R 28 6
<18> LAN_SMBCLK
SMBUS
10K_0402_5%~D @ R552 1 2 0_0402_5%~D LAN_SMBDATA_R 31 SMB_CLK RSVD_NC
<18> LAN_SMBDATA SMB_DATA 1 +RSVD_VCC3P3_1 R553 2 1 4.7K_0402_5%~D +3.3V_LAN
RSVD_VCC3P3_1 2 +RSVD_VCC3P3_2 R554 2 1 4.7K_0402_5%~D
SMBus Device Address 0xC8
2
@ R555 RSVD_VCC3P3_2 5 +1.0V_LAN

1 2 LAN_DISABLE#_R 3 VDD3P3_IN +3.3V_LAN
<21> PM_LANPHY_ENABLE LAN_DISABLE_N
0_0402_5%~D 4 +3.3V_LAN_OUT
VDD3P3_OUT
<48> LAN_DISABLE#_R
22U_0805_6.3V6M~D
15 1
VDD3P3_15
1
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
22U_0805_6.3V6M~D
LOM_ACTLED_YEL# 26 19
@ R557 LOM_SPD100LED_ORG# 27 LED0 VDD3P3_19 29 C464
LED1 VDD3P3_29 1 1 1 1 1 1
LED
C1177
C1178
10K_0402_5%~D LOM_SPD10LED_GRN# 25 1U_0603_10V7K~D
LED2 2
C466
C467
C468
C469
47 +1.0V_LAN
2
VDD1P0_47 46 2 2 2 2 2 2
@ T142 PAD~D TP_LAN_JTAG_TDI 32 VDD1P0_46 37
@ T143 PAD~D TP_LAN_JTAG_TDO 34 JTAG_TDI VDD1P0_37
JTAG_TDO
JTAG
TP_LAN_JTAG_TMS 33 43
TP_LAN_JTAG_TCK 35 JTAG_TMS VDD1P0_43
JTAG_TCK 11 Note:
VDD1P0_11
+1.0V_LAN will work at 0.95V to 1.15V Place C1178 close to pin5
XTALO_R 1 2 XTALO 9 40
@ R1144 0_0402_5%~D XTALI 10 XTAL_OUT VDD1P0_40 22
Y3 XTAL_IN VDD1P0_22 16
25MHZ_18PF_X3G025000DI1H-H~D VDD1P0_16 8
1 3 LAN_TEST_EN 30 VDD1P0_8
IN OUT TEST_EN +1.0V_LAN POWER OPTIONS
33P_0402_50V8J~D
33P_0402_50V8J~D
2 4 RES_BIAS 12 7 REGCTL_PNP10 Shared with PCH

GND GND RBIAS CTRL_1P0
1 1 1.05V SVR * Internal SRV
C471
3.01K_0402_1%~D
C
49 C
VSS_EPAD
C470
1
1K_0402_1%~D
R561
R562
82579_QFN48_6X6~D STUFF: R548 STUFF: L29

2 2
NO STUFF: L29 NO STUFF: R548
2
Need to verify A3 silicon drive

power before removing C427
CPN : SA00003SI3L
KDS crystal vender verify
driving level in A3
+PWR_SRC_S Q34 +3.3V_LAN +3.3V_M

+3.3V_ALW SI3456DDV-T1-GE3_TSOP6~D
100K_0402_5%~D
1
D
6 @ R563
S
R564
+3.3V_ALW2 5 4 2 1
2 0_1206_5%~D
10U_0603_6.3V6M~D
0.1U_0402_10V7K~D
1 1 1
100K_0402_5%~D
G
2
1
C475
C476
3
R565
+ENAB_3VLAN 2 2
+3.3V_LAN
3
2200P_0402_50V7K~D
2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1M_0402_5%~D
1
Q297B
1 1 1 1
R1638
5
C472
C473
C474
C477
LAN ANALOG
6
4
2 2 2 2
SWITCH
2
Q297A
2
39
30
21
14
<19,48> SIO_SLP_LAN#
8
4
1
B U32 B
VDD
VDD
VDD
VDD
VDD
VDD
VDD
1
38 SW_LAN_TX3-
B0+ SW_LAN_TX3- <38>
37 SW_LAN_TX3+
B0- SW_LAN_TX3+ <38>
LAN_TX3- 1 2 LAN_TX3-R 2
L37 12NH_0603CS-120EJTS_5%~D A0+ 34 SW_LAN_TX2-
LAN_TX3+ 1 2 LAN_TX3+R 3 B1+ 33 SW_LAN_TX2+ SW_LAN_TX2- <38>
L36 12NH_0603CS-120EJTS_5%~D A0- B1- SW_LAN_TX2+ <38>
29 SW_LAN_TX1-
B2+ SW_LAN_TX1- <38>
LAN_TX2- 1 2 LAN_TX2-R 6 28 SW_LAN_TX1+
A1+ B2- SW_LAN_TX1+ <38>
L35 12NH_0603CS-120EJTS_5%~D
LAN_TX2+ 1 2 LAN_TX2+R 7 25 SW_LAN_TX0-
A1- B3+ SW_LAN_TX0- <38>
L34 12NH_0603CS-120EJTS_5%~D 24 SW_LAN_TX0+
B3- SW_LAN_TX0+ <38>
LAN_TX1- 1 2 LAN_TX1-R 9 17 LAN_ACTLED_YEL#
A2+ LEDB0 LAN_ACTLED_YEL# <38>
L32 12NH_0603CS-120EJTS_5%~D 18 LED_100_ORG#
LEDB1 LED_100_ORG# <38> +3.3V_LAN
LAN_TX1+ 1 2 LAN_TX1+R 10 41 LED_10_GRN# C478
A2- LEDB2 LED_10_GRN# <38>
L33 12NH_0603CS-120EJTS_5%~D 0.1U_0402_10V7K~D
36 DOCK_LOM_TRD3- 1 2
C0+ DOCK_LOM_TRD3- <46>
LAN_TX0- 1 2 LAN_TX0-R 11 35 DOCK_LOM_TRD3+
A3+ C0- DOCK_LOM_TRD3+ <46>
L31 12NH_0603CS-120EJTS_5%~D
5
LAN_TX0+ 1 2 LAN_TX0+R 12 32 DOCK_LOM_TRD2- U15
L30 12NH_0603CS-120EJTS_5%~D A3- C1+ 31 DOCK_LOM_TRD2+ DOCK_LOM_TRD2- <46> LOM_SPD100LED_ORG# 1
P
C1- DOCK_LOM_TRD2+ <46> IN1 4
13 27 DOCK_LOM_TRD1- LOM_SPD10LED_GRN# 2 O WLAN_LAN_DISB# <48>
<34,48> DOCKED SEL C2+ DOCK_LOM_TRD1- <46> IN2
G
26 DOCK_LOM_TRD1+
C2- DOCK_LOM_TRD1+ <46>
3
LOM_ACTLED_YEL# 15 23 DOCK_LOM_TRD0-
LEDA0 C3+ DOCK_LOM_TRD0- <46>
LOM_SPD100LED_ORG# 16 22 DOCK_LOM_TRD0+ prevent material shortage for Thai flood.
LEDA1 C3- DOCK_LOM_TRD0+ <46>
Layout Notice : Place bead as LOM_SPD10LED_GRN# 42
LEDA2 19 DOCK_LOM_ACTLED_YEL#
close PI3L500 as possible 5 LEDC0 20 DOCK_LOM_SPD100LED_ORG#
DOCK_LOM_ACTLED_YEL# <46>
PD LEDC1 DOCK_LOM_SPD100LED_ORG# <46>
40 DOCK_LOM_SPD10LED_GRN#
LEDC2 DOCK_LOM_SPD10LED_GRN# <46>
43
PAD_GND
1: TO DOCK
FROM NIC DOCKED
A 0: TO RJ45 PI3L720ZHEX_TQFN42_9X3P5~D
TO A
DOCK
LAN/LAN SW
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5 4 3 2 1
5 4 3 2 1
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D D
change to SP050006P0L for LAN EA.
T156
SW_LAN_TX0+ 1 1:1 24 NB_LAN_TX0+

<37> SW_LAN_TX0+ TD1+ TX1+
+3.3V_LAN
SW_LAN_TX0- 2
<37> SW_LAN_TX0- TD1- 23 NB_LAN_TX0-
TX1-
0.1U_0402_10V7K~D
1U_0603_10V6K~D
470P_0402_50V7K~D
+TRM_CT1 3 22 Z2805 1 1 1
TDCT1 TXCT1
C483
C481
C1167
+TRM_CT2 4 21 Z2807 2
TDCT2 TXCT2 2 2
SW_LAN_TX1+ 5 1:1 20 NB_LAN_TX1+
<37> SW_LAN_TX1+ TD2+ TX2+
0.47U_0603_10V7K~D
0.47U_0603_10V7K~D
1 1
+3.3V_LAN:20mils
6 19 +3.3V_LAN
C480
SW_LAN_TX1- NB_LAN_TX1-
C479
<37> SW_LAN_TX1- TD2- TX2-

C 2 2 C
JLOM1 CONN@
1 2 13
<37> LAN_ACTLED_YEL# Yellow LED-
R1171 150_0402_5%~D
SW_LAN_TX2+ 7 1:1 18 NB_LAN_TX2+ 12
<37> SW_LAN_TX2+ TD3+ TX3+ Yellow LED+
NB_LAN_TX3- 8
PR4-
SW_LAN_TX2- 8 NB_LAN_TX3+ 7
<37> SW_LAN_TX2- TD3- PR4+
17 NB_LAN_TX2-
TX3- NB_LAN_TX1- 6
PR2-
+TRM_CT3 9 16 Z2806 NB_LAN_TX2- 5
TDCT3 TXCT3 PR3-
NB_LAN_TX2+ 4
+TRM_CT4 10 15 Z2808 PR3+
TDCT4 TXCT4 for ESD Hi-Pot fail.
75_0402_1%~D
75_0402_1%~D
75_0402_1%~D
75_0402_1%~D
SW_LAN_TX3+ 11 1:1 14 NB_LAN_TX3+ NB_LAN_TX1+ 3
<37> SW_LAN_TX3+ TD4+ TX4+ PR2+
0.47U_0603_10V7K~D
0.47U_0603_10V7K~D
1 1 NB_LAN_TX0- 2 15
PR1- SHLD2
C484
C486
NB_LAN_TX0+ 1 14
SW_LAN_TX3- 12 13 NB_LAN_TX3- PR1+ SHLD1
2 2 <37> SW_LAN_TX3- TD4- TX4- 1 2 10
<37> LED_10_GRN# Green LED-
R1170 150_0402_5%~D
1
9
LED+
350uH_IH-115-F~D
1 2 11
<37> LED_100_ORG# ORANGE_LED-
R1167 150_0402_5%~D
TYCO_2041333-1~D
GND
R571 2
R572 2
R573 2
R574 2
CHASSIS
B 1 2
Link CIS OK B
C485 1000P_1808_3KV7K~D
0722
GND_CHASSIS
A A
RJ45
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5 4 3 2 1
5 4 3 2 1
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D D
+5V_ESATA_PWR
0.1U_0402_16V4Z~D
C L51 C
150U_B2_6.3V-M~D
4 3 USBP9_D+
<20> USBP9+ 4 3
1
1
+5V_ESATA_PWR
C667
C668
+5V_ALW U48 1 2 USBP9_D- +
PJP31 <20> USBP9- 1 2
@ 1 10
2 1 +5V_ALW_ESATA 2 GND FAULT1# 9 DLW21SN900SQ2L_0805_4P~D JESA1 CONN@
2 1 IN OUT1 2 2
10U_0805_10V4Z~D
3 8 1 2
IN OUT2
0.1U_0402_16V4Z~D
JUMP_43X79 4 7 @ R736 0_0402_5%~D 1 USB

5 EN1# ILIM 6 USBP9_D- 2 USB_V
1 1 <48> ESATA_USB_PWR_EN# EN2# FAULT#2 USB_OC4# <20> USB_D-
11 1 2 USBP9_D+ 3
T-PAD USB_D+
24.9K_0402_1%~D
C676
C675
@ R742 0_0402_5%~D 4
USB_GND
1
TPS2560DRCR-PG1.1_SON10_3X3~D
2 2 5
R783
C671 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P4 6 GND
<17> ESATA_PTX_DRX_P4_C A+
C672 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N4 7 ESATA
<17> ESATA_PTX_DRX_N4_C A-
2 D73 8 12
USBP9_D- 2 C673 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N4 9 GND GND 13
1 <17> ESATA_PRX_DTX_N4_C C674 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P4 10 B- GND 14
<17> ESATA_PRX_DTX_P4_C B+ GND
USBP9_D+ 3 11 15
GND GND
PESD5V0U2BT_SOT23-3~D TAIWI_EU093-117CRL-TW
Link CIS OK
0722
B B
A A
Title
ESATA
5 4 3 2 1
5 4 3 2 1
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For USB3 redriver 2nd source
+USB3
+5V_USB_PWR1
1 2 USB3_TEST JUSB1 CONN@
@ R26 4.7K_0402_5%~D EQ : Equalizer control and program, TEST : Chip test mode enable. 1
1 2 USB3_B_EQ0 USBP0_R_D- 2 VBUS
3.3V tolerant. Internally pulled down at ~150K ohm 3.3V tolerant. Internally pulled down at ~150K ohm.
R18 4.7K_0402_5%~D USBP0_R_D+ 3 D-
Solve kingston issue.
[A_EQ1, A_EQ0] == L: Normal operation (default) For EMI request D+

1 2 USB3_B_EQ1 LL: program EQ for channel loss up to 4.5dB H: Test mode enable 4
@ R27 4.7K_0402_5%~D L42 USB3_RX1_N_D- 5 GND
LH: program EQ for channel loss up to 7.5dB for compliance test, this pin should be pulled to high. SSRX-
1 2 USB3_B_DE0 HL: program EQ for channel loss up to 9.5dB USB3TP1_RP 3 4 USB3_TX1_P_D+ ESD request change main source to SC300002F0L. USB3_RX1_P_D+ 6 10
R28 4.7K_0402_5%~D 3 4 7 SSRX+ GND 11
HH: program EQ for channel loss up to 13dB GND GND
1 2 USB3_B_DE1 USB3_TX1_N_D- 8 12
R30 4.7K_0402_5%~D USB3TN1_RP 2 1 USB3_TX1_N_D- USB3_TX1_P_D+ 9 SSTX- GND 13
D
1 2 USB3_A_EQ0 2 1 For ESD request SSTX+ GND D
R24 4.7K_0402_5%~D DLW21SN900HQ2L_0805_4P~D LOTES_AUSB0041-P001A

1 2 USB3_A_EQ1 DE : Programmable output pre-emphasis level setting, Pin 13 : B_EQ0 / SDA_CTL Pin28 : A_DE1 / NC
@ R22
1 2
4.7K_0402_5%~D
USB3_A_DE0
3.3V tolerant. Internally pulled down at ~150K ohm
[A_DE1, A_DE0] ==
Pin 14 : B_EQ1 / SCL_CTL
Pin 15 : B_DE0 / I2C_ADDR0
Pin29 : A_DE0 / NC
Pin31 : A_EQ1 / NC @ R743
1 2
0_0402_5%~D USB3_TX1_P_D+ 1
D14
10 USB3_TX1_P_D+
Link CIS OK
R23
1 2
4.7K_0402_5%~D
USB3_A_DE1
LL: 3.5dB de-emphasis
LH: No de-emphasis
Pin 16 : B_DE1 / I2C_ADDR1 Pin32 : A_EQ0 / NC
@ R744
1 2
0_0402_5%~D USB3_TX1_N_D- 2 9 USB3_TX1_N_D- 0305
R25 4.7K_0402_5%~D HL: 2.7dB de-emphasis
Vender suggest for EA. HH: 5dB de-emphasis USB3_RX1_P_D+4 7 USB3_RX1_P_D+
L40 USB3_RX1_N_D- 5 6 USB3_RX1_N_D-

USB3RP1_RP 3 4 USB3_RX1_P_D+
3 4 3
+3.3V_RUN +USB3 USB3RN1_RP 2 1 USB3_RX1_N_D- 8 +5V_USB_PWR1

2 1
R2196 1 X761@ 2 0_0402_5%~D
For USB3 redriver 2nd source For USB3 redriver 2nd source DLW21SN900HQ2L_0805_4P~D IP4292CZ10-TBR_XSON10_2.5X1~D
+1.5V_MEM
10U_0603_6.3V6M~D
+USB3 +USB3 1 2 1
150U_B2_6.3V-M~D
@ R746 0_0402_5%~D 1
C324
C793
R2197 1 X762@ 2 0_0402_5%~D 1 2 +
@ R745 0_0402_5%~D
For USB3 redriver 2nd source 2 2
0.01U_0402_16V7K~D
0.1U_0402_16V4Z~D
EMI request. D15
1 1 USBP0_R_D- 2
L39 1
C453
C450
USBP0_D+ 2 1 USBP0_R_D+ USBP0_R_D+ 3
2 1
2 2 PESD5V0U2BT_SOT23-3~D
USBP0_D- 3 4 USBP0_R_D-
3 4
DLW21SN900SQ2L_0805_4P~D
U638 X76@ 1 2
@ R749 0_0402_5%~D
33 Vender suggest. NEC_TOKIN shortage issue for the flood in Tailand and small size for ME space.
USB3TN1_RP 0.1U_0402_16V4Z~D 1 2 C488 USB3TN1_RP_C 1 EPAD 32 USB3_A_EQ0 1 2
USB3TP1_RP 0.1U_0402_16V4Z~D 1 2 C489 USB3TP1_RP_C 2 A1_OUTn A_EQ0 31 USB3_A_EQ1 @ R748 0_0402_5%~D
C A1_OUTp A_EQ1 C
3 30 R2141 2 1 4.7K_0402_1%~D
USB3RN1_RP 4 GND REXT 29 USB3_A_DE0
USB3RP1_RP 5 B1_INn A_DE0 28 USB3_A_DE1
6 B1_INp A_DE1 27 USB3TN1_C 0.1U_0402_16V4Z~D 1 2 C452
I2C_EN A1_INn USB3TN1 <20>
USB3TN2_RP 0.1U_0402_16V4Z~D 1 2 C492 USB3TN2_RP_C 7 26 USB3TP1_C 0.1U_0402_16V4Z~D 1 2 C454
A2_OUTn A1_INp USB3TP1 <20>
USB3TP2_RP 0.1U_0402_16V4Z~D 1 2 C493 USB3TP2_RP_C 8 25
9 A2_OUTp VDD 24 USB3RN1_C 0.1U_0402_16V4Z~D 1 2 C487 +5V_ALW
USB3RN2_RP 10 VDD B1_OUTn 23 USB3RP1_C 0.1U_0402_16V4Z~D 1 2 C465 USB3RN1 <20>
B2_INn B1_OUTp USB3RP1 <20>
100K_0402_5%~D
USB3RP2_RP 11 22 USB3_TEST
B2_INp TEST
2
12 21 USB3TN2_C 0.1U_0402_16V4Z~D 1 2 C456 +3.3V_ALW +5V_USB_PWR2 +5V_USB_PWR1
PD# A2_INn USB3TN2 <20>
USB3_B_EQ0 13 20 USB3TP2_C 0.1U_0402_16V4Z~D 1 2 C457
B_EQ0/SDA_CTL A2_INp USB3TP2 <20>
R816
USB3_B_EQ1 14 19
USB3_B_DE0 15 B_EQ1/SCL_CTL GND 18 USB3RN2_C 0.1U_0402_16V4Z~D 1 2 C490 +5V_ALW U45
B_DE0 B2_OUTn USB3RN2 <20> PJP30
1
USB3_B_DE1 16 17 USB3RP2_C 0.1U_0402_16V4Z~D 1 2 C491 @ 1 10
1
B_DE1 B2_OUTp USB3RP2 <20> R2094 2 1 +5V_ALW_FUSE 2 GND FAULT1# 9
2 1 IN OUT1
10U_0805_10V4Z~D
33K_0402_5% 3 8
IN OUT2
0.1U_0402_16V4Z~D
PWRSHARE_EN# USB_SIDE_EN# 4 7
JUMP_43X79 <47,48> USB_SIDE_EN# EN1# ILIM
PS8720BTQFN32GTR-A0_TQFN32_3X6 1 1 PWRSHARE_EN# 5 6 USB_OC0# <20>
2
EN2# FAULT#2
11
HDD Redriver Select Component T-PAD
1
D
24.9K_0402_1%~D
C669
C670
1
PWRSHARE_EN 2 TPS2560DRCR-PG1.1_SON10_3X3~D
2 2
R747
G
X76(Main) X76(2nd)
Q55
S
3
2
PD# : chip power down, active LOW, 3.3V tolerant,
X7641231L03 X7641231L04 internally pulled up at ~ 150K ohm.
2
D99
PS8720B PS8720A
RB751VM-40TE-17_SOD323-2~D
SA00004UI00 SA00005PO00
1
<48> USB_PWR_SHR_VBUS_EN
U638 V V
R2196 V For EMI request

B L44 B
USB3TN2_RP 2 1 USB3_TX2_N_D- ESD request change main source to SC300002F0L.
2 1
R2197 V Follow conn list 0220A.
USB3TP2_RP 3 4 USB3_TX2_P_D+ +5V_USB_PWR2
3 4 For ESD request JUSB2 CONN@
DLW21SN900HQ2L_0805_4P~D 1
1 2 USBP1_D- 2 VBUS
@ R750 0_0402_5%~D D16 USBP1_D+ 3 D-
USB3_TX2_P_D+ 1 10 USB3_TX2_P_D+ 4 D+
1 2 USB3_RX2_N_D- 5 GND
@ R751 0_0402_5%~D USB3_TX2_N_D- 2 9 USB3_TX2_N_D- USB3_RX2_P_D+ 6 SSRX- 10
7 SSRX+ GND 11
USB3_RX2_P_D+ 4 7 USB3_RX2_P_D+ USB3_TX2_N_D- 8 GND GND 12
USB3_TX2_P_D+ 9 SSTX- GND 13
USB3_RX2_N_D- 5 6 USB3_RX2_N_D- SSTX+ GND
change SILEGO to be main source L43 LOTES_AUSB0041-P001A
USB3RP2_RP 3 4 USB3_RX2_P_D+ 3
@ R1626 1 2 0_0402_5%~D SB# 8

U2
1 PWRSHARE_EN
3 4
8
Link CIS OK
<48> USB_PWR_SHR_EN# CB CEN
<20>
<20>
USBP0-
USBP0+
7
6 TDM
TDP
DM
DP
2
3
USBP0_D-
USBP0_D+
USB3RN2_RP 2
2 1
1 USB3_RX2_N_D-
IP4292CZ10-TBR_XSON10_2.5X1~D 0305
5 4 SEL +5V_ALW DLW21SN900HQ2L_0805_4P~D
+5V_ALW VDD SELCDP 9 1 2 +5V_USB_PWR2
Thermal Pad
10K_0402_5%~D
@ R752 0_0402_5%~D
2
SLG55584AVTR_TDFN8_2X2
R1614
1 2
0.1U_0402_25V6K~D
150U_D2_6.3VY_R15M~D
10U_0603_6.3V6M~D
1 @ R753 0_0402_5%~D 1
D17 1
C715
C323
C794
USBP1_D- 2 +
EMI request.
1
1
2 L41 USBP1_D+ 3
2 1 USBP1_D+ 2 2
<20> USBP1+ 2 1
10K_0402_5%~D
@ R1613
2
D
2 SB# 3 4 USBP1_D-
<20> USBP1- 3 4
G
S DLW21SN900SQ2L_0805_4P~D
A CB=0 autodetection charger identification active A
3
@ Q338 1 2
1
SSM3K7002FU_SC70-3~D @ R754 0_0402_5%~D

charging downstream port with active USB2.0 data communication
CB=1 Reserve for samsung mobile issue. NEC_TOKIN shortage issue for the flood in Tailand.
mode with 1.5A support 1 2
@ R764 0_0402_5%~D
CB SELCDP Function DELL CONFIDENTIAL/PROPRIETARY

0 X DCP autodetect with mouse/keyboard wakeup
1 0 S0 charging with SDP only Title
1 1 S0 charging with CDP or SDP only (depending on external device)
USB3.0
5 4 3 2 1
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5 4 3 2 1
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0914: modify JUSH1 pin define for USH/B pin define change.
D D
+3.3V_RUN +3.3V_RUN_TPM
PJP77
1 2
CONN@
JUSH1
PAD-OPEN1x1m +3.3V_SB3V 22
+3.3V_RUN_TPM 21 GND
+3.3V_RUN_TPM +3.3V_SB3V 20 GND
ATMEL TPM for E4 <20> USBP7-
19 20
19
0.1U_0402_25V6K~D
4700P_0402_25V7K~D
18
<20> USBP7+ 18
2200P_0402_50V7K~D
2200P_0402_50V7K~D
2200P_0402_50V7K~D
0.1U_0402_25V6K~D
1 2 17
1@ R873 0_0402_5%~D 1@ 1 1@ 16 17
1 <49> USH_SMBCLK 16
1@ U39 15
Solve +3.3V_RUN Giltch in S5 +3.3V_RUN_TPM
1 1 1 1 <49> USH_SMBDAT 15
C48
C45
C553
14
<48> BCM5882_ALERT# 14
C550
C551
C552
10 13
when AC plugging in. 2 2 5 VCC_0 19
+3.3V_SUS
12 13
1 2 SB3V VCC_1 24 2 2 2 2 11 12
@ R2186 10K_0402_5%~D VCC_2 10 11
1 2 <50> BT_COEX_STATUS2 9 10
R2185 0_0402_5%~D <50> BT_PRI_STATUS 8 9
+3.3V_RUN 8
+5V_RUN 7
1 2 SP_TPM_LPC_EN_R 28 12 6 7
<48> SP_TPM_LPC_EN LPCPD# V_BAT <20> PLTRST_USH# 6
@ D103 RB751S40T1_SOD523-2~D 13 5
NBO_13 JETWAY_CLK14M <18> <48> USH_PWR_STATE# 5
LPC_LAD0 26 14 NC_P 1 2 4
<17,42,48,49> LPC_LAD0 LAD0 NBO_14 <21> CONTACTLESS_DET# 4
LPC_LAD1 23 4@ C554 1U_0402_6.3V6K~D 3
<17,42,48,49> LPC_LAD1 LAD1 3
LPC_LAD2 20 2
<17,42,48,49> LPC_LAD2 LAD2 2
LPC_LAD3 17 1
<17,42,48,49> LPC_LAD3 LAD3 <21> USH_DET# 1
6
GPIO6 ACES_51522-02001-001
CLK_PCI_TPM_TCM 21 9 TCM_BA0
<18> CLK_PCI_TPM_TCM LCLK TESTBI
LPC_LFRAME# 22 8
<17,42,48,49> LPC_LFRAME# LFRAME# TESTI
PCH_PLTRST#_EC 16 +3.3V_RUN_TPM
<20,42,43,47,48,49> PCH_PLTRST#_EC LRESET#
IRQ_SERIRQ 27
<17,48,49> IRQ_SERIRQ SERIRQ
CLKRUN# 15
C <19,48,49> CLKRUN# CLKRUN#
NC_7
7 PP 1
@ R656
2
4.7K_0402_5%~D
Link CIS OK C
CLK_PCI_TPM_TCM 1
2 ATEST_1 GND_4
4
11
0722
TCM_BA1 3 ATEST_2 GND_11 18
ATEST_3 GND_18
33_0402_5%~D
25
GND_25
1
@ RE5
AT97SC3204-X2A14-AB_TSSOP28
+3.3V_RUN +5V_RUN +3.3V_SUS
Change U39 TPM solution to new p/n: SA00004WQ10
2
27P_0402_50V8J~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
@ CE3
1 1 1
C52
C56
C53
2
2 2 2
Co-lay U37 and U39

LPC layout: Place TCM first and then end LPC with TPM.
China TCM: NationZ & Jetway co-lay

+3.3V_RUN_TPM
B
LOW:Power Down Mode 4@ U37 B
High:Working Mode
10
VDD_0 19
VDD_1 24
VDD_2
SP_TPM_LPC_EN_R 28
LPC_LAD0 26 LPCPD# 11
LPC_LAD1 23 LAD0 GND_11 18
+3.3V_RUN_TPM LPC_LAD2 20 LAD1 GND_18 25
LPC_LAD3 17 LAD2 GND_25 4
LAD3 GND_4 +3.3V_SB3V
10K_0402_5%~D
1
10K_0402_5%~D
CLK_PCI_TPM_TCM 21 5 JETWAY_CLK14M
LCLK NC_5
1
LPC_LFRAME# 22 12
LFRAME# NC_12
1
@ R657
@ R658
33_0402_5%~D
PCH_PLTRST#_EC 16 13 JETWAY_CLK14M
LRESET# NC_13
@ RE6
IRQ_SERIRQ 27
CLKRUN# 15 SERIRQ 1
2
PP 7 CLKRUN# NC_1 2
2
TCM_BA1 3 PP NC_2 6
BA_1 NC_6 2
27P_0402_50V8J~D
TCM_BA0 TCM_BA0 9 8
BA_0 NC_8 14 NC_P
NC_P 1
TCM_BA1
@ CE4
2
10K_0402_5%~D
10K_0402_5%~D
1
1
R659
R660
SSX44-B-D-T1_TSSOP28~D
2
A A
TPM/TCM
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5 4 3 2 1
5 4 3 2 1
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@ R700 2 1 0_0402_5%~D
Mini WLAN/WIMAX/WiGig H=4 WLAN_RADIO_DIS#_R 2 1

WLAN_RADIO_DIS# <48>
D31
+3.3V_WLAN +3.3V_WLAN RB751S40T1_SOD523-2~D
+1.5V_RUN
JMINI4 CONN@ @ R2204 2 1 0_0402_5%~D

<16,43,47,49> PCIE_WAKE# 1 2
@ R707 1 2 0_0402_5%~D COEX2_WLAN_ACTIVE_R 3 1 2 4
<50> COEX2_WLAN_ACTIVE @ R702 1 2 0_0402_5%~D COEX1_BT_ACTIVE_R 5 3 4 6 WiGi_RADIO_DIS#_R 2 1
D WiGi_RADIO_DIS# <48> D
<50> COEX1_BT_ACTIVE 7 5 6 8
<18> MINI2CLK_REQ# 9 7 8 10 @ D104
11 9 10 12 RB751S40T1_SOD523-2~D
<18> CLK_PCIE_MINI2# 11 12
13 14 MSDATA
<18> CLK_PCIE_MINI2 13 14
15 16
15 16 HOST_DEBUG_TX <49>
17 18 @ R2205 2 1 0_0402_5%~D
<49> HOST_DEBUG_RX 19 17 18 20 WLAN_RADIO_DIS#_R
<49> MSCLK 21 19 20 22 PCH_PLTRST#_EC_R1 2 PCH_PLTRST#_EC
23 21 22 24 @ R703 0_0402_5%~D BT_RADIO_DIS#_R 2 1
<18> PCIE_PRX_WLANTX_N2 23 24 BT_RADIO_DIS# <48,50>
25 26
<18> PCIE_PRX_WLANTX_P2 27 25 26 28 @ D105
C596 0.1U_0402_10V7K~D 29 27 28 30
Add WiGig card function RB751S40T1_SOD523-2~D
1 2 PCIE_PTX_WLANRX_N2_C 31 29 30 32 WiGi_RADIO_DIS#_R
<18> PCIE_PTX_WLANRX_N2 31 32
1 2 PCIE_PTX_WLANRX_P2_C 33 34
<18> PCIE_PTX_WLANRX_P2
C598 0.1U_0402_10V7K~D 35 33 34 36 USBP8- Reserve for WiGig card function
35 36 USBP8- <20>
37 38 USBP8+
37 38 USBP8+ <20>
39 40
39 40
41
41 42
42 WIMAX_LED# EMI issue
43 44 WLAN_LED#
45 43 44 46 WiGi_BT_LED# WiGi_BT LED function.
<18> PCH_CL_CLK1 45 46 WiGi_BT_LED# <51>
47 48 1 2 MSDATA
<18> PCH_CL_DATA1 47 48 MSDATA <49>
@ R709 1 2 0_0402_5%~D PCH_CL_RST1#_R 49 50 @ R706 0_0402_5%~D
<18> PCH_CL_RST1# 49 50
BT_RADIO_DIS#_R 51 52
51 52
Add WiGig card function 53 54
GND1 GND2
LCN_DAN08-52526-0100
follow connecter list 1005: AAA-PCI-092-P01_A footprint

same as DAN08-52526-0100. next phase need change.
Link CIS OK_0722
C C
+3.3V_WLAN +3.3V_WLAN
100K_0402_5%~D
100K_0402_5%~D
HOST_DEBUG_TX C595 1 2 4700P_0402_25V7K~D
2
2
+1.5V_RUN +3.3V_WLAN R718
R705
COEX2_WLAN_ACTIVE @ C600 1 2 33P_0402_50V8J~D
5
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
0.1U_0402_25V6K~D
1 1 1 1 1 2 2 1 WIMAX_LED# 4 3
WIRELESS_LED# <43,48,51>
@ C603
Q124B
C601
C602
C604
C605
C606
C607
C608
2 2 2 2 2 1 1 2
WLAN_LED# 1 6
Q124A
B B
1/2 Minicard Pink Pather

+3.3V_PCIE_FLASH +3.3V_PCIE_FLASH
JMINI3 CONN@
PCIE_WAKE# 1 2
<16,43,47,49> PCIE_WAKE# 1 2 3 1 2 4
<50> COEX2_WLAN_ACTIVE 3 4
@ R724 0_0402_5%~D 5 6
5 6 +1.5V_RUN
MINI3CLK_REQ# 7 8 LPC_LFRAME#
<18> MINI3CLK_REQ# 7 8 LPC_LFRAME# <17,41,48,49>
9 10 LPC_LAD3
9 10 LPC_LAD3 <17,41,48,49>
CLK_PCIE_MINI3# 11 12 LPC_LAD2
<18> CLK_PCIE_MINI3# 11 12 LPC_LAD2 <17,41,48,49>
CLK_PCIE_MINI3 13 14 LPC_LAD1
<18> CLK_PCIE_MINI3 13 14 LPC_LAD1 <17,41,48,49>
15 16 LPC_LAD0
15 16 LPC_LAD0 <17,41,48,49>
PCH_PLTRST#_EC 17 18
PCLK_80H 19 17 18 20 @ R730
<18> PCLK_80H 19 20
21 22 1 2
21 22 PCH_PLTRST#_EC <20,41,43,47,48,49>
PCIE_PRX_WPANTX_N5 23 24 0_0402_5%~D
<18> PCIE_PRX_WPANTX_N5 PCIE_PRX_WPANTX_P5 25 23 24 26
<18> PCIE_PRX_WPANTX_P5 27 25 26 28
C636 0.1U_0402_10V7K~D 29 27 28 30
1 2 PCIE_PTX_WPANRX_N5_C 31 29 30 32
<18> PCIE_PTX_WPANRX_N5 31 32
1 2 PCIE_PTX_WPANRX_P5_C 33 34
<18> PCIE_PTX_WPANRX_P5 33 34
C626 0.1U_0402_10V7K~D 35 36
37 35 36 38
39 37 38 40
41 39 40 42
43 41 42 44
45 43 44 46
47 45 46 48
49 47 48 50
51 49 50 52
51 52
+1.5V_RUN +3.3V_PCIE_FLASH 53 54
GND1 GND2
LCN_DAN08-52526-0100
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
0.1U_0402_25V6K~D
Link CIS OK
@ C639
1 1 1 1 1 2 2 1
A A
C625
C635
C634
C624
C637
C638
C633
2 2 2 2 2 1 1 2 0722
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Mini Card-1/2
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Size Document Number Rev
LA-7931P 1.0

5 4 3 2 1
5 4 3 2 1

Mini WWAN/GPS/LTE/mSATA
0.01U_0402_16V7K~D
0.1U_0402_16V4Z~D
1 1 +3.3V_PCIE_NVM +3.3V_PCIE_NVM
SATA Repeater JMINI2 CONN@
+1.5V_RUN
C1311
C1312
PCIE_WAKE# 1 2
<16,42,47,49> PCIE_WAKE# 1 2
3 4
U637 X76@ 2 2 5 3 4 6
@ C1313 1 2 1U_0402_6.3V6K~D M_SATA_EN 7 6 MINI1CLK_REQ# 7 5 6 8
EN VDD <18> MINI1CLK_REQ# 7 8 +SIM_PWR
16 9 10 UIM_DATA
0.01U_0402_16V7K~D 1 2 C445 SATA_NVRAM_PTX_DRX_P2 1 VDD CLK_PCIE_MINI1# 11 9 10 12 UIM_CLK
D <17> SATA_NVRAM_PTX_DRX_P2_C A_INp <18> CLK_PCIE_MINI1# 11 12 D
0.01U_0402_16V7K~D 1 2 C446 SATA_NVRAM_PTX_DRX_N2 2 10 M_MAXIM_PWR CLK_PCIE_MINI1 13 14 UIM_RESET
<17> SATA_NVRAM_PTX_DRX_N2_C A_INn NC <18> CLK_PCIE_MINI1 13 14
20 M_REXT 15 16 UIM_VPP
0.01U_0402_16V7K~D 1 2 C447 SATA_NVRAM_PRX_DTX_P2 5 REXT 17 15 16 18
<17> SATA_NVRAM_PRX_DTX_P2_C 0.01U_0402_16V7K~D 1 2 C448 SATA_NVRAM_PRX_DTX_N2 4 B_OUTp 9 M_A_PRE0 19 17 18 20
<17> SATA_NVRAM_PRX_DTX_N2_C B_OUTn A_PRE0 19 20 WWAN_RADIO_DIS# <48>
8 M_B_PRE0 21 22 1 2
B_PRE0 21 22 PCH_PLTRST#_EC <20,41,42,47,48,49>
M_B_PRE1 17 PCIE_SATA_PRX_WANTX_N 23 24 @ R713 0_0402_5%~D
M_A_PRE1 19 B_PRE1 15 SATA_NVR_PTX_DRX_P2 PCIE_SATA_PRX_WANTX_P 25 23 24 26
A_PRE1 A_OUTp 14 SATA_NVR_PTX_DRX_N2 27 25 26 28
M_TEST 18 A_OUTn 29 27 28 30 WWAN_SMBCLK
HDD Redriver Select Component 3 TEST
GND B_INp
11 SATA_NVR_PRX_DTX_P2 PCIE_SATA_PTX_WANRX_N 31 29
31
30
32
32 WWAN_SMBDAT
13 12 SATA_NVR_PRX_DTX_N2 PCIE_SATA_PTX_WANRX_p 33 34
21 GND B_INn 35 33 34 36 USBP5-
X76(Main) X76(2nd) EPAD 37 35 36 38 USBP5+
USBP5- <20>
37 38 USBP5+ <20>
PS8520BTQFN20GTR2_TQFN20_4X4 39 40
X7641231L01 X7641231L02 41 39 40 42 LED_WWAN_OUT#
For Gen2, Gen3 EA setting 43 41 42 44
PARADE(Main) MAXIM(2nd) 45 43 44 46
+3.3V_RUN 47 45 46 48 +3.3V_PCIE_NVM
SA00004WF00 SA00002EY1L @ R2105 49 47 48 50
M_B_PRE1 2 1 X761@ 1 2 51 49 50 52
<48> HW_GPS_DISABLE2# 51 52
4.7K_0402_5%~D R2135
U637 V V M_A_PRE1 2 1 X761@ 0_0402_5%~D 53 54
pull high on EC side. GND1 GND2
100K_0402_5%~D
4.7K_0402_5%~D R2136
2
M_TEST 2 1 @ LCN_DAN08-52526-0100
R719
4.7K_0402_5%~D R2137
R2135 V M_A_PRE0 2 1 X761@
4.7K_0402_5%~D R2140
Link CIS OK
2
G
M_B_PRE0 2 1 X761@
1
4.7K_0402_5%~D R2138
R2136 V
M_REXT 2 1 @ 0722 LED_WWAN_OUT# 3 1
WIRELESS_LED# <42,48,51>
D
4.99K_0402_1%~D R2139
C @ U40 Q77 C
R2137 +3.3V_PCIE_NVM SSM3K7002FU_SC70-3~D
UIM_RESET 1 6 UIM_VPP
+3.3V_RUN
R2140 V
2.2K_0402_5%~D
2.2K_0402_5%~D
M_MAXIM_PWR 1 2 X762@ 2 5 +SIM_PWR
1
@ R1159
0_0402_5%~D R2189
1
@ R1160
M_REXT 1 2 X762@
R2138 V 0_0402_5%~D R2190 UIM_DATA 3 4 UIM_CLK
M_SATA_EN 1 2 X762@
33P_0402_50V8J~D
33P_0402_50V8J~D
33P_0402_50V8J~D
33P_0402_50V8J~D
0_0402_5%~D R2191
2
R2139 1 1 1 1
2
@ C628
@ C629
@ C630
@ C631
SRV05-4.TCT_SOT23-6~D
M_B_PRE1 1 2 X762@ WWAN_SMBCLK 1 2
DDR_XDP_WAN_SMBCLK <12,13,14,15,17,18,35>
0_0402_5%~D R2192 @ R1157 0_0402_5%~D
M_TEST 1 2 X762@ 2 2 2 2 WWAN_SMBDAT 1 2
R2189 V 0_0402_5%~D R2193 @ R1158 0_0402_5%~D
R2190 V 2nd source for SATA redriver

+1.5V_RUN
R2191 V
(Add X762@ for 2nd source option.)
+SIM_PWR
SIM Card Push-Push
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
+1.5V_RUN
+3.3V_PCIE_NVM JSIM1 CONN@
1 5
R2192 V 1 1 VCC GND
C435
C436
UIM_RESET 2 6 UIM_VPP
U12 UIM_CLK 3 RST VPP 7 UIM_DATA
CLK I/O
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
@ 330U_V_6.3VM~D
33P_0402_50V8J~D
22U_0805_6.3VAM~D
33P_0402_50V8J~D
9 1 4 8
33P_0402_50V8J~D
B 2 2 11 VDD 4 PCIE_SATA_PRX_WANTX_N NC NC 9 B
R2193 V VDD A0+ 1 1 1 1 1 1 1 GND
C615
1U_0402_6.3V6K~D
13 5 PCIE_SATA_PRX_WANTX_P + 10
VDD A0- GND
C620
C609
C623
C621
C618
C622
C617
19 1
26 VDD 6 PCIE_SATA_PTX_WANRX_N SUYIN_254070FB008S205ZL
VDD A1+ 2 2 2 2 2 2 2 2
C616
28 7 PCIE_SATA_PTX_WANRX_P
VDD A1-
SATA_NVR_PRX_DTX_P2 C1314 2 1 0.01U_0402_16V7K~D SATA_NVR_PRX_DTX_P2_C24 3 PCIE_SATA# 2
SATA_NVR_PRX_DTX_N2 C1315 2 1 0.01U_0402_16V7K~D SATA_NVR_PRX_DTX_N2_C23 B0+ SEL
PIN mSATA WWAN SATA_NVR_PTX_DRX_N2
SATA_NVR_PTX_DRX_P2
C1316 2
C1317 2
1
1
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
SATA_NVR_PTX_DRX_N2_C22
SATA_NVR_PTX_DRX_P2_C21
B0-
B1+
B1- GND
1
Link CIS OK
PCIE_PRX_WANTX_N1 18 10
23 TX+ PERn0 <18>
<18>
<18>
PCIE_PRX_WANTX_N1
PCIE_PRX_WANTX_P1
PCIE_PTX_WANRX_N1
0.1U_0402_10V7K~D 2 1 C640
PCIE_PRX_WANTX_P1 17
PCIE_PTX_WANRX_N1_C 16
C0+
C0-
C1+
GND
GND
GND
12
14
0722
0.1U_0402_10V7K~D 2 1 C641 PCIE_PTX_WANRX_P1_C 15 20
25 TX- PERp0 <18> PCIE_PTX_WANRX_P1 C1- GND 25 For RF layout request
2 GND 27
8 NC GND 29
31 NC TPAD
RX- PETn0 +1.5V_RUN
PI2DBS212ZHEX_TQFN28_5P5X3P5~D
1
33
100K_0402_5%~D
RX+ PETp0
Primary Power Aux Power
R785
+3.3V_PCIE_NVM PWR Voltage

Rail Tolerance
100K_0402_5%~D
Peak Normal Normal

2
1
Function SEL
PCIE_SATA#
R740
+3.3V +-9% 1000 750

3
Port A to Port B L
250 (Wake enable)
2
H +3.3Vaux +-9% 330 250 5 (Not wake enable)

Q322B
Port A to Port C MCARD_PCIE_SATA 5

A A
6
+1.5V +-5% 500 375 NA

4
Q322A
MCARD_PCIE_SATA# 2
<48> MCARD_PCIE_SATA#
1

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Mini Card-2/2

5 4 3 2 1
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5 4 3 2 1
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D D
Power Control for Mini card1
+PWR_SRC_S
+3.3V_ALW
Q38 +3.3V_WLAN
100K_0402_5%~D
SI3456DDV-T1-GE3_TSOP6~D
D
R720
6
S
+3.3V_ALW 5 4
2
1
1
100K_0402_5%~D
G
2
1
R716
3
R715
47K_0402_1%~D
+AUX_EN
for power saving in DC mode S3
2
3
4700P_0402_25V7K~D
2
1M_0402_5%~D
1
Q310B
C632
AUX_EN_WOWL# 5
R1620
4 2
6
2
Q310A
2
C <48> AUX_EN_WOWL C
+PWR_SRC_S +3.3V_ALW
1
1
100K_0402_5%~D
Q46 +3.3V_PCIE_NVM
R717
470K_0402_5%~D
1
D
6
S
R737
5 4
2
+3.3V_ALW 2
1
G
2
20K_0402_5%~D
3
1
1
100K_0402_5%~D
R734
R738
+NVRAM_PWREN
2
3
220P_0402_50V8J~D
4.7M_0402_5%~D
1
1
Q313B
R1629
C652
NVRAM_PWR_EN# 5
2
4
Solve 300mW
2
6
+PWR_SRC_S +3.3V_ALW
PWR consumption
issue.
Q313A
Q44 +3.3V_PCIE_FLASH 2
<48> NVRAM_PWR_EN
470K_0402_5%~D
1
1
100K_0402_5%~D
+3.3V_ALW 6
S
@
R731
5 4
R739
2
100K_0402_5%~D
1
1
B B
G
2
R735
20K_0402_5%~D
3
2
1
R732
+MISC_PWREN
2
2
3
220P_0402_50V8J~D
4.7M_0402_5%~D
1
1
Q312B
R1628
C651
MCARD_MISC_PWREN# 5
2
Solve 300mW
2
6
PWR consumption
issue.
Q312A
2
<48> MCARD_MISC_PWREN
100K_0402_5%~D
1
1
R733
2
A A
Mini Card PWR
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5 4 3 2 1
5 4 3 2 1
DOCK DPB(PORT2) DDC
1
+5V_RUN
R2145
2.2K_0402_5%~D
2
1
+3.3V_ALW2 1 2
R2149 @ R2147 0_0402_5%~D
6
100K_0402_5%~D
D D
Q333A
2
1
100K_0402_5%~D
2
R2150
1
Q334B
2
5
4
6
DPC_DOCK_SW_AUX
+3.3V_RUN DPC_DOCK_SW_AUX <33,46>
Q334A
<33,46> DPC_CA_DET DPC_CA_DET 2
1
R2146
1
0.01U_0402_16V7K~D 2.2K_0402_5%~D
1 C1331
2
2 1 2
@ R2148 0_0402_5%~D
3
Q333B
5
4
C C
DPC_DOCK_SW_AUX#
DPC_DOCK_SW_AUX# <33,46>
+3.3V_RUN
+3.3V_RUN
DOCK DPA(PORT1) DDC
1
+5V_RUN 1 R2161
R2151 2.2K_0402_5%~D
2.2K_0402_5%~D
2
1 2
2
1
+3.3V_ALW2
1 2 @ R2162 0_0402_5%~D
6
R2153 @ R2156 0_0402_5%~D

6
100K_0402_5%~D
Q337A
Q335A
DPD_DOCK_AUX_Q 2
2
1
100K_0402_5%~D
DPD_DOCK_AUX_Q 2
R2152
1
3
1
Q336B
2
5
4
MXM_DPC_AUX
MXM_DPC_AUX <16,34>
6
DPD_DOCK_AUX
+3.3V_RUN DPD_DOCK_AUX <34,46>
B B
Q336A
DPD_CA_DET 2 +3.3V_RUN
<34,46> DPD_CA_DET
1
R2157
1
1
0.01U_0402_16V7K~D
1 2.2K_0402_5%~D
R2164
C1332
2.2K_0402_5%~D
2
2 1 2
2
@ R2155 0_0402_5%~D
3
1 2
@ R2163 0_0402_5%~D
3
Q335B
5
Q337B
5
4
4
DPD_DOCK_AUX#
DPD_DOCK_AUX# <34,46>
MXM_DPC_AUX#
MXM_DPC_AUX# <16,34>
A A

Title
DOCK DP DDC SW
5 4
WWW.AliSaler.Com 3 2
Size
Date:
Document Number
LA-7931P
1
Sheet 45 of 70
Rev
1.0
5 4 3 2 1
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<34> DPD_GPU_LANE_P0
<34> DPD_GPU_LANE_N0
<34> DPD_GPU_LANE_P1
DPD_GPU_LANE_P0
DPD_GPU_LANE_N0
DPD_GPU_LANE_P1
C1281 2
C1282 2
C1277 2
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
DPD_DOCK_LANE_P0
DPD_DOCK_LANE_N0
DPD_DOCK_LANE_P1
DPC_DOCK_LANE_P0_C
DPC_DOCK_LANE_N0_C
DPC_DOCK_LANE_P1_C
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
1
1
2 C1275
2 C1276
2 C1283
MXM_DPB_P0
MXM_DPB_N0
MXM_DPB_P1
MXM_DPB_P0 <16>
MXM_DPB_N0 <16>
MXM_DPB_P1 <16>
DPD_GPU_LANE_N1 C1284 2 1 0.1U_0402_10V7K~D DPD_DOCK_LANE_N1 DPC_DOCK_LANE_N1_C 0.1U_0402_10V7K~D 1 2 C1285 MXM_DPB_N1
<34> DPD_GPU_LANE_N1 MXM_DPB_N1 <16>
DPD_GPU_LANE_P2 C1286 2 1 0.1U_0402_10V7K~D DPD_DOCK_LANE_P2 DPC_DOCK_LANE_P2_C 0.1U_0402_10V7K~D 1 2 C1287 MXM_DPB_P2
<34> DPD_GPU_LANE_P2 MXM_DPB_P2 <16>
DPD_GPU_LANE_P3 C1279 2 1 0.1U_0402_10V7K~D DPD_DOCK_LANE_P3 DPC_DOCK_LANE_P3_C 0.1U_0402_10V7K~D 1 2 C1289 MXM_DPB_P3
<34> DPD_GPU_LANE_P3 MXM_DPB_P3 <16>
EMI request add 33ohm for DOCK DVI signals.
JDOCK1 CONN@ reduce layout via.
D D
DOCK DPA(PORT1) DOCK_DET_1 1 2
3 1 2 4 DOCK_AC_OFF <48,63>
<37> DOCK_LOM_SPD10LED_GRN# 3 4 DOCK_LOM_SPD100LED_ORG# <37> DOCK DPB(PORT2)
DPD_CA_DET 5 6
<34,45> DPD_CA_DET 7 5 6 8 DPC_CA_DET <33,45>
DPD_DOCK_LANE_P0 R2160 1 2 33_0402_5%~D DPD_DOCK_LANE_P0_R 9 7 8 10 DPC_DOCK_LANE_P0_R R2172 1 2 33_0402_5%~D DPC_DOCK_LANE_P0_C
DPD_DOCK_LANE_N0 R2165 1 2 33_0402_5%~D DPD_DOCK_LANE_N0_R 11 9 10 12 DPC_DOCK_LANE_N0_R R2173 1 2 33_0402_5%~D DPC_DOCK_LANE_N0_C
13 11 12 14
19 17 18 20
25 23 24 26
31 29 30 32
DPD_DOCK_AUX 33 31 32 34 DPC_DOCK_SW_AUX
<34,45> DPD_DOCK_AUX 33 34 DPC_DOCK_SW_AUX <33,45>
DPD_DOCK_AUX# 35 36 DPC_DOCK_SW_AUX#
<34,45> DPD_DOCK_AUX# 35 36 DPC_DOCK_SW_AUX# <33,45>
37 38
DPD_GPU_HPD 39 37 38 40 DPC_GPU_HPD
<34> DPD_GPU_HPD 39 40 DPC_GPU_HPD <16>
+NBDOCK_DC_IN_SS 41 42
41 42 ACAV_DOCK_SRC# <63>
0.033U_0402_16V7K~D
1 43 44
43 44
0.033U_0402_16V7K~D
BLUE_DOCK 45 46 1
<32> BLUE_DOCK 45 46 DAT_DDC2_DOCK <32>
C695
47 48
47 48 CLK_DDC2_DOCK <32>
C696
49 50 Close to DOCK
2 51 49 50 52
RED_DOCK 53 51 52 54 SATA_PRX_DKTX_P5 C697 2 1 0.01U_0402_16V7K~D 2 Its for Enhance ESD on dock issue.
<32> RED_DOCK 53 54 SATA_PRX_DKTX_P5_C <17>
Close to DOCK 55 56 SATA_PRX_DKTX_N5 C698 2 1 0.01U_0402_16V7K~D
55 56 SATA_PRX_DKTX_N5_C <17>
57 58
Its for Enhance ESD on dock issue. GREEN_DOCK 59 57 58 60 SATA_PTX_DKRX_P5 C699 1 2 0.01U_0402_16V7K~D
<32> GREEN_DOCK 59 60 SATA_PTX_DKRX_P5_C <17>
61 62 SATA_PTX_DKRX_N5 C700 1 2 0.01U_0402_16V7K~D
63 61 62 64 SATA_PTX_DKRX_N5_C <17>
65 63 64 66
<32> HSYNC_DOCK 65 66 USBP4+ <20>
67 68 EMI issue
C <32> VSYNC_DOCK 67 68 USBP4- <20> C
69 70 Add pull-down R for DPC_GPU_HPD.
DPD_GPU_HPD 71 69 70 72
<49> CLK_MSE 71 72 USBP3+ <20>
73 74
<49> DAT_MSE 73 74 USBP3- <20>
75 76 DPC_GPU_HPD
75 76
100K_0402_5%~D
77 78
<47> DAI_BCLK# 77 78 CLK_KBD <49>
1
79 80
<47> DAI_LRCK# 79 80 DAT_KBD <49>
R757
100K_0402_5%~D
81 82
81 82
1
83 84
<47> DAI_DI 83 84 USB3RN4 <20>
R773
85 86
<47> DAI_DO# 85 86 USB3RP4 <20>
87 88
2
89 87 88 90
<47> DAI_12MHZ# 89 90 USB3TN4 <20>
91 92
USB3TP4 <20>
2
93 91 92 94
95 93 94 96
97 95 96 98
<48> D_LAD0 97 98 BREATH_LED# <48,51>
99 100
<48> D_LAD1 99 100 DOCK_LOM_ACTLED_YEL# <37>
101 102
103 101 102 104
<48> D_LAD2 103 104 DOCK_LOM_TRD0+ <37>
105 106
<48> D_LAD3 105 106 DOCK_LOM_TRD0- <37>
107 108
109 107 108 110 +3.3V_ALW
<48> D_LFRAME# 109 110 DOCK_LOM_TRD1+ <37> +LOM_VCT
111 112
<48> D_CLKRUN# 111 112 DOCK_LOM_TRD1- <37>
1U_0402_6.3V6K~D
113 114
115 113 114 116 DOCK_DET# 2 1
<48> D_SERIRQ 115 116 1
@ C701
117 118 +LOM_VCT 10K_0402_5%~D R755
<48> D_DLDRQ1# 117 118
119 120
121 119 120 122
<20> CLK_PCI_DOCK
123 121 122 124
DOCK_LOM_TRD2+ <37> 2 Solve dock detection issue.
123 124 DOCK_LOM_TRD2- <37>
125 126
127 125 126 128
<49> DOCK_SMB_CLK 127 128 DOCK_LOM_TRD3+ <37>
129 130
<49> DOCK_SMB_DAT 129 130 DOCK_LOM_TRD3- <37>
131 132
133 131 132 134
<48,53> DOCK_SMB_ALERT# 133 134 DOCK_DCIN_IS+ <62>
135 136
<53> DOCK_PSID 135 136 DOCK_DCIN_IS- <62>
B 137 138 B
139 137 138 140 D32
<49> DOCK_PWR_BTN# 139 140 DOCK_POR_RST# <49>
141 142 RB751S40T1_SOD523-2~D
143 141 142 144 DOCK_DET_R# 1 2
<48,53,63> SLICE_BAT_PRES# 143 144 DOCK_DET# <48>
145 149 +DOCK_PWR_BAR
GND1 PWR2
PESD24VS2UT_SOT23-3~D
146 150
PWR1 PWR2
0.1U_0603_50V7K~D
0.1U_0603_50V7K~D
2011/09/01 change. 147 151 @
PWR1 PWR2
4.7U_0805_25V6K~D
148 152
PWR1 GND2 D33
@
1 1 1
C702
C703
153 159
Shield_G Shield_G
CE6
154 160
155 Shield_G Shield_G 161 1
156 Shield_G Shield_G 162 2 2 2
157 Shield_G Shield_G 163
158 Shield_G Shield_G 164
Shield_G Shield_G
JAE_WD2F144WB5R400
2011/09/01 change.
Link CIS OK ESD request reserve it.
0904 DAI_12MHZ# DAI_BCLK# CLK_PCI_DOCK
1
@ RE11 @ RE12 R756
10_0402_1%~D 10_0402_1%~D 33_0402_5%~D
2
1 1 1
@CE8 @CE9 C704
4.7P_0402_50V8C~D 4.7P_0402_50V8C~D 12P_0402_50V8J~D
A 2 2 2 A
Docking
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5 4 3 2 1
5 4 3 2 1
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D D
JIO1 CONN@
1 2 +3.3V_ALW
3 1 2 4
<17> PCH_AZ_CODEC_BITCLK 3 4
5 6
<17> PCH_AZ_CODEC_SDIN0
7
9
5
7
6
8
8
10
WireLess ON/OFF CONN
<17> PCH_AZ_CODEC_SDOUT 9 10 PLTRST_MMI# <20>
11 12
13 11 12 14
<17> PCH_AZ_CODEC_SYNC 13 14 PCIE_PRX_MMITX_P8 <18>
15 16 JWL1 CONN@
<17> PCH_AZ_CODEC_RST# 15 16 PCIE_PRX_MMITX_N8 <18>
17 18 1
<46> DAI_12MHZ# 19 17 18 20 2 1
19 20 PCIE_PTX_MMIRX_P8 <18> 2
21 22 3
<46> DAI_DI 21 22 PCIE_PTX_MMIRX_N8 <18> <48> WIRELESS_ON#/OFF 3
23 24
<46> DAI_DO# 23 24
25 26 4
<46> DAI_BCLK# 25 26 CLK_PCIE_CARD# <18> GND
27 28 5
<46> DAI_LRCK# 27 28 CLK_PCIE_CARD <18> GND
29 30
<48> EN_I2S_NB_CODEC# 29 30
31 32 ACES_50228-0037N-001
<28> DMIC_CLK 31 32 CARDCLK_REQ# <18>
33 34
<28> DMIC0 33 34 SIO_SLP_S3# <11,19,35,48,52,56>
35 36
<48> DOCK_HP_DET
<48> DOCK_MIC_DET
37
39
35
37
36
38
38
40
RUN_ON <35,48,52,56>
PCH_PLTRST#_EC <20,41,42,43,48,49> Link CIS OK_0722
<48> AUD_HP_NB_SENSE 39 40
41 42
41 42 USBP10- <20>
43 44
<48> AUD_NB_MUTE# 43 44 USBP10+ <20>
45 46
<49> BEEP 45 46
47 48 CARD_SMBCLK <49>
<17> SPKR 47 48
49 50
49 50 CARD_SMBDAT <49>
51 52
<20> USB_OC1# 51 52 PCIE_WAKE# <16,42,43,49>
53 54
<17,20> USB_OC3# 53 54 EXPCLK_REQ# <18>
55 56
57 55 56 58
<20> USBP2- 57 58 CLK_PCIE_EXP# <18>
59 60
<20> USBP2+ 59 60 CLK_PCIE_EXP <18>
61 62
C
63 61 62 64 C
<20> USBP6- 63 64 PCIE_PRX_EXPTX_N3 <18>
65 66 PCIE_PRX_EXPTX_P3 <18>
<20> USBP6+ 65 66
67 68
69 67 68 70
<40,48> USB_SIDE_EN# 69 70 PCIE_PTX_EXPRX_N3 <18>
71 72
<48,51> LID_CL# 71 72 PCIE_PTX_EXPRX_P3 <18>
73 74
<49> VOL_UP 73 74
75 76 +1.5V_RUN
<49> VOL_DOWN 75 76
77 78
<49> VOL_MUTE 77 78
79 80
81 79 80 82
+5V_ALW 81 82 +3.3V_SUS
83 84
85 83 84 86
87 85 86 88
87 88 SATA_SIDE_LED <51>
89 90
89 90 NUM_LED <51>
91 92
91 92 BT_LED <51>
93 94
93 94 WLAN_LED <51>
95 96
95 96 SATA_LED <51>
97 98
99
101
97
99
98
100
100
102 Remove net VOL_MUTE_LED.
BREATH_LED#_Q <51>
Power Bottom CONN
101 102 BAT2_LED# <48>
103 104
103 104 BAT1_LED# <48>
105 106
105 106 MASK_BASE_LEDS# <51>
107 108 JPB1
107 108 DAT_TP_SIO <49>
109 110 POWER_SW#_MB 1
109 110 CLK_TP_SIO <49> 1
111 112 +5V_ALW 2
113 111 112 114 3 2
113 114 PS2_DAT_TS <50> 3
2
PESD24VS2UT_SOT23-3~D
115 116 @ 4
115 116 PS2_CLK_TS <50> <51> BREATH_WHITE_LED 4
117 118 D97 5
119 117 118 120 6 5
119 120 +3.3V_RUN 6
121 122
123 121 122 124 7
125 123 124 126 8 GND
+5V_RUN
1
127 125 126 128 GND
129 127 128 130 ACES_50228-0067N-001
131 129 130 132 CONN@
B B
133 131 132 134
135
137
133
135
134
136
136
138
Link CIS OK
137 138
139
139 140
140
0722
141 142
GND GND
ESD request reserve it.
FOX_QTS01401-A021-9H
Link CIS OK
0722 Power Switch for debug
1 2
<49> POWER_SW#_MB 1 2
100P_0402_50V8J~D
1
+5V_RUN +5V_ALW +3.3V_RUN +3.3V_ALW +1.5V_RUN +3.3V_SUS
@ C759
@ PWRSW1
2 @SHORT PADS~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 1 1 1 1 1
Place on Bottom
C763
C721
C722
C723
C724
C725
A 2 2 2 2 2 2 A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT I/O board
WWW.AliSaler.Com
5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com
+3.3V_ALW_U46
1 2 HW_GPS_DISABLE2#
+3.3V_RUN
R798 100K_0402_5%~D +3.3V_ALW_U46 D_CLKRUN# 1 2

1 2 PROCHOT_GATE PJP29 +3.3V_ALW 100K_0402_5%~D R777
R761 100K_0402_5%~D PAD-OPEN1x1m D_SERIRQ 1 2
1 2 CPU_DETECT# 2 1 100K_0402_5%~D R780
R765 100K_0402_5%~D D_DLDRQ1# 1 2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1 2 SLICE_BAT_PRES# 100K_0402_5%~D R782
R760 100K_0402_5%~D
C710
C709
1 2 WWAN_RADIO_DIS# 1 1 1 1 1 1
C708
C717
C718
C719
R774 100K_0402_5%~D
1 2 USB_PWR_SHR_EN# RUN_ON 1 2
R776 100K_0402_5%~D 100K_0402_5%~D R786
D 1 2 USB_SIDE_EN# 2 2 2 2 2 2 CPU_VTT_ON 1 2 D
R768 10K_0402_5%~D 100K_0402_5%~D R789
1 2 ESATA_USB_PWR_EN# 0.75V_DDR_VTT_ON 1 2
R769 100K_0402_5%~D 100K_0402_5%~D R790
A17
B30
A43
A54
1 2 USB_PWR_SHR_VBUS_EN SLICE_BAT_ON 1 2
B5
R778 100K_0402_5%~D U46 100K_0402_5%~D R791
1 2 DOCK_SMB_ALERT# SUS_ON 1 2
VCC1
VCC1
VCC1
VCC1
VCC1
R763 10K_0402_5%~D 100K_0402_5%~D R888
1 2 WIRELESS_ON#/OFF <32> CRT_SWITCH CRT_SWITCH B52 B63 SIO_SLP_A# LCD_TST 2 1
GPIOA0 GPIOI1 SIO_SLP_A# <19,52,57>
R2158 100K_0402_5%~D <55> DDR_1.5V_CNTRL0 DDR_1.5V_CNTRL0 A49 A60 0.75V_DDR_VTT_ON 100K_0402_5%~D R767
1 2 BT_RADIO_DIS# MCARD_MISC_PWREN B53 GPIOA1 GPIOI2/TACH0 A61 SIO_SLP_S4# 0.75V_DDR_VTT_ON <55> SYS_LED_MASK# 2 1
<44> MCARD_MISC_PWREN GPIOA2 GPIOI3 SIO_SLP_S4# <19,52,55>
@ R2202 100K_0402_5%~D <62> PROCHOT_GATE PROCHOT_GATE A50 B65 SIO_SLP_S3# 10K_0402_5%~D R775
GPIOA3 GPIOI4 SIO_SLP_S3# <11,19,35,47,52,56>
LID_CL_SIO# B54 A62 IMVP_PWRGD DGPU_PWR_EN 2 1
GPIOA4 GPIOI5 IMVP_PWRGD <60>
1 2 WiGi_RADIO_DIS# DOCK_SMB_ALERT# A51 B66 @ R771 1 2 0_0402_5%~D 100K_0402_5%~D R1582
<46,53> DOCK_SMB_ALERT# GPIOA5 GPIOI6 IMVP_VR_ON <60>
@ R2203 100K_0402_5%~D B55 A63 DOCK_AC_OFF_EC AUX_MODE_EN 2 1
A52 GPIOA6 GPIOI7 DOCK_AC_OFF_EC <63> 100K_0402_5%~D R13
+3.3V_RUN Reserve for WiGig function. <16> GPU_PWR_LEVEL GPIOA7 B67 AUX_EN_WOWL MXM_DP_HDMI_HPD 2 1
USB_SIDE_EN# A33 GPIOJ0 A64 WLAN_LAN_DISB# AUX_EN_WOWL <44> 100K_0402_5%~D R2106
<40,47> USB_SIDE_EN# GPIOB0 GPIOJ1/TACH1 WLAN_LAN_DISB# <37>
1 2 MCARD_PCIE_SATA# EN_I2S_NB_CODEC# B36 A5 SIO_SLP_LAN# USH_PWR_STATE# 2 1
<47> EN_I2S_NB_CODEC# GPIOB1 GPIOJ2/TACH2 SIO_SLP_LAN# <19,37>
R457 100K_0402_5%~D USH_PWR_STATE# A34 B6 SIO_SLP_SUS# 1M_0402_5%~D R2107
<41> USH_PWR_STATE# GPOC2 GPIOJ3 SIO_SLP_SUS# <19>
1 2 WIRELESS_ON#/OFF <63> EN_DOCK_PWR_BAR EN_DOCK_PWR_BAR B37 A6 GPIO_PSID_SELECT
@ R766 100K_0402_5%~D PANEL_BKEN_EC A35 GPOC3 GPIOJ4 B7 MODC_EN GPIO_PSID_SELECT <53>
<28> PANEL_BKEN_EC GPOC4 GPIOJ5 MODC_EN <36>
1 2 SP_TPM_LPC_EN ENVDD_PCH B38 A7 DOCK_HP_DET
<19,28> ENVDD_PCH GPOC5 GPIOJ6 DOCK_HP_DET <47>
@ R772 10K_0402_5%~D LCD_TST A36 B8 DOCK_MIC_DET
<28> LCD_TST GPOC6/TACH4 GPIOJ7 DOCK_MIC_DET <47>
1 2 GPU_PWR_LEVEL PSID_DISABLE# A37
R787 100K_0402_5%~D <53> PSID_DISABLE# PBAT_PRES# B40 GPIOC7 A8 ME_FWP
<53> PBAT_PRES# GPIOD0 GPIOK0 ME_FWP <17>
1 2 DGPU_ALERT# DOCKED A38 B9 MASK_SATA_LED#
<34,37> DOCKED GPIOC1 GPIOK1/TACH3 MASK_SATA_LED# <51>
R788 100K_0402_5%~D DOCK_DET# B41 B10 1.8V_RUN_PWRGD
<46> DOCK_DET# GPIOC0 GPIOK2 1.8V_RUN_PWRGD <56>
AUD_NB_MUTE# A39 A10 LED_SATA_DIAG_OUT# @ R741
<47> AUD_NB_MUTE# GPIOB7 GPIOK3 LED_SATA_DIAG_OUT# <51>
B42 B11 TEMP_ALERT#_R 1 2
GPIOB6 GPIOK4 TEMP_ALERT# <17,21>
LCD_VCC_TEST_EN A40 A11 RUN_ON 0_0402_5%~D
<28> LCD_VCC_TEST_EN GPIOB5 GPIOK5 RUN_ON <35,47,52,56>
CCD_OFF B43 B12
<28> CCD_OFF GPIOB4 GPIOK6 LED_WLAN_WWAN_DIAG_OUT# <51>
AUD_HP_NB_SENSE A41 A12
<47> AUD_HP_NB_SENSE GPIOB3 GPIOK7 SPI_WP#_SEL <17>
ESATA_USB_PWR_EN# B44
<39> ESATA_USB_PWR_EN# GPIOB2 B60 SUS_ON
C GPIOL0/PWM7 SUS_ON <52> C
A57
NVRAM_PWR_EN B32 GPIOL1/PWM8 B64 BAT1_LED#
<44> NVRAM_PWR_EN GPIOD1 GPIOL2/PWM0 BAT1_LED# <47> trace width 20 mils
<63> SLICE_BAT_ON SLICE_BAT_ON A31 B68
SLICE_BAT_PRES# B33 GPIOD2 GPIOL3/PWM1 A9 BAT2_LED#
+3.3V_ALW <46,53,63> SLICE_BAT_PRES# GPIOD3 GPIOL4/PWM3 BAT2_LED# <47> trace width 20 mils
1.5V_RUN_PWRGD B15 B1
<56> 1.5V_RUN_PWRGD A15 GPIOD4 GPIOL5/PWM2 A18 USH_PWR_ON
GPIOD5 GPIOL6 PAD~D T117 @
B16 A44
DDR_1.5V_CNTRL1 A16 GPIOD6 GPIOL7/PWM5
<55> DDR_1.5V_CNTRL1 GPIOD7
1
B34 HW_GPS_DISABLE2#
GPIOM1 HW_GPS_DISABLE2# <43>
Reserve for WiGig function. GPIOM3/PWM4
B39 BREATH_LED#
BREATH_LED# <46,51>
R2097 WiGi_RADIO_DIS# A1 B51
100K_0402_5%~D <42> WiGi_RADIO_DIS# USB_PWR_SHR_EN# B2 GPIOE0/RXD GPIOM4/PWM6
<40> USB_PWR_SHR_EN# NUM_LED# A2 GPIOE1/TXD
2
<51> NUM_LED# MCARD_PCIE_SATA# B3 GPIOE2/RTS# A27 LPC_LAD0

<43> MCARD_PCIE_SATA# GPIOE3/DSR# LAD0 LPC_LAD0 <17,41,42,49>
CPU_DETECT# A3 A26 LPC_LAD1
<7> CPU_DETECT# GPIOE4/CTS# LAD1 LPC_LAD1 <17,41,42,49>
eDP_DET# DGPU_PWR_EN B45 B26 LPC_LAD2
<16> DGPU_PWR_EN GPIOE5/DTR# LAD2 LPC_LAD2 <17,41,42,49>
DGPU_ALERT# A42 B25 LPC_LAD3
<16> DGPU_ALERT# GPIOE6/RI# LAD3 LPC_LAD3 <17,41,42,49>
MXM_DP_HDMI_HPD B4 A21 LPC_LFRAME#
<16> MXM_DP_HDMI_HPD GPIOE7/DCD# LFRAME# LPC_LFRAME# <17,41,42,49>
B22 PCH_PLTRST#_EC
LRESET# PCH_PLTRST#_EC <20,41,42,43,47,49>
1
A28 CLK_PCI_5048
PCICLK CLK_PCI_5048 <20>
6@ R2098 ZODD_WAKE# A59 B20 CLKRUN#
<36> ZODD_WAKE# GPIOF0 CLKRUN# CLKRUN# <19,41,49>
1K_0402_5%~D BCM5882_ALERT# B62 A23
<41> BCM5882_ALERT# GPIOF1 LDRQ0#
SUSACK# A58 A22 LPC_LDRQ1#
<19> SUSACK# GPIOF2 LDRQ1# LPC_LDRQ1# <17>
EDID_SELECT# B61 B21 IRQ_SERIRQ
<32> EDID_SELECT# IRQ_SERIRQ <17,41,49>
2
DGPU_PWROK A56 GPIOF3/TACH8 SER_IRQ A32 CLK_SIO_14M

<16,21> DGPU_PWROK GPIOF4/TACH7 14.318MHZ/GPIOM0 CLK_SIO_14M <18>
VGA_ID B59 B35 EC_32KHZ_ECE5048 EC_32KHZ_ECE5048 <49>
RUN_GFX_ON A55 GPIOF5 CLK32/GPIOM2
<18,52> RUN_GFX_ON GPIOF6
SLP_ME_CSW_DEV# B58
<17,21> SLP_ME_CSW_DEV# GPIOF7 B29 D_LAD0
+3.3V_ALW DLAD0 B28 D_LAD1 D_LAD0 <46>
LAN_DISABLE#_R B47 DLAD1 A25 D_LAD2 D_LAD1 <46>
<37> LAN_DISABLE#_R GPIOG0/TACH5 DLAD2 D_LAD2 <46>
AUX_MODE_EN A45 A24 D_LAD3
GPIOG1 DLAD3 D_LAD3 <46>
100K_0402_5%~D
<51> SYS_LED_MASK# SYS_LED_MASK# B48 B23 D_LFRAME#

GPIOG2 DLFRAME# D_LFRAME# <46>
1
<26> DYN_TURB_SYS_PWR_ALRT# DYN_TURB_SYS_PWR_ALRT# A46 A19 D_CLKRUN#

GPIOG3 DCLKRUN# D_CLKRUN# <46>
@ R800
B <21> SIO_EXT_WAKE# @ R797 1 2 0_0402_5%~D B49

GPIOG4 DLDRQ1#
B24 D_DLDRQ1#
D_DLDRQ1# <46> B
WIRELESS_LED# A47 A20 D_SERIRQ
<42,43,51> WIRELESS_LED# GPIOG5 DSER_IRQ D_SERIRQ <46>
USB_PWR_SHR_VBUS_EN B50
<40> USB_PWR_SHR_VBUS_EN WLAN_RADIO_DIS# A48 GPIOG6
<42> WLAN_RADIO_DIS#
2
GPIOG7/TACH6 A29 BC_INT#_ECE5048

BC_INT# BC_INT#_ECE5048 <49>
B31 BC_DAT_ECE5048
VGA_ID Reserve for WiGig function. WIRELESS_ON#/OFF B13 BC_DAT A30 BC_CLK_ECE5048
BC_DAT_ECE5048 <49>
<47> WIRELESS_ON#/OFF GPIOH0 BC_CLK BC_CLK_ECE5048 <49>
BT_RADIO_DIS# A13
<42,50> BT_RADIO_DIS# GPIOH1
WWAN_RADIO_DIS# A53
<43> WWAN_RADIO_DIS# SYSOPT1/GPIOH2
100K_0402_5%~D
SYS_PWROK B57 A4 RUNPWROK

<7,19> SYS_PWROK SYSOPT0/GPIOH3 PWRGD RUNPWROK <7,49>
1
DGPU_SELECT# B14
<27,28,32> DGPU_SELECT# GPIOH4
R803
eDP_DET# A14 B56 SP_TPM_LPC_EN

GPIOH5 OUT65 SP_TPM_LPC_EN <41>
CPU_VTT_ON B17
<58> CPU_VTT_ON GPIOH6
1 2 B18
<19> PCH_DPWROK GPIOH7
@ R802 0_0402_5%~D B19 1 2
2
TEST_PIN R804 1K_0402_1%~D

B46 +CAP_LDO
CAP_LDO +3.3V_ALW
4.7U_0603_6.3V6K~D
B27 1
VSS C1 @ C711
VGA_ID0 EP
C714
1 2
Discrete 0 DB Version 0.4
ECE5048-LZY_DQFN132_11X11~D 2 0.1U_0402_25V6K~D
UMA 1
5
1
P
<49,62,63> ACAV_IN_NB B
+3.3V_ALW 4 2 1
DOCK_AC_OFF_EC 2 O D34 @ DOCK_AC_OFF <46,63>
+CAP_LDO trace width 20 mils A
33K_0402_5%~D
RB751S40T1_SOD523-2~D
100K_0402_5%~D
@ R770
CLK_SIO_14M CLK_PCI_5048 U47 @
3
1
1
TC7SH08FU_SSOP5~D
R805
1
ME_FWP PCH has internal 20K PD. @ R794 @ R795

(suspend power rail) 10_0402_1%~D 10_0402_1%~D
2
2
A A
ME_FWP
2
LID_CL_SIO# 2 1
LID_CL# <47,51>
1 1 R807 10_0402_1%~D
1
1K_0402_1%~D
0.047U_0402_16V4Z~D
@ R793
@ C712 @ C713 1
C716
4.7P_0402_50V8C~D 4.7P_0402_50V8C~D
2 2

2
2
SIO
WWW.AliSaler.Com

5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com +RTC_CELL +RTC_CELL
100K_0402_5%~D
100K_0402_5%~D
1
1
R810
R819
@ C746 @ C733
+3.3V_ALW 1 2 1 2
C720 1U_0402_6.3V6K~D 1U_0402_6.3V6K~D
2
1 2
1 2 1 2 +3.3V_ALW_PCH
<25> POWER_SW_IN# POWER_SW#_MB <47> <25> DOCK_PWR_SW# DOCK_PWR_BTN# <46>
0.1U_0402_25V6K~D R811 10K_0402_5%~D R825 10K_0402_5%~D
1U_0402_6.3V6K~D
U50 1
1U_0402_6.3V6K~D
1 1 AC_PRESENT 1 2
P
<58,59> 1.05V_VTTPWRGD IN1
C734
4 10K_0402_5%~D R835
O 1.05V_0.8V_PWROK <17,60>
C757
2
<59> VCCSAPWROK IN2
G
2 +3.3V_ALW
74AHC1G08GW_SOT353-5~D 2
SMBUS EA for rise timing fail.
3
LCD_SMBCLK 1 2
prevent material shortage for Thai flood. 2.2K_0402_5%~D R2099
+3.3V_ALW_U54 LCD_SMBDAT 1 2
D D
PJP28 +3.3V_ALW 2.2K_0402_5%~D R2100
PAD-OPEN1x1m DOCK_SMB_DAT 1 2
+RTC_CELL 2 1 2K_0402_5%~D R838
+5V_RUN DOCK_SMB_CLK 1 2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
10U_0603_6.3V6M~D
2K_0402_5%~D R841
2 1 CLK_KBD 1 2 +RTC_CELL_VBAT 1 1 1 1 1 1 1 1 1 BAY_SMBDAT 1 2
0.1U_0402_25V6K~D
R845 4.7K_0402_5%~D @ R815 0_0402_5%~D 2.2K_0402_5%~D R854
C732
C727
C729
C731
C726
C728
C739
C738
C730
2 1 DAT_KBD 1 BAY_SMBCLK 1 2
R846 4.7K_0402_5%~D 2.2K_0402_5%~D R856
C745
2 1 CLK_MSE 2 2 2 2 2 2 2 2 2 DYN_TUR_CURRNT_SET# 1 2
R851 4.7K_0402_5%~D 100K_0402_5%~D R1178
2 1 DAT_MSE 2 DEVICE_DET# 1 2
R852 4.7K_0402_5%~D 100K_0402_5%~D R1125
B64
A11
A22
B35
A41
A58
A52
A26
2 1
B3
PCIE_WAKE#
+RTC_CELL U54 10K_0402_5%~D R759
BC_DAT_EMC4002 1 2
VTR[1]
VTR[2]
VTR[3]
VTR[4]
VTR[5]
VTR[6]
VTR[7]
VTR[8]
VBAT
100K_0402_5%~D R821
2 1 VCI_IN1# BC_DAT_ECE5048 2 1
R1156 100K_0402_5%~D 100K_0402_5%~D R814
1 2 LAT_ON_SW# PS/2 INTERFACE MISC INTERFACE BC_DAT_ECE1117 2 1
R870 100K_0402_5%~D SML1_SMBDATA A5 A10 SYSTEM_ID 100K_0402_5%~D R817
<18> SML1_SMBDATA GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA GPIO021/RC_ID1
SML1_SMBCLK B6 B10 BOARD_ID PBAT_SMBDAT 2 1
+3.3V_RUN <18> SML1_SMBCLK GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK GPIO020/RC_ID2
CLK_TP_SIO A37 B14 DDR_ON 2.2K_0402_5%~D R818
<47> CLK_TP_SIO GPIO110/PS2_CLK2/GPTP-IN6 GPIO025/UART_CLK DDR_ON <55>
DAT_TP_SIO B40 B44 HOST_DEBUG_TX PBAT_SMBCLK 2 1
<47> DAT_TP_SIO GPIO111/PS2_DAT2/GPTP-OUT6 GPIO120/UART_TX HOST_DEBUG_TX <42>
2 1 VOL_MUTE CLK_KBD A38 B46 HOST_DEBUG_RX 2.2K_0402_5%~D R820
<46> CLK_KBD GPIO112/PS2_CLK1A GPIO124/GPTP-OUT5/UART_RX HOST_DEBUG_RX <42>
@ R1177 100K_0402_5%~D DAT_KBD B41 B26 RUNPWROK LPC_LDRQ#_MEC 2 1
<46> DAT_KBD GPIO113/PS2_DAT1A VCC_PRWGD RUNPWROK <7,48>
2 1 VOL_DOWN CLK_MSE A39 A25 EN_INVPWR 100K_0402_5%~D R823 @
<46> CLK_MSE GPIO114/PS2_CLK0A GPIO060/KBRST EN_INVPWR <28>
@ R1197 100K_0402_5%~D DAT_MSE B42 B36 CHARGER_SMBDAT 2 1
<46> DAT_MSE GPIO115/PS2_DAT0A GPIO101/ECGP_SCLK
2 1 VOL_UP PBAT_SMBDAT B59 B37 2.2K_0402_5%~D R827
<53> PBAT_SMBDAT GPIO154/I2C1C_DATA/PS2_CLK1B GPIO103/ECGP_MISO
@ R1118 100K_0402_5%~D PBAT_SMBCLK A56 B38 CHARGER_SMBCLK 2 1
<53> PBAT_SMBCLK GPIO155/I2C1C_CLK/PS2_DAT1B GPIO105/ECGP_MOSI
2 1 GPU_SMBDAT A34 DDR_HVREF_RST_GATE 2.2K_0402_5%~D R828
R829 4.7K_0402_5%~D GPIO102/HSPI_SCLK A35 DYN_TUR_CURRNT_SET# DDR_HVREF_RST_GATE <7>
2 1 GPU_SMBCLK GPIO104/HSPI_MISO A36 CPU1.5V_S3_GATE DYN_TUR_CURRNT_SET# <62>
R822 4.7K_0402_5%~D GPIO106/HSPI_MOSI A40 MSDATA CPU1.5V_S3_GATE <11>
JTAG INTERFACE GPIO116/MSDATA MSDATA <42>
JTAG_TDI A51 B43 MSCLK
GPIO145/I2C1K_DATA/JTAG_TDI GPIO117/MSCLK MSCLK <42>
JTAG_TDO B55 A45 SIO_A20GATE
GPIO146/I2C1K_CLK/JTAG_TDO GPIO127/A20M SIO_A20GATE <21>
JTAG_CLK B56 A55 PS_ID
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK GPIO153/LED3 PS_ID <53>
JTAG_TMS A53 A57 MSDATA 2 1
+3.3V_SUS JTAG_RST# B57 GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS GPIO156/LED1 B61 10K_0402_5%~D R869
JTAG_RST# GPIO157/LED2 B65 FWP# DDR_ON 2 1
1 2 USH_SMBCLK nFWP A46 PROCHOT#_EC 100K_0402_5%~D R876
R589 2.2K_0402_5%~D PROCHOT#/PWM4 PCH_ALW_ON 2 1
1 2 USH_SMBDAT FAN PWM & TACH 100K_0402_5%~D R880
R585 2.2K_0402_5%~D DOCK_POR_RST# B22 GENERAL PURPOSE I/O DOCK_POR_RST# 2 1
<46> DOCK_POR_RST# GPIO050/FAN_TACH1
A21 B2 R884 1 2 1K_0402_1%~D 100K_0402_5%~D R881
GPIO051/FAN_TACH2 GPIO001/ECSPI_CS1 VOL_MUTE <47>
B23 A2 EN_INVPWR 2 1
B24 GPIO052/FAN_TACH3 GPIO002/ECSPI_CS2 B8 R886 1 2 1K_0402_1%~D 100K_0402_5%~D R882
C GPIO053/PWM0 GPIO014/GPTP-IN7/HSPI_CS1 VOL_UP <47> C
PCH_ALW_ON A23 B18 R887 1 2 1K_0402_1%~D 1.05V_0.8V_PWROK 2 1
<52,53> PCH_ALW_ON GPIO054/PWM1 GPIO040/GPTP-OUT3/HSPI_CS2 VOL_DOWN <47>
<28> BIA_PWM_EC BIA_PWM_EC B25 A8 10K_0402_5%~D R883
GPIO055/PWM2 GPIO015/GPTP-OUT7 ME_SUS_PWR_ACK <19>
+3.3V_ALW A24 B9 RESET_OUT# 2 1
GPIO056/PWM3 GPIO016/GPTP-IN8 1.5V_SUS_PWRGD <55>
A9 PM_APWROK 8.2K_0402_5%~D R843 @
GPIO017/GPTP-OUT8 PM_APWROK <19>
10K_0402_5%~D
A14 1.05V_A_PWRGD CPU1.5V_S3_GATE 2 1

GPIO026/GPTP-IN1 1.05V_A_PWRGD <57>
1
BC-LINK B15 ALW_PWRGD_3V_5V 100K_0402_5%~D R889

GPIO027/GPTP-OUT1 ALW_PWRGD_3V_5V <54>
R824
BC_CLK_ECE5048 A43 A17 DEVICE_DET# PCH_RSMRST# 2 1

<48> BC_CLK_ECE5048 GPIO123/BCM_A_CLK GPIO041 DEVICE_DET# <36>
BC_DAT_ECE5048 B45 B39 RESET_OUT# 10K_0402_5%~D R892
<48> BC_DAT_ECE5048 GPIO122/BCM_A_DAT GPIO107/nRESET_OUT RESET_OUT# <19>
BC_INT#_ECE5048 A42 A44
JTAG_RST# citcuit <48> BC_INT#_ECE5048
BC_CLK_EMC4002 A12 GPIO121/BCM_A_INT# GPIO125/GPTP-IN5 B47 PCH_RSMRST#
DYN_TURB_GPU_PWR_ALRT# <16,26>
PCH_RSMRST# <50>
2
close to U51.B57 <25> BC_CLK_EMC4002 BC_DAT_EMC4002 B13 GPIO022/BCM_B_CLK GPIO126 A54 AC_PRESENT

<25> BC_DAT_EMC4002 GPIO023/BCM_B_DAT GPIO151/GPTP-IN4 AC_PRESENT <19>
JTAG_RST# BC_INT#_EMC4002 A13 B58 SIO_PWRBTN#
<25> BC_INT#_EMC4002 GPIO024/BCM_B_INT# GPIO152/GPTP-OUT4 SIO_PWRBTN# <19>
B20
GPIO044/BCM_C_CLK
0.1U_0402_25V6K~D
PCH_PCIE_WAKE# A18
<19> PCH_PCIE_WAKE# GPIO043/BCM_C_DAT
1
1
100_0402_1%~D
1 PCIE_WAKE# B19 SMBUS INTERFACE

<16,42,43,47> PCIE_WAKE# GPIO042/BCM_C_INT#
@
BC_CLK_ECE1117 A20 A3 DOCK_SMB_DAT

1
<50> BC_CLK_ECE1117 GPIO047/LSBCM_D_CLK GPIO003/I2C1A_DATA DOCK_SMB_DAT <46>

JTAG1 CONN@
@SHORT PADS~D
C735
R836
<50> BC_DAT_ECE1117 BC_DAT_ECE1117 B21 B4 DOCK_SMB_CLK

GPIO046/LSBCM_D_DAT GPIO004/I2C1A_CLK DOCK_SMB_CLK <46>
BC_INT#_ECE1117 A19 A4 LCD_SMBDAT
2 <50> BC_INT#_ECE1117 GPIO045/LSBCM_D_INT# GPIO005/I2C1B_DATA LCD_SMBDAT <26,28>
BEEP A16 B5 LCD_SMBCLK
<47> BEEP LCD_SMBCLK <26,28>
2
SIO_SLP_S5# B16 GPIO032/GPTP-IN3/BCM_E_CLK GPIO006/I2C1B_CLK B7 BAY_SMBDAT

<19> SIO_SLP_S5# GPIO31/GPTP-OUT2/BCM_E_DAT GPIO012/I2C1H_DATA/I2C2D_DATA
ACAV_IN_NB A15 A7 BAY_SMBCLK
<48,62,63> ACAV_IN_NB GPIO30/GPTP-IN2/BCM_E_INT# GPIO013/I2C1H_CLK/I2C2D_CLK B48 GPU_SMBDAT
GPIO130/I2C2A_DATA GPU_SMBDAT <16>
2
B49 GPU_SMBCLK
GPIO131/I2C2A_CLK GPU_SMBCLK <16>
HOST INTERFACE A47 CHARGER_SMBDAT
CHARGER_SMBDAT <62>
2
SIO_EXT_SMI# A6 GPIO132/I2C1G_DATA B50 CHARGER_SMBCLK

<17,20> SIO_EXT_SMI# GPIO011/nSMI GPIO140/I2C1G_CLK CHARGER_SMBCLK <62>
SIO_RCIN# A27 B52 CARD_SMBDAT
<21> SIO_RCIN# GPIO061/LPCPD# GPIO141/I2C1F_DATA/I2C2B_DATA CARD_SMBDAT <47>
LPC_LDRQ#_MEC B29 A49 CARD_SMBCLK
LDRQ# GPIO142/I2C1F_CLK/I2C2B_CLK CARD_SMBCLK <47>
IRQ_SERIRQ A28 B53 USH_SMBDAT
<17,41,48> IRQ_SERIRQ SER_IRQ GPIO143/I2C1E_DATA USH_SMBDAT <41>
PCH_PLTRST#_EC B30 A50 USH_SMBCLK
<20,41,42,43,47,48> PCH_PLTRST#_EC LRESET# GPIO144/I2C1E_CLK USH_SMBCLK <41>
CLK_PCI_MEC A29
<20> CLK_PCI_MEC PCI_CLK
LPC_LFRAME# B31
<17,41,42,48> LPC_LFRAME# LFRAME#
LPC_LAD0 A30 DELL PWR SW INF
<17,41,42,48> LPC_LAD0 LAD0
LPC_LAD1 B32 A59
32 KHz Clock
1 2 MEC_XTAL2
<17,41,42,48> LPC_LAD1
<17,41,42,48> LPC_LAD2
<17,41,42,48> LPC_LAD3
LPC_LAD2
LPC_LAD3
CLKRUN#
A31
B33
A32
LAD1
LAD2
LAD3
BGPO0
VCI_IN2#
VCI_OUT
B63
A60
A63
LAT_ON_SW#
ALWON
VCI_IN1#
ALWON <54>
<19,41,48> CLKRUN# CLKRUN# VCI_IN1#
@ R1068 0_0402_5%~D SIO_EXT_SCI# A33 B67 POWER_SW_IN# R862 close to
<21> SIO_EXT_SCI# GPIO100/nEC_SCI VCI_IN0# B1 ACAV_IN
U54 at least 250mils +1.05V_RUN_VTT
MEC_XTAL2_R
VCI_OVRD_IN ACAV_IN <16,25,62,63>

MEC_XTAL1 A1 DOCK_PWR_SW#
VCI_IN3# @ R862
MASTER CLOCK
MEC_XTAL1 A61 PECI B51 +PECI_VREF 1 2
MEC_XTAL2 A62 XTAL1 PECI_VREF A48 PECI_EC_R 1 2 0_0402_5%~D
XTAL2 PECI PECI_EC <7>
1 2 B62 DB Version 0.12 R863 43_0402_5%~D
Y6 <48> EC_32KHZ_ECE5048 GPIO160/32KHZ_OUT
0.1U_0402_25V6K~D
@ R867 0_0402_5%~D I2S B17 1
2 1 I2S_DAT B27
VSS_RO
I2S_CLK
VR_CAP
C737
B34 B28
VSS[1]
VSS[4]
NC1 I2S_WS
AGND
B 32.768KHZ_12.5PF_Q13FC1350000~D A64 B
B68 NC2 EP 2
NC3
39P_0402_50V8J~D
39P_0402_50V8J~D
2 1 MEC5055-LZY_DQFN132_11X11~D
B66
B11
B60
+VR_CAP B12
B54
C1
C743
C741
Crystal EA.
1 2
15mil Change to CPN: SA00003TZ2L
least
4.7U_0603_6.3V6K~D
15mil 1
C740
2
C740 close to U51.B12
Place closely pin A29 Place closely pin B22
+3.3V_M
CLK_PCI_MEC DOCK_POR_RST# +3.3V_RUN
+3.3V_ALW
1
1
10_0402_1%~D
@ R885
10K_0402_5%~D
R893 1 2
1
0.1U_0402_25V6K~D
10K_0402_5%~D
100K_0402_5%~D @ R1180 0_0402_5%~D

1
R799
1
4.7P_0402_50V8C~D
C736
R872
2
PCH_PWRGD# <25> H_PROCHOT# <7,26,60,62>

1
2
2
@ C747
2
1
RESET_OUT# 2 FWP# RUNPWROK
2
Q52
1
D
10K_0402_5%~D
S
3
+1.05V_RUN_VTT
@ Q47
PROCHOT#_EC 2
1
D
@ R879
Q45
G
2 S
<52> RUN_ON_ENABLE#
3
G
S
1
1
10K_0402_5%~D
@ R1179
+3.3V_ALW
2
+3.3V_ALW
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
R864 R875 C744 REV +3.3V_ALW PROCHOT#_EC

1
+3.3V_ALW
1K_0402_1%~D
1 2
1
R858
R859
R860
R861
100K_0402_5%~D
240K 4700p X00_SSI Change board ID to A00
1
2
R871
49.9_0402_1%~D
+PWR
A A
@ R812
R875
130K 4700p X01_Pre-PT
1
1
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
100K_0402_5%~D
@ R850
CONN@ 8.2K_0402_5%~D
2
R847
R848
R849
JDEG1
62K 4700p X02_PT2
2
1
2
1
1 2 JTAG_TDI BOARD_ID SYSTEM_ID
2 33K 4700p X03_ST
4700P_0402_25V7K~D
3 JTAG_TMS
2
3 4 JTAG_CLK
11
4
5
5
6 MSCLK
JTAG_TDO * 8.2K 4700p A00_X-build 1
C744
1
G1 6 4.3K 4700p
C742
12 7 MSDATA 4700P_0402_25V7K~D
G2 7 8 HOST_DEB_TX 1 2 HOST_DEBUG_TX
8 9 HOST_DEB_RX @ R853 1 2 0_0402_5%~D HOST_DEBUG_RX 2K 4700p 2 2
9
10
10 @ R855 0_0402_5%~D
1K 4700p DELL CONFIDENTIAL/PROPRIETARY
TYCO_1-2041070-0~D
Link CIS OK CHIPSET_ID for BID function
Title
EMC5055
WWW.AliSaler.Com
BOARD_ID rise time is measured from 5%~68%.
0722 Size Document Number
LA-7931P
Rev
1.0

5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com
D D
BlueTooth JBT1 pin11 Need confirm with Dell to add BT_DET or not.
+3.3V_RUN
0.1U_0402_25V6K~D
+3.3V_RUN 1 2 BT_COEX_STATUS2
For meet T235(power off)= min 40ns(SPEC).T08a(power on)= max 90ms. R1133 1K_0402_1%~D
1 2 BT_PRI_STATUS 1
RSMRST circuit
C748
R1134 1K_0402_1%~D JBT1
1 2 CONN@
@ R1623 0_0402_5%~D 14
+5V_ALW_PCH +3.3V_ALW_PCH 2 13 GND
GND
+3.3V_ALW 12
2 C289 11 12
11
1
1 2 10
<42> COEX1_BT_ACTIVE 10
R2159 R1622 9
0_0402_5%~D 100K_0402_5%~D 0.1U_0402_25V6K~D <41> BT_COEX_STATUS2 8 9
<41> BT_PRI_STATUS 7 8
1
U4 <51> BT_ACTIVE 7
5
EC SIDE U7 BT_RADIO_DIS#_D 6
2
1 @ R2142 5 6
P
<49> PCH_RSMRST# IN1 <42> COEX2_WLAN_ACTIVE 5
+5V_ALW_PCH_R 1 4 1 2 PCH_RSMRST#_Q <17,19> 4
VCC O 4
0.01U_0402_16V7K~D
3 RSMRST# 2 3
RESET# IN2 3
G
1 2 0_0402_5%~D 2
GND <20> USBP11- 2
74AHC1G08GW_SOT353-5~D 1
<20> USBP11+
3
1
C290
C C
RT9818A-44GU3_SC70-3~D prevent material shortage for Thai flood. ACES_50450-0127N-001
2
100P_0402_50V8J~D
R2206 1 2 0_0402_5%~D
33P_0402_50V8J~D
10K_0402_5%~D
Link CIS OK
@ C754
1 1
C753
R904
1 2 BT_RADIO_DIS#_D
<42,48> BT_RADIO_DIS#
@ D106
RB751S40T1_SOD523-2~D 2 2 0914
2
Reserve for WiGig card function
JBT1 pin1~pin12 pin define order swap to
pin12~pin1 for BT connector change to
ACES_50450-0127N-001.
(because footprint different from ACES_50228-0127N_001)
Keyboard
B B
JKB1 CONN@
+3.3V_ALW +5V_RUN KB_DET# 1 2 KB_DET#
<21> KB_DET# PS2_CLK_TS 3 1 2 4 PS2_CLK_TS
<47> PS2_CLK_TS 3 4 6
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
PS2_DAT_TS 5 PS2_DAT_TS
<47> PS2_DAT_TS 5 6 8
1 1 +3.3V_ALW 7 +3.3V_ALW
9 7 8 10
+5V_RUN 9 10 12 +5V_RUN
C756
C758
11 BC_INT#_ECE1117
<49> BC_INT#_ECE1117 13 11 12 14 BC_DAT_ECE1117
2 2 <49> BC_DAT_ECE1117 13 14 16
15
17 15 16 18 BC_CLK_ECE1117
<49> BC_CLK_ECE1117 17 18 20
19
19 20
Place close to JKB1 AMPHE_G281010112CHR~D
Link CIS OK
0722
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Touch PAD/Int KB

5 4 3 2 1
5 4 3 2 1
HDD LED
WWW.AliSaler.Com
+3.3V_ALW
+5V_ALW
1
R932
10K_0402_5%~D
3
2
Q74B Q74A
DMN66D0LDW-7_SOT363-6~D D59 DMN66D0LDW-7_SOT363-6~D
<17> SATA_ACT#
4 3 1 2
RB751S40T1_SOD523-2~D
1 6 2
Q75
NUM LED
D PDTA114EU_SC70-3~D D
+5V_RUN
2
<48> MASK_SATA_LED#
3
MASK_BASE_LEDS#
1 2
D62 680_0402_5%~D R934 SATA_LED <47>
1 2 2
<48> LED_SATA_DIAG_OUT# Meet LED brightness spec. <48> NUM_LED#
RB751S40T1_SOD523-2~D Q80
+5V_ALW PDTA114EU_SC70-3~D
1
3
Q326
SSM3K7002FU_SC70-3~D 1 2
806_0402_1%~D R942 NUM_LED <47>
D
3 1 2
Q86
Meet LED brightness spec.
PDTA114EU_SC70-3~D
G
2
1
SYS_LED_MASK#
R943 1 2 510_0402_1%
SATA_SIDE_LED <47>
Breath LED
WWAN/WLAN LED
Change B39 of ECE5048 EC code to GPIO(input) BREATH_LED side view.
C
Solving LED flicker when AC-in plug. Meet LED brightness spec. C
+3.3V_ALW +3.3V_ALW 1 2 BREATH_LED#_Q

<46,48> BREATH_LED# BREATH_LED#_Q <47>
340_0402_1% R956
+5V_ALW
1
R944 R937
change to single package.
100K_0402_5%~D 100K_0402_5%~D
Q84
3
Q78B Q78A SSM3K7002FU_SC70-3~D
2
DMN66D0LDW-7_SOT363-6~D D60 DMN66D0LDW-7_SOT363-6~D
D
4 3 1 2 1 6 2 3 1 1 2 BREATH_WHITE_LED <47>
<42,43,48> WIRELESS_LED#
300_0402_1% R955
RB751S40T1_SOD523-2~D Q79
PDTA114EU_SC70-3~D
G
BREATH_LED TOP view.
5
2
MASK_BASE_LEDS#
MASK_SATA_LED#
1
D63 MASK_BASE_LEDS#
1 2
<48> LED_WLAN_WWAN_DIAG_OUT#
RB751S40T1_SOD523-2~D 1 2
WLAN_LED <47>
680_0402_5%~D R939
BT LED
improve BT_LED behaviour abnormal(BT_LED must dark) in S3/S4/S5. Remove Q339 for WiGig card function usage.
+3.3V_ALW
100K_0402_5%~D
MASK_BASE_LEDS#
1
B B
R938
2
2
1 2 WiGi_BT_LED#_R 1 6 1 2
<42> WiGi_BT_LED# BT_LED <47>
@ R2207 0_0402_5%~D R941 680_0402_5%~D
Q318A
WiGi_BT LED function. DMN66D0LDW-7_SOT363-6~D Meet LED brightness spec.

3
Q318B
5
<50> BT_ACTIVE
4
+3.3V_ALW
C778
1 2
0.1U_0402_25V6K~D
5
U58
SYS_LED_MASK# 1
LED Circuit Control Table
P
<48> SYS_LED_MASK# IN1 4 MASK_BASE_LEDS#
LID_CL# 2 O MASK_BASE_LEDS# <47>
<47,48> LID_CL# IN2
G
SYS_LED_MASK# LID_CL# 74AHC1G08GW_SOT353-5~D
3
prevent material shortage for Thai flood.
Mask All LEDs (Sniffer Function) 0 X
Mask Base MB LEDs (Lid Closed) 1 0
Fiducial Mark Do not Mask LEDs (Lid Opened) 1 1
@ FD1
1 for Hi-POT issue.
A FIDUCIAL MARK~D A
@ H1 @ H4 @ H5 @ H6 @ H7 @ H8 @ H9 @ H10 @ H11 @ H12 @ H13 @ H14 @ H15 @ H16 @ H17 @ H18 @ H19 @ H20 @ H21
@ FD2 H_2P8 H_2P8 H_3P2x6P2N H_2P8 H_3P8 H_3P3 H_3P3 H_3P3 H_3P3 H_2P3 H_3P2 H_2P8 H_2P8 H_3P8 H_2P8 H_4P1 H_4P1 H_2P8 H_4P1x2P1
1
FIDUCIAL MARK~D
1
@ FD3
1
FIDUCIAL MARK~D @ H22 @ H23 @ H24 @ H25 @ H26 @ H27

@ FD4
H_2P8 H_4P1 H_4P1 H_2P8 H_2P8 H_2P3
1 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
PAD & Standoff & LED
1
FIDUCIAL MARK~D BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
5
ME request.
4 WWW.AliSaler.Com 3
2
LA-7931P
1
Sheet 51 of 70
1.0
5 4 3 2 1
WWW.AliSaler.Com +3.3V_ALW
+3.3V_ALW to +3VMXM
Q25
+1.05V_RUN Source
+PWR_SRC_S SI3456DDV-T1-GE3_TSOP6~D +3.3V_MXM
+PWR_SRC_S +1.05V_M Q63
D
6 +3.3V_ALW2 SI4164DY-T1-GE3_SO8~D +1.05V_RUN
S
10U_0805_10V4Z~D
5 4 40mil(1A) 8 1
1
200K_0402_5%
1 2 7 2
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
10U_0603_6.3V6M~D
1 R930 6 3
1
R269
C357
20K_0402_5%~D
1 1 330K_0402_5%~D 5 1
1
C449
C772
R931
3
2
C354
R909
4
100K_0402_5%~D +1.05V_RUN_ENABLE
2
2 2 2
2
+3.3V_ALW2
3
100P_0402_50V8J~D
+3VMXM_GATE
1
1M_0402_5%~D
0.1U_0603_25V7K~D
Q304B
R1611
1
1
D D
100K_0402_5%~D
1M_0402_5%~D
1 RUN_ON_ENABLE# 5
<49> RUN_ON_ENABLE#
R2104
C352
C773
R294
2
2
Solve 300mW
6
2 1 2
<11,19,35,47,48,56> SIO_SLP_S3#
2
3
@ R781 0_0402_5%~D
PWR consumption
2
Q304A
issue.
Q294B
1 2 2
<35,47,48,56> RUN_ON
RUN_GFX_ON# 5 @ R762 0_0402_5%~D
1
4
6
+5V_RUN Source
2 +PWR_SRC_S +5V_ALW Q329 +5V_RUN
<18,48> RUN_GFX_ON
Q294A
DMN3030LSS-13_SOP8L-8
+5V_ALW to +5VMXM
470K_0402_5%~D
8 1
100K_0402_5%~D
1
1
1
0.1U_0603_25V7K~D
1 7 2
R2067
10U_0805_10V4Z~D
@
+5V_ALW +5V_MXM 6 3
R301
1
C362
20K_0402_5%~D
Q76 5 1
C1271
SI4800BDY-T1-GE3_SO8
R2068
2 +PWR_SRC_S 8 1
2
4
10U_0805_10V4Z~D
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
1 7 2 100mil(2.5A)
6 3 +5V_RUN_ENABLE 2
1 1
2
C353
5
C356
C351
1
1
2 D
200K_0402_5%
220P_0402_50V8J~D
Solve 300mW
4
2 2
R275
Q330
2
1
G PWR consumption
C1272
S
3
issue.
2
2
+5VMXM_GATE
0.1U_0603_25V7K~D
@
1
0_0402_5%~D
1
R278
1
D C355
+3.3V_RUN Source
Q36
2
G 2 2
+3.3V_ALW Q331 +3.3V_RUN
S
3
+PWR_SRC_S DMN3030LSS-13_SOP8L-8
8 1
470K_0402_5%~D
10U_0805_6.3V6M~D
7 2
1
20K_0402_5%~D
6 3
Solve 300mW 1
R2069
5
C1273
R2070
PWR consumption
Solve S4/S5 +MXM_PWR_SRC leakage in DC mode.
4
2
issue.(R2069, C1274)
2
C
MXM_PWR_SRC Source <26> MXM_SENSE_N +3.3V_RUN_ENABLE
C
<26> MXM_SENSE_P
1M_0402_5%~D
220P_0402_50V8J~D
+PWR_SRC_MXM
1
D
@ R2127
C1274
+PWR_SRC_MXM Q186 2 3 +MXM_PWR_SRC 2
100K_0402_5%~D
Q332
SI4835DDY-T1-GE3_SO8~D G
1
1 8 +MXM_PWR 1 4 S
2
R940
10U_1206_25V6M~D
2 7
2
1
100K_0402_5%~D
3 6 1
5 0.005_2512_1%
R1973
C776
R935
2
2
Meet power sequencing 0.7V.
2
+MXM_SRC_EN#
2200P_0402_50V7K~D
1
D
Q87
RUN_GFX_ON 2 1 R935 form 20K to 100K

G
Power saving.
C774
S
3
+3.3V_SUS Source +PWR_SRC_S +3.3V_SUS

+3.3V_ALW Q54
D
R911 6
+3.3V_ALW_PCH Source
S
+3.3V_ALW2 100K_0402_5%~D 5 4
+PWR_SRC_S +3.3V_ALW Q49 +3.3V_ALW_PCH 2
10U_0603_6.3V6M~D
20K_0402_5%~D
+3.3V_ALW2 SI3456DDV-T1-GE3_TSOP6~D 1
1
100K_0402_5%~D
G
1
D
C765
R914
6
S
3
1
100K_0402_5%~D
5 4 R915 +SUS_ENABLE
1
R905
2 100K_0402_5%~D
3
2
R907
10U_0603_6.3V6M~D
1M_0402_5%~D
470P_0402_50V7K~D
1
2
1
20K_0402_5%~D
1
G
2
1
C760
Q303B
R1618
2
R908
+3V_ALW_PCH_ENABLE SUS_ON_3.3V# 5 1
2
C767
3
6
2
2
1M_0402_5%~D
3300P_0402_50V7K~D
2
1
2
Q305B
Q303A
1
R1619
C762
ALW_ON_3.3V# 5 1 2 2
<23> ALW_ON_3.3V# <48> SUS_ON
@ R806 0_0402_5%~D
6
1
Q305A 2 1 2
<19,48,55> SIO_SLP_S4#
2
DMN66D0LDW-7_SOT363-6~D @ R808 0_0402_5%~D

B B
2
<49,53> PCH_ALW_ON
tune +3.3V_SUS timing begin to +3.3V_RUN for solving Smart card detect issue.
1
+3.3V_M Source +3.3V_MXM +5V_MXM

+3.3V_ALW Q58
+PWR_SRC_S SI3456DDV-T1-GE3_TSOP6~D +3.3V_M
+3.3V_ALW2
D
6
S
1
1
470_0603_5%
470_0603_5%
R917 5 4
10U_0603_6.3V6M~D
470K_0402_5%~D 2
1
R268
R274
1
20K_0402_5%~D
R918 1
G
1
C768
@ R919
100K_0402_5%~D
2
+A_ENABLE
2
2
+3VMXM_D
+5VMXM_D
4.7M_0402_5%~D
2
1
Q57B
220P_0402_50V8J~D
R1617
A_ON_3.3V# 5
1
6
C770
4
D D
@
Q57A
2
Q48
Q50
DMN66D0LDW-7_SOT363-6~D RUN_GFX_ON# 2 2
2 Solve 300mW G G
<19,48,57> SIO_SLP_A#
PWR consumption S S
3
3
1
issue.
pop for boot leakage to +3.3v_run.
Discharg Circuit
+3.3V_SUS +3.3V_ALW_PCH +5V_RUN +1.5V_RUN +3.3V_RUN +1.05V_RUN +1.5V_CPU_VDDQ +0.75V_DDR_VTT +3.3V_M
1
R926 R916
A @ R922 @ R928 @ R923 @ R924 R929 @ R925 220_0402_5%~D R927 39_0603_5%~D A
1K_0402_1%~D 1K_0402_1%~D 1K_0402_1%~D 1K_0402_1%~D 39_0603_5%~D 39_0402_5%~D 22_0603_5%~D
2
2
+3.3V_ALWPCH_CHG
+5V_RUN_CHG
+1.5V_RUN_CHG
+3.3V_RUN_CHG
+1.05V_RUN_CHG
+1.5V_CPU_VDDQ_CHG
+3.3V_M_CHG
+3.3V_SUS_CHG
+DDR_CHG
1
D D D D D
@ Q67
@ Q68
@ Q70
1
D D D
@ Q65
@ Q66
Q69
Q72
RUN_ON_ENABLE# 2 2 2 2 2
1
D
Q60
SUS_ON_3.3V# 2 ALW_ON_3.3V# 2 G G G G G A_ON_3.3V# 2

Q71
G G S S S S 2 S G
<7,11> RUN_ON_CPU1.5VS3#
3
G
S S S
3
S
3
Title
Power Control
5 4 3
WWW.AliSaler.Com 2
Size
Date:
Document Number

LA-7931P
1
Sheet 52 of 70
Rev
1.0
5 4 3 2 1
WWW.AliSaler.Com +COINCELL
COIN RTC Battery

PL1
1
HCB2012KF-121T50_0805
2 1 +PWR_SRC_MXM PR1
+PWR_SRC 1K_0402_5%~D
+3.3V_RTC_LDO
10U_0805_25V6K
0.1U_0603_25V7K~D
2
1
100U_25V_M~D
JRTC1
Z4012
1
1
+
PC1
PC31
PC30
+COINCELL 1
2 1
2
2
D
@ @ 2 3 D
GND
2
4
+RTC_CELL GND
ESD Diodes
ACES_50271-0020N-001
PD1
1
RB715FGT106_UMD3 1
PC2
1U_0603_10V4Z~D
2
1
Move to power schematic
PD2 @ PD3 @
PESD24VS2UT_SOT23-3~D PESD24VS2UT_SOT23-3~D
3
PL2 +3.3V_ALW
FBMJ4516HS720NT_2P~D
1 2
Primary Battery Connector
PL6
1
FBMJ4516HS720NT_2P~D
100K_0402_5%~D
PBATT1 PBATT+_C 1 2 PBATT+
PR2
11
0.1U_0603_25V7K~D
GND
1
10
GND
PC3
1 PR3
2
9 2 100_0402_5%~D PR5
2
8 3 Z4304 1 2 100_0402_5%~D PR4
2200P_0402_50V7K~D
7 PBAT_SMBCLK <49>
4 Z4305 1 2 100_0402_5%~D
6 PBAT_SMBDAT <49>
5 Z4306 1 2
5 PBAT_PRES# <48>
1
PC4
6
4 7 PQ1
3 8
2
2 9 FDN338P_G_NL_SOT23-3~D
C C
1 PD5
SUYIN_200045GR009M28QL 1 2 1 3
3
DOCK_SMB_ALERT# <46,48>
SDMK0340L-7-F_SOD323-2~D
2
2
@ PR6
0_0402_5%~D
GND 1 2
<46,48,63> SLICE_BAT_PRES#
1
PC5
1500P_0402_7K~D
2
+5V_ALW
DA204U_SOT323~D
+3.3V_ALW
2
PD7
GND
@ PR7 PU1
2.2K_0402_5%~D
2
1 2 @ <46> DOCK_PSID 1 6 GPIO_PSID_SELECT <48>
0_0402_5%~D NO IN
PR8
1
2 5 +5V_ALW
PL3 PR9 GND V+
1
BLM18BD102SN1D_0603~D 33_0402_5%~D
NB_PSID 2 1 1 3 1 2 NB_PSID_TS5A63157 3 4
D
S
NC COM PS_ID <49>
100K_0402_1%~D
PQ2 TS5A63157DCKR_SC70-6~D
2
FDV301N_G_NL_SOT23-3~D
G
2
PR10
+5V_ALW
10K_0402_1%~D
1
1
B C B
PR11
2 PQ3
B MMST3904-7-F_SOT323~D
E
15K_0402_1%~D
3
2
2
PR12
PR13
1 2
PSID_DISABLE# <48>
1
@ 10K_0402_5%~D
DC_IN+ Source +PWR_SRC_S

+PWR_SRC
3 1
SI7149DP PQ5
100K_0402_1%~D
+DC_IN +DC_IN_SS
0.1U_0603_25V7K~D
0.22U_0603_25V7K~D
1
1
1
PR15
PC7
PC8
2
3 5
PL4
2
C8B BPH 853025_2P~D
2
1 2 +DC_IN PQ4
4
PR17 TP0610K-T1-E3_SOT23-3
1
1M_0402_5%~D
22K_0402_1%
0.022U_0805_50V7K~D
2
1 2
100K_0402_5%~D
10U_0805_25V6K
VSB_N_001
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
1
1VSB_N_003
PC9
PR16
PJPDC1
1
PC10
PC12
PC13
PR18
PC14
1 @ PR21 0_0402_5%~D
0.1U_0603_25V7K~D
1 2
1
PR20
4.7K_0805_5%~D
2 3
1
1 2 1 2VSB_N_002
0.1U_0603_25V7K~D
SOFT_START_GC <63> +3.3V_ALW
2
3 4
1
PQ7
PC11
4 5
@ PR19
10K_0402_5%~D 1 2 2
5 6
1
<49,52> PCH_ALW_ON
PC15
1M_0402_5%~D
@ G
2
6 7 +DCIN_JACK PR23 .1U_0402_16V7K~D S

2
3
7 8
1
PR22
PC16
A 0_0402_5%~D A
8 9 @
9 10
2
10 11
11
ACES_50290-01101-001
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D +DCIN
WWW.AliSaler.Com
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1.0
LA-7931
5 4 3 2 1
A B C D E
WWW.AliSaler.Com
2VREF_6182
1
1 1
PC101
1U_0603_16V6K~D @ PC121
2
@ PC120 2 1
2 1
22P_0402_50V8J~D
22P_0402_50V8J~D
PR101 PR102
13.7K_0402_1%~D 30.9K_0402_1%~D
1 2 1 2
+PWR_SRC +DC1_PWR_SRC PR103 PR104

20K_0402_1%~D 20K_0402_1%~D +DC1_PWR_SRC
1 2 FB_3V 1 2
PL100 +3.3V_RTC_LDO
1UH_PCMB053T-1R0MS_7A_20% FB_5V
2 1
+3.3V_ALW2
@ PR105 PR106 PR107
2200P_0402_50V7K~D
2200P_0402_50V7K~D
0_0402_5%~D 110K_0402_1%~D 124K_0402_1%~D
0.1U_0402_25V6K~D
4.7U_0805_25V6K~D
0.1U_0402_25V6K~D
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
1 2 1 2ENTRIP2 1
ENTRIP1 2
1
1
PC102
PC103
PC104
PC106
PC107
PC108
PC109
PQ101
1
FDMC8884_POWER33-8-5 PU101
2
5
ENTRIP2
FB2
FB1
TONSEL
REF
ENTRIP1
1
PC105 PQ102
4 10U_0805_6.3V6M~D 25 FDMC8884_POWER33-8-5
P PAD
2
7 24 4
2 VO2 VO1 2
1
2
3
PC100 8 23 PC110
0.22U_0603_16V7K~D VREG3 PGOOD 0.22U_0603_16V7K~D
PR108 PR109
1 2 BST1_3V 1 2 BST_3V 9 22 BST_5V 1 2 BST1_5V 1 2
3
2
1
BOOT2 BOOT1
2.2_0603_5%~D 2.2_0603_5%~D
PL103 UG_3V 10 21 UG_5V PL102
2.2UH_FDSD0630-H-2R2M-P3_8.3A_20% UGATE2 UGATE1 3.3UH_FDV0630-3R3M-P3_5.7A_20%
+3.3V_ALWP 1 2 LX_3V 11
PHASE2 PHASE1
20 LX_5V 1 2
+5V_ALWP
1
1
4.7_1206_5%~D
4.7_1206_5%~D
LG_3V 12 19 LG_5V
LGATE2 LGATE1
220U_6.3V_M
PR110
PR111
@ @
SKIPSEL
220U_6.3V_M
1
VREG5
1
GND
VIN
PC112
FDMC7692S_POWER33-8-5
NC
EN
2
2
1
PC113
4 4 +
@ PR113 @ PC198
13
14
15
16
17
18
SNUB_3V
SNUB_5V
2 PQ103 499K_0402_1%~D 56P_0402_50V8J~D PQ104
2
FDMC7692S_POWER33-8-5 2 1 RT8205LZQW(2) WQFN 24P PWM 2
2
680P_0603_50V7K~D
1
2
3
3
2
1
680P_0603_50V7K~D
PC199
56P_0402_50V8J~D
+5V_ALW2
1
1
PC114
@
+3.3V_ALWP @
PC115
@
TDC 6 A
2
2
1
1
Peak Current 8 A
300K_0402_1%
1U_0603_10V6K~D
1
+3.3V_ALW
PC116
@ PD100 PC117
OCP current 9.6 A
PR112
MMSZ5229BS_SOD323~D 4.7U_0805_10V6K~D
2
1 2
+PWR_SRC
2
@
2 +DC1_PWR_SRC PR114
470K_0402_5%~D
1
3 3
1
PC118
2VREF_6182
2
ENTRIP2
ENTRIP1
0.1U_0603_25V7K~D
ALW_PWRGD_3V_5V <49>
+5V_ALWP
TDC 6.5 A
3
Peak Current 9.2 A

PQ106B
PQ106A
5 2 OCP current 11 A
@
PJP102
4
1 2
PAD-OPEN 4x4m
PR117
@
100K_0402_1%~D PJP103
1 2 1 2
+5V_ALW2
1
+5V_ALWP PAD-OPEN 4x4m +5V_ALW

PR115 PQ105
2K_0402_1%~D PDTC115EU_SOT323-3 @
1 2 2 PJP104
<49> ALWON
1 2 +3.3V_ALW
@ PR118 +3.3V_ALWP
0_0402_5%~D
PAD-OPEN 4x4m
1 2
<25> THERM_STP#
3
@
4 PJP105 4
1U_0603_10V6K~D
1 2
1
PC119
PAD-OPEN 4x4m
2

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +5V_ALWP/+3.3V_ALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
WWW.AliSaler.Com
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
LA-7931
A B C D E
A B C D
WWW.AliSaler.Com @
@ PJP204
0.75Volt +/- 5%
+PWR_SRC PJP201 VLDOIN_1.5V 1 2 +1.5VP TDC 1.4 A
1 2 1.5V_B+
PR201 Peak Current 2 A
1 2 BOOT_1.5V PAD-OPEN1x1m
PAD-OPEN 4x4m 2.2_0603_5%~D
2200P_0402_50V7K~D
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
0.1U_0402_25V6K~D
0.22U_0603_16V7K~D
DH_1.5V
+0.75VSP
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
1
1
1 1
PC205
SW_1.5V
FDMS7698 1N POWER56-8
PC201
PC202
PC203
PC204
1
2
1
PC206
PC207
DL_1.5V
16
17
18
19
20
1.5VP
PQ201
PU201
TDC 13 A
PHASE
UGATE
BOOT
VLDOIN
VTT
2
21
PAD
Peak Current 18.4 A
4 15 1
OCP current 22 A LGATE VTTGND
PR202 14 2
PL201 6.98K_0402_1%~D PGND VTTSNS
1
2
3
FDMS0309S_POWER56-8-5
1.0UH_PCMC104T-1R0MN_20A_20% 1 2 CS_1.5V
1 2 13 3
+1.5VP PC208 CS RT8207MZQW_WQFN20_3X3 GND
5
4.7_1206_5%~D
1U_0603_10V6K~D
+V_DDR_REF
PQ202
PR203
@ PR204 12 4
VDDP VTTREF
220U_D2_4VM~D
1 5.1_0603_5%~D
+5V_ALW
PC209
+ 1 2 VDD_1.5V 11 5 PC210
SNUB_1.5V 2 VDD VDDQ
PGOOD
4 0.033U_0402_16V7~D
PC211
TON
2
56P_0402_50V8J~D
FB
S5
S3
+3.3V_ALW 1U_0603_10V6K~D
2
680P_0603_50V7K~D
PC299
1
2
3
10
6
@ PR206
+5V_ALW
1
0_0402_5%~D
1
1
PC212
@ @ PR205 1 2
470K_0402_5%~D +1.5VP +1.5VP
2
2
PGOOD_1.5V @ PC218 2
2
2
PR209 22P_0402_50V8J~D PR208
<49> 1.5V_SUS_PWRGD 1M_0402_1%~D 10K_0402_1%~D
@ PR210 1.5V_B+ 1 2
1
0_0402_5%~D
1
1 2 S5_1.5V
<49> DDR_ON
1
@ PC213 @ PR214 +3.3V_ALW
@ PR226 0.1U_0402_16V7K~D 0_0402_5%~D @ PR211
0_0402_5%~D 1 2 S3_1.5V 150K_0402_1%~D
<48> 0.75V_DDR_VTT_ON
2
1
1 2 1 2
<19,48,52> SIO_SLP_S4#
PR213 @
1
10K_0402_5%~D
DMN66D0LDW-7 2N SOT363-6
+3.3V_ALW @ PQ204A PR215
2
10K_0402_1%~D
PR216 @ 2
2
1
10K_0402_5%~D
10K_0402_5%~D
0.01U_0402_25V7K~D
1
Mode DDR_ON 0.75V_DDR_VTT_ON +1.5VP +0.75VSP +V_DDR_REF @
1
S0 H H on on on
75K_0402_1%~D
PC214
PR219 @ @ PQ204B @
2
S3 H L on off on
PR217
10K_0402_5%~D
PR218
S4 L L off off off 1 2 5 @
<48> DDR_1.5V_CNTRL0
2
2
1
S5 L L off off off
0.01U_0402_25V7K~D
4
2
1
10K_0402_5%~D
PR220
PC215
Note: S3 - sleep ; S5 - power off
2
@ @
2
3
@ PJP202 3
JUMP_43X118
+1.5VP 1 2
1 2 +1.5V_MEM
DDR GPIO Output Voltage Selection
@ PJP203
JUMP_43X118 DDR_1.5V_CNTRL1 DDR_1.5V_CNTRL0 DDR Vout
1 2
1 2
0 0 1.65V
+3.3V_ALW
0 1 1.6V PR221 @
6
+3.3V_ALW 10K_0402_5%~D
@ PQ205A
PJP205 1 0 1.55V
2
1
+0.75VSP 2 1 +0.75V_DDR_VTT PR222 @ 2
2 1 10K_0402_5%~D
@ JUMP_43X79 1 1 1.5V (Default)
1
3
10K_0402_5%~D
0.01U_0402_25V7K~D
PR223 @ PQ205B
2
10K_0402_5%~D
1
1 2 5
<48> DDR_1.5V_CNTRL1
1
PR224
PC216
0.01U_0402_25V7K~D
4
1
2
1
PC217
@ PR225 @
2
10K_0402_5%~D @
2
@
2
@
4 4

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, +1.5VSP/0.75VSP
A B
WWW.AliSaler.Com NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
C
Size
Date:
Document Number

LA-7931
D
Sheet 55 of 70
Rev
1.0
A B C D
WWW.AliSaler.Com
1.8Volt +/-5%
TDC 0.65A
Peak Current 0.93A
1 1
PR301
2 1 +3.3V_RUN
470K_0402_5%~D
1.8V_RUN_PWRGD <48>
PL301
PU301 PL302
4
HCB1608KF-121T30_0603 1UH_NRS4018T1R0NDGJ_3.2A_30%
+5V_ALW 1 2 1.8VSP_VIN 10 2 1.8VSP_LX 1 2
PG
PVIN LX +1.8V_RUNP
22P_0402_50V8J~D
9 3
PVIN LX
1
4.7_1206_5%~D
@
1
PC302
PC301 8 <Vo=1.8V> VFB=0.6V
SVIN
PR302
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D PR303
Vo=VFB*(1+PR303/PR306)=0.6*(1+20K/10K)=1.8V
22U_0805_6.3VAM~D
6 1.8VSP_FB 20K_0402_1%~D
2
5 FB @
2
EN
1
PC303
PC304
@
NC
NC
TP
PR304
0_0402_5%~D
11
2
SNUB_1.8VSP
1 2 EN_1.8VSP
<35,47,48,52> RUN_ON
1
1
SYN470DBC_DFN10_3X3 PR306
1
@ PR307 @ PR305 @ 10K_0402_1%~D
680P_0603_50V7K~D
2
0_0402_5%~D 47K_0402_5%~D PC305 2
2
1 2 0.1U_0402_16V7K~D
<11,19,35,47,48,52> SIO_SLP_S3#
PC306
@ @
PJP301
1 2
2
+1.8V_RUNP +1.8V_RUN
PAD-OPEN 3x3m
PR308
2 1 +3.3V_ALW
470K_0402_5%~D 1.5Volt +/-5%

1.5V_RUN_PWRGD <48> TDC 0.88 A
Peak Current 1.26 A
3 3
PL303
PU302 PL304
4
HCB1608KF-121T30_0603 1UH_NRS4018T1R0NDGJ_3.2A_30%
+3.3V_ALW 1 2 1.5VSP_VIN 10 2 1.5VSP_LX 1 2
PG
PVIN LX +1.5V_RUNP
22P_0402_50V8J~D
9 3
PVIN LX
1
4.7_1206_5%~D
@
1
1
PC308
PC307 8 <Vo=1.5V> VFB=0.6V
SVIN
PR309
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D PR310
Vo=VFB*(1+PR310/PR313)=0.6*(1+15K/10K)=1.5V
22U_0805_6.3VAM~D
6 1.5VSP_FB 15K_0402_1%~D
2
2
5 FB @
2
2
EN
1
PC310
PC309
NC
NC
TP
@ PR311
0_0402_5%~D
11
2
SNUB_1.5VSP
1 2 EN_1.5VSP
<11,19,35,47,48,52> SIO_SLP_S3#
1
1
SYN470DBC_DFN10_3X3 PR313
1
@ @ PR312 @ 10K_0402_1%~D
680P_0603_50V7K~D
PR314 47K_0402_5%~D PC311
2
0_0402_5%~D 0.1U_0402_16V7K~D
2
1 2
<35,47,48,52> RUN_ON
1
PC312
@ @
PJP302
1 2
2
+1.5V_RUNP +1.5V_RUN
PAD-OPEN 3x3m
4 4
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.8V_RUN
A B
WWW.AliSaler.Com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Size
Date:
Document Number
LA-7931
D
Sheet 56 of 70
Rev
1.0
5 4 3 2 1
WWW.AliSaler.Com @
PJP401
+V1.05SP_B+ 1 2
+PWR_SRC
PAD-OPEN 4x4m
2200P_0402_50V7K~D
0.1U_0402_25V6K~D
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
1
1
5
+3.3V_ALW
PC401
PC402
PC403
PC404
D D
2
470K_0402_5%~D
1
4
PR401
PC405
0.22U_0603_16V7K~D
PR402
1 2 2 1 PQ401
2
2.2_0603_5%~D FDMC8884_POWER33-8-5
3
2
1
PU401
<49> 1.05V_A_PWRGD 1 10 BST_+V1.05SP
PGOOD VBST
PR403
1 2 TRIP_+V1.05SP 2 9 UG_+V1.05SP PL401
TRIP DRVH 1UH_ETQP3W1R0WFN_11.8A_20%
68.1K_0402_1%~D
EN_+V1.05SP 3
EN SW
8 SW_+V1.05SP 1 2 +1.05V_MP
@ PR404
5
0_0402_5%~D FB_+V1.05SP 4 7
<19,48,52> SIO_SLP_A#
1 2 VFB V5IN
+5V_ALW
220U_D2_4VM~D
RF_+V1.05SP 5 6 LG_+V1.05SP PQ402 1
RF DRVL
1
S0 mode be high level @
+
PC406
@ 11 FDMC7692S_POWER33-8-5 PR405
TP
1
PC407 PC408 4 4.7_1206_5%~D
56P_0402_50V8J~D
0.1U_0402_16V7K~D TPS51212DSCR_SON10_3X3 1U_0603_10V6K~D
2
2
2
2
PC499
SNUB_+V1.05SP
1
3
2
1
1
PC409
1
PR406 @ 680P_0603_50V7K~D
470K_0402_5%~D
2
C C
2
PR407
4.99K_0402_1%~D
2 1
+1.05Volt +/- 5%
2
PR408
TDC 4.6 A
10K_0402_1%~D Peak Current 6.7 A
OCP current 8 A
1
PJP402
+1.05V_MP 2
2 1
1 +1.05V_M
@ JUMP_43X118
B B
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.05V_M
WWW.AliSaler.Com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-7931
5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com @ PJP501
+V1.05S_VCCPP_B+ 2 1
2 1 +PWR_SRC
JUMP_43X118
+3.3V_RUN
2200P_0402_50V7K~D
0.1U_0402_25V6K~D
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
1
1
PC501
PC502
PC503
PC504
1
D D
2
5
PR501
470K_0402_5%~D PQ501
FDMC8884_POWER33-8-5
2
PC505
0.22U_0603_16V7K~D 4
<49,59> 1.05V_VTTPWRGD PR502
1 2 2 1
2.2_0603_5%~D
PU501
PR503 1 10 BST_+V1.05S_VCCPP
3
2
1
93.1K_0402_1%~D PGOOD VBST
1 2 TRIP_+V1.05S_VCCPP 2 9 UG_+V1.05S_VCCPP PL501
TRIP DRVH 1UH_ETQP3W1R0WFN_11.8A_20%
@ PR504 EN_+V1.05S_VCCPP 3 8 SW_+V1.05S_VCCPP 1 2
0_0402_5%~D EN SW
+1.05VTTP
1 2 FB_+V1.05S_VCCPP 4 7
<48> CPU_VTT_ON VFB V5IN
+5V_ALW PQ502
330U_2.5V_M
@ RF_+V1.05S_VCCPP 5 6 LG_+V1.05S_VCCPP FDMC7692S_POWER33-8-5 1
RF DRVL
1
1
PC507 @
+
PC508
0.1U_0402_16V7K~D 11 PC506 PR505
TP 1U_0603_10V6K~D 4.7_1206_5%~D
2
TPS51212DSCR_SON10_3X3
PR506 2
2
470K_0402_5%~D 4 SNUB_+V1.05S_VCCPP
56P_0402_50V8J~D
@
1
PC509
2
1
PC599
680P_0603_50V7K~D
PC511
3
2
1
2
C .1U_0402_16V7K~D C
2
@
PR508
@ PR509
4.99K_0402_1%~D 0_0402_5%~D
2 1 1 2
VTT_SENSE <10>
@ PR510
0_0402_5%~D
1 2
VSSIO_SENSE_R <10>
+3.3V_RUN
1
2
@ PR512
1
PR511
10K_0402_1%~D 71.5K_0402_1%~D PR514
10K_0402_5%~D
2
@
1
+1.05Volt +/- 5%
2
D
PQ503
2 From GPIO
TDC 6.6 A
VCCP_PWRCTRL <11>
B G Peak Current 8.5 A B
@
0.1U_0402_16V7K~D
S
3
@ OCP current 10.2 A

VCCP_PWRCTRL = "High" , Vo = 1.05V (SNB)
1
PC510
1
PR515 VCCP_PWRCTRL = "Low" , Vo = 1V (IVB)

10_0402_1%~D
2
2
PJP502
+1.05VTTP 2
2 1
1 +1.05V_RUN_VTT
@ JUMP_43X118
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.05V_RUN_VTT
WWW.AliSaler.Com
5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com VID [0] VID[1] VCCSA Vout

0 0 0.9V
The 1k PD on the VCCSA VIDs are empty. 0 1 0.8V
These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability. 1 0 0.725V
1 1 0.675V
PR601
1K_0402_5%~D
D
2 1 output voltage adjustable network D
+3.3V_RUN @ PR613
0_0402_5%~D
1 2
VCCSA_VID_1 <11>
1
PR602 @ PR614
100K_0402_5%~D 0_0402_5%~D
1 2
VCCSA
VCCSA_VID_0 <11>
@ PR603 TDC 4.2A
2
0_0402_5%~D
<49> VCCSAPWROK
1 2 PR604 Peak Current 6A
1K_0402_5%~D
+VCCSA_PWRGD
2 1 OCP current 7.2A
+5V_ALW
1U_0603_10V6K~D
2
PC601
PR605 @ PR606
10_0402_1%~D 0_0402_5%~D
1
2 1 +VCCSA_EN 1 2
1.05V_VTTPWRGD <49,58>
PC602
2.2U_0603_10V7K~D
1 2
18
17
16
15
14
13
PU601
PC603
V5DRV
V5FILT
VID1
VID0
PGOOD
EN
.1U_0603_16V7K~D
PR607
12 +VCCSA_BT 1 2+VCCSA_BT_1 1 2
19 BST PL601
PGND 2.2_0603_5%~D
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
C
SW
11 +VCCSA_PHASE 1 2 +VCCSA_P C
20
PGND
2200P_0402_50V7K~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
0.1U_0402_25V6K~D
1
10 @
2200P_0402_50V7K~D
0.1U_0402_25V6K~D
21 SW PR608
PGND
2
PC604
PC605
PC606
PC607
PC608
PC609
PC610
PC611
4.7_1206_5%~D
TPS51461RGER_QFN24_4X4~D 9
22 SW +VCCSA_SNUB
1
VIN
1
2
PC612
PC613
@ @
PC614 PC615 8 @
SW
1
@ 10U_0805_25V6K
10U_0805_25V6K 23 PC616
2
+5V_ALW PAD-OPEN 43X118

VIN 680P_0603_50V7K~D
7
2
2 1 +VCCSA_PWR_SRC 24 SW
VIN
PJP601 25
COMP
MODE
TP
SLEW
VOUT
VREF
GND
1
6
@ PR609
2 1
33K_0402_5%~D
PR610
100_0402_5%~D
PC617 2 1
2 1
GNDA_VCCSA
0.22U_0402_10V6K~D PR612
5.1K_0402_1%~D @ PR611
2 1 2 1 0_0402_5%~D
0.01U_0402_25V7K~D 1 2
VCCSA_SENSE <11>
PC618 2
3300P_0402_50V7K~D
PC619
B B
@
PJP602
1 2
+VCCSA_P +VCC_SA
PAD-OPEN 4x4m
@
PJP603
2 1
PAD-OPEN1x1m
GNDA_VCCSA
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +VCC_SA
WWW.AliSaler.Com
5 4 3 2 1
5 4 3 2 1
PR701 PC701
WWW.AliSaler.Com PR702
2K_0402_1%
2 1
330P_0402_50V7K~D
2 1
PC702
VCC_core
TDC 75 A
2 1 2 1 2 1
Peak Current 97A
169K_0402_1%~D
PC703 4.32K_0402_1%~D PR703 150P_0402_50V8F~D
1
OCP current 116A
PR705
2 1 267K_0402_1%
<11> VCC_AXG_SENSE PR704 PC704 PC705
330P_0402_50V7K~D 2 1 2 1 1 2 Load line 1.9
<11> VSS_AXG_SENSE PC706 499_0402_1%~D 470P_0402_50V7K~D 68P_0402_50V8J~D
2
1 2
0.01U_0402_50V7K
D D
<61> VSUMG+ +5V_ALW

2.61K_0402_1%
@ PR707
0.1U_0402_10V7K~D
1
1 2 IMVP_PWRGD
PR706
1U_0603_10V6K~D
0.015U_0402_16V7K
0.1U_0402_10V7K~D
1
11K_0402_1%
0_0402_5%~D PR711
1
PC710
0_0603_5%~D
2 1
1
1
PR708
PC707
PC709
PR709 2.2_0603_5%~D
10KB_0402_5%_ERTJ0ER103J
+VCC_PWR_SRC
1 2
2
@ PR710
BOOT3
2
649_0402_1%~D PWMG2 <61> HCB4532VF-800T90_2P
2
2
+PWR_SRC
2200P_0402_50V7K~D
1 2 PC712 PL710
0.1U_0603_25V7K~D
2
2
PH701
LGATE1G <61> 0.22U_0603_16V7K~D +VCC_PWR_SRC 1 2
1
1
PC708
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
@ PC711
PR712 3300P_0402_50V7K~D PHASE1G <61> PU701
2
453_0402_1%~D 6 1 UGATE3
2
VCC UGATE
PGOODG
1
PC713
PC714
PC715
PC716
PC717
<61> VSUMG- 1 2 UGATE1G <61> PQ702
7 2 CSD87351Q5D_SON8~D
FCCM BOOT
1
.1U_0402_16V7K~D
BOOT1G <61>
2
1
<61> ISEN1G 3 8 PHASE3 UGATE32 @

PWM PHASE
PC718
PC719 PWM3_1
2 1 4 5 LGATE3
2
9 GND LGATE 7
40
39
38
37
36
35
34
33
32
31
0.22U_0402_16V7K~D PU702 BOOT2 TP PQ701 PHASE3 3 6 PL701
<61> VSUMG- <61> ISEN2G
2
PC720 ISL6208BCRZ-T_QFN8_2X2 CSD87351Q5D_SON8~D 5 0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
ISUMNG
RTNG
FBG
COMPG
PGOODG
PWM2G
LGATE1G
PHASE1G
UGATE1G
BOOT1G
+VCC_CORE
1
2 1 UGATE2 PR713 4
LGATE3 2 1
PR714 0_0402_5%~D 2
1 2 2 1
PC721 4.7_1206_5%~D
0.22U_0402_16V7K~D PHASE2 @ @ PR719
1
PR721
PH702 @ PR720 1 30 @ PR715 PR716 2 1ISEN1
ISUMPG BOOT2 +5V_ALW
2
3.83K_0402_1% 470K_0402_5%_ TSM0B474J4702RE 1 2 ISEN1G 2 29 LGATE2 0_0402_5%~D 7 ISEN3 1 2 10K_0402_1%~D
+5V_ALW
8
ISEN1G UGATE2
680P_0603_50V7K~D
0_0402_5%~D ISEN2G 3 28 1 2 3 6 PC791 10K_0603_1%~D
2 PR7171 NTCG 4 ISEN2G PHASE2 27 PR718 5 56P_0402_50V8J~D
1
C
27.4K_0402_1% SCLK 5 NTCG LGATE2 26 VCCP 1 2 4 P3_SNUB P3_SW @ PR723 C
@
1 2
1 2 ALERT# 6 SCLK VCCP 25 PR724 2 1ISEN2
<10> VIDSCLK ALERT# VDD
@ PR722 0_0402_5%~D 7 24 PWM3 0_0603_5%~D VSUM+ 1 2 10K_0402_1%~D
SDA PWM3
2
<10> VIDALERT_N 1 2 8 23 PR726 3.65K_0603_1%
@ PR725 0_0402_5%~D VR_EN 9 VR_HOT# LGATE1 22 LGATE1 2 1 PC792
2
1 2 SDA NTC 10 VR_ON PHASE1 21 PR728
<10> VIDSOUT 56P_0402_50V8J~D
1
NTC UGATE1
ISEN3/FB2
PC722
PC723
2 1
1U_0603_10V6K~D
1U_0603_10V6K~D
@ PR727 0_0402_5%~D PHASE1 1_0402_1%~D @ VSUM-
1 2 VR_HOT# 1_0402_5%
PGOOD
BOOT1
ISUMN
ISUMP
1
COMP
ISEN2
ISEN1
@ PR729 0_0402_5%~D UGATE1
RTN
@ PR730 0_0402_5%~D 41
FB
<48> IMVP_VR_ON 1 2 TP
<7,26,49,62> H_PROCHOT#
2
+VCC_PWR_SRC
11
12
13
14
15
16
17
18
19
20
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K~D
1 2 ISL95836HRTZ-T_TQFN40_5X5~D
0.1U_0603_25V7K~D
<17,49> 1.05V_0.8V_PWROK 1 1 1
+1.05V_RUN_VTT
100U_25V_M~D
100U_25V_M~D
100U_25V_M~D
@ PR732
+ + +
PC724
PC725
PC726
1 2 @ PR731 0_0402_5%~D BOOT1
PGOOD
1
PC727
PC728
PC729
PC731
PC730
COMP
PR733 PQ704
43P_0402_50V8J
0_0402_5%~D 1 2 2 1 @ PR734 CSD87351Q5D_SON8~D

ISEN3
ISEN2
ISEN1
1
PH703 0_0402_5%~D 2 2 2
2
1
PC732
3.83K_0402_1% 470K_0402_5%_ TSM0B474J4702RE 1 2 IMVP_PWRGD <48> UGATE2 2

UGATE2 @
PR735 PR736 1.91K_0402_1% PQ703

2
27.4K_0402_1% 2 1 CSD87351Q5D_SON8~D 7
+3.3V_RUN
1
2 1 3
PHASE2 6 PL702
2 5 0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
PHASE2 4
LGATE2 2 1
@ +VCC_CORE
7
PC737 4.7_1206_5%~D
PC733 10P_0402_25V8J
1
PR737 54.9_0402_1% COMP 2 1 PR738 3 6
PR739
BOOT2 2 1 1 2 5 PC793
680P_0603_50V7K~D
2 1 SCLK @ PR740 0_0402_5%~D 2.2_0603_5%~D 4 56P_0402_50V8J~D P2_SW
1
1 2 PC734
+5V_ALW PC735 0.22U_0603_16V7K~D
@
PR741 @ PR742
1 2
@ PR743 75_0402_5% PR744 470P_0402_50V7K~D PC736 LGATE2 ISEN21
P2_SNUB 2 2 1ISEN1
2 1 ALERT# 2 1 2 1 2 1 10K_0603_1%~D 10K_0402_1%~D
8
2
B B
PC738 499_0402_1%~D 68P_0402_50V8J~D PC794
2
PR745 130_0402_1% 2 1 56P_0402_50V8J~D PR746 @ PR747
1
2 1 SDA 0.22U_0402_6.3V6K @ 1
VSUM+ 2 2 1 ISEN3
PC739 PR750 3.65K_0603_1% 10K_0402_1%~D
VSUM- 2 1 PR748 PR749 PC741 5.76K_0402_1% PR751
PC740 0.22U_0402_6.3V6K 2 1 2 1 2 1 1 2 VSUM- 2 1
2 1 PC742 1_0402_5%
2 1 3.48K_0402_1%~D 267K_0402_1% 150P_0402_50V8F~D
0.1U_0402_25V6K~D 0.22U_0402_6.3V6K PR752 PC743 +VCC_PWR_SRC
2200P_0402_50V7K~D
10U_0805_25V6K
10U_0805_25V6K
2K_0402_1% 680P_0402_50V7K~D
0.1U_0603_25V7K~D
1 2 1 2
10U_0805_25V6K
1
1
PC744
PC745
PC746
PC747
PC748
PQ706
VSUM+ CSD87351Q5D_SON8~D
1
0.01U_0402_25V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
11K_0402_1%
2.61K_0402_1%
@ UGATE1 2
UGATE1 @
PC749
1
PR753
1 2
10KB_0402_5%_ERTJ0ER103J
PQ705 7
VCCSENSE <10>
1
330P_0402_50V7K CSD87351Q5D_SON8~D 3
PHASE1 6 PL703
1
5 0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
VSSSENSE <10>
12
1 2 PHASE1 2 4
LGATE1 2 1
PC750 2
+VCC_CORE
PR754
PH704
PC751
PC752
PC757 4.7_1206_5%~D
PC753 0.01U_0402_50V7K
2
1
PR755 7
PR756
PR757 BOOT1 2 1 1 2 3 6 PC795 P1_SW
2
680P_0603_50V7K~D
VSUM- 2 1 2.2_0603_5%~D 5 56P_0402_50V8J~D
1
604_0402_1% LGATE1 PC754 4 @
0.22U_0603_16V7K~D P1_SNUB PR758 @ PR759
1 2
@ ISEN11 2 2 1 ISEN2
.1U_0402_16V7K~D
PC756
1
@ PR760 10K_0603_1%~D 10K_0402_1%~D

PC755
1 2 1 2 PC796
8
56P_0402_50V8J~D
2
2
649_0402_1%~D 2200P_0402_25V7K~D @ @ PR762
A A
VSUM+1 PR761 2 2 1 ISEN3
3.65K_0603_1% 10K_0402_1%~D
PR763
VSUM- 2 1
1_0402_5%
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +VCC_CORE
5 4
WWW.AliSaler.Com
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
3 2
Size
Date:
Document Number
LA-7931
1
Sheet 60 of 70
Rev
1.0
5 4 3 2 1
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VCC_GFXCORE
TDC 38A
Peak Current 46A
OCP current 57.18A
Load line 3.9
D D
+VCC_PWR_SRC
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
10U_0805_25V6K
10U_0805_25V6K
1
1
+5V_ALW
PC761
PC762
PC758
PC759
2
2
1U_0603_10V6K~D
1
1
PC763
0_0603_5%~D
PQ707
PR776
UGATE2G CSD87351Q5D_SON8~D
1
2 2
2
PL704
7 0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
PU703 PR764 4.7_0603_5%~D 3 6 2 1
6
VCC UGATE
1 5 +VCC_GFXCORE
<60> PWMG2 2 1 1 2 4 GP2_SW
7 2 BOOT2G
4.7_1206_5%~D
FCCM BOOT
3.65K_0603_1%
PC764
1
PR765
3 8 PHASE2G
10K_0603_1%~D
PWM PHASE
PR766
PR767
0.22U_0603_16V7K~D
8
4 5 LGATE2G PR768 1_0402_5%
9 GND LGATE GP2_SNUB 2 1 VSUMG- <60>
1 2
TP
680P_0603_50V7K~D
2
2
PC765
ISL6208BCRZ-T_QFN8_2X2 PC797 VSUMG+ <60> PR769 10K_0402_1%~D
56P_0402_50V8J~D 1 2 ISEN1G <60>
2
@ ISEN2G <60>
C C
+VCC_PWR_SRC
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
1
1
PC766
PC767
PC769
PC770
PQ708
2
2
<60> UGATE1G CSD87351Q5D_SON8~D
1
PL705
7 0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
<60> PHASE1G 3 6 2 1 +VCC_GFXCORE
5
2
4 GP1_SW
PC771
B B
0.22U_0603_16V7K~D
1 1
3.65K_0603_1%
10K_0603_1%~D
2
10K_0402_1%~D
PC798
4.7_1206_5%~D
8
1_0402_5%
PR771
PR772
PR773
PR774
PR775 2 1
PR770
4.7_0603_5%~D
680P_0603_50V7K~D
56P_0402_50V8J~D
2
1
@ GP1_SNUB
<60> BOOT1G
1 2
ISEN2G <60>
VSUMG+ <60>
PC772
VSUMG- <60>
2
<60> ISEN1G
<60> LGATE1G
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D +VCC_GFXCORE
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DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1.0
LA-7931
Date: Sheet 61 of 70
5 4 3 2 1
5 4 3 2 1
@ PD901 ES2AA-13-F
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PQ901 SI7149DP
1 Iada=0~9.23A(180W)
PR901
<26>
+SDC_IN +PWR_SRC +CHAGER_SRC
EMC1700_SENSE_P
0.01_2512_1%~D PL901
1 1UH_PCMB053T-1R0MS_7A_20%
2 1 4 2 1
+DC_IN_SS 5 3
0.1U_0603_25V7K~D
2 3
0.1U_0603_25V7K~D
@
47P_0402_50V8J~D
1
1
PC902
PC903
<26> EMC1700_SENSE_N
PC901
@ PR902
0_0402_5%~D @ PR903
2
1
1 2 0_0402_5%~D D @
DC_BLOCK_GC <63>
1 2 2 PQ902
<63> CSS_GC
G NTR4502PT1G_SOT23-3~D
1
D S
3
D D
2 PQ904A
G SI3993CD
PQ903 S
PD902
S
E2 AC_OK=17.7 Volt NTR4502PT1G_SOT23-3~D 5 6
D
DOCK_DCIN_IS+ <46>
+DOCK_PWR_BAR 2
CSSN_1
CSSP_1
PR913 1
G
1
PQ904B
TI bq24745 = 316K 3 PR904 SI3993CD
+DC_IN_SS
PR905 11@
Intersil ISL88731 = 226K
10_0402_5%~D
10_0402_5%~D
100K_0402_5%~D
100K_0402_1%~D
S
2 1 2 4
D
Maxim = 383K BAT54CW_SOT323~D
1
PR906
PR907
100K_0402_1%~D
1
1
11@
G
3
+SDC_IN
DOCK_DCIN_IS- <46>
PR908
MAX8731A_LDO MAX8731_REF PC904 11@ PC905 11@
10K_0402_1%~D
10K_0402_5%~D
@ PR909 0.1U_0402_25V6K~D 0.047U_0402_25V7K~D PC906 @ PR910
2
<63> +CHGR_DC_IN 1 2 1 2 1 2 1 2 0_0402_5%~D
2
1
1
22@ PR912 1 2
226K_0402_1%~D
DK_CSS_GC <63>
11@ PR911
1_0805_5%~D 0.1U_0402_25V6K~D
2
11@
PR913
GNDA_CHG
28
27
1
PC907 GNDA_CHG PU901 ICOUT
2
0.1U_0805_50V7M~D 11@ PR918
1U_0603_10V6K~D
CSSP
ICREF
CSSN
PR914 2 1 +DCIN 22 26 4.7_0603_5%~D
1
DCIN ICOUT
11@ PC908
49.9K_0402_1%~D PR917
1
2 1 @ PR915 2 2.2_0603_1%~D
BAT54HT1G_SOD323-2~D
0_0402_5%~D ACIN 25 1
BOOT 2 BOOT_D
1 2 13 BOOT
15.8K_0402_1%~D
PC909
2
<16,25,49,63> ACAV_IN ACOK
1
PC910
22@ PD903
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
1
1
1
2 1 11
VDDSMB
5
11@
PR916
1
PC912
PC913
PC914
PC915
0.01U_0402_25V7K~D 10 GNDA_CHG PQ905
2
SCL PC911
2
GNDA_CHG +5V_ALW 9 21 MAX8731A_LDO 1 2 SIR472DP-T1-GE3_POWERPAK8-5
2
2
SDA VDDP
GNDA_CHG 14 1U_0603_10V6K~D 4
NC 24 CHG_UGATE
C C
MAX8731_IINP 8 UGATE 11@ PR919
VICM
1
23 2 1 +VCHGR_B
PC916 6 PHASE 0_0603_5%~D
3300P_0402_50V7K~D
3
2
1
FBO
1
0.1U_0402_10V7K~D
2
1 2 5 @ PC917
22@ PC918 22@ PR921 EAI 220P_0402_50V7K~D
1
GNDA_CHG 22@ PR920 2 1 1 2 4 20 CHG_LGATE
4.7K_0402_5%~D
EAO LGATE +VCHGR
PC919
56P_0402_50V8~D
<49> CHARGER_SMBCLK 200K_0402_5%~D 7.5K_0402_5%~D PR923

1
22@ PC920
2200P_0402_50V7K~D PL902 0.01_1206_1%~D
2
PR922
<49> CHARGER_SMBDAT 5.6UH_FDVE1040-H-5R6M-P3_9.2A_20%~D

2
MAX8731_REF 3 19 @ 2 1+VCHGR_L
4 1
VREF PGND 18
22@ PC921 22@ PR924 CSOP PQ906 3 2
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
SI7716ADN-T1-GE3_POWERPAK8-5
2
<25> MAX8731_IINP
PC930
120P_0402_50VNPO~D 1 2 7 17 PR929
0.1U_0603_25V7K~D
CE CSON
11@ PR927
10_0402_5%~D
1 2 10K_0402_5%~D 4.7_1206_5%~D
8.45K_0402_1%~D
220P_0402_50V8J~D
1
1
0_0402_5%
PC931
PC932
15 VFB 1 PR926 2
0.1U_0402_10V7K~D
VFB +VCHGR
1
1
PR925
22@ PC922
PR928
12
1U_0603_10V6K~D
Vref
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
GND
1
PC929
16 100_0402_5%~D CHG_SNUB
TI bq24747 = 3.3V
1 1
2
NC
1
1
11@ PC923
PC926
11@ PC927
22@ PC924
PC928
29 4
2
2
TP
Intersil ISL88731C = 3.2V @ @
56P_0402_50V8J~D
2
2
VDDP
2
2
PC999
@ @ ISL88731C_QFN28_5X5~D PC925
2
TI bq24747 = 6V 11@ PJP902 1000P_0603_50V7K~D
3
2
1
1 2 22@ PC933
Intersil ISL88731C = 5.1V
1
@ 0.1U_0402_25V6K~D
1 2 1 2 1 2
PAD-OPEN1x1m PC934
GNDA_CHG 0.22U_0603_25V7K~D PC935
GNDA_CHG 11@ @ 0.1U_0402_25V6K~D
Maximum charging current is 7.2A GNDA_CHG
GNDA_CHG
MAX8731_REF
+5V_ALW
+DC_IN MAX8731_REF
100P_0402_50V8J~D
0.01U_0402_25V7K~D
10K_0402_1%~D
DYN_TUR_CURRENT_SET# PR930
232K_0402_1%~D
47K_0402_1%~D
1M_0402_1%~D
1
1
PC936
PC937
1 2
221K_0402_1%~D
H_PROCHOT# <7,26,49,60>
2
B B
PR931
PR932
PR933
PR934
+5V_ALW
150W High
2
+3.3V_ALW2 @ @
+5V_ALW PR936 PR935
2
1.8M_0402_1% 0_0402_5%~D
1
8
1 2 PU902A @ PR938
180W Low @
1
3 0_0402_5%~D
P
+
1
PR937 1 1 2
100K_0402_1%~D PR939 2 O ACAV_IN_NB <48,49,63>
100P_0402_50V8J~D
22.6K_0402_1%~D
42.2K_0402_1%~D
41.2K_0402_1%~D
DMN66D0LDW-7 2N_SOT363-6~D
-
8
G
20K_0402_1%~D PU902B
100P_0402_50V8J~D
DMN66D0LDW-7 2N_SOT363-6~D
6
1
PQ908B
MAX8731_IINP 1 2 5 LM393DR_SO8~D
P
2
4
+
1
PQ908A
PC938
PR940
PR941
PC939
PR942
7
6 O 5
-
G
2
220P_0402_50V8J~D
2
LM393DR_SO8~D @
4
2
1
287K_0402_1%
PC940
SSM3K7002FU_SC70-3~D 121K_0402_1%~D
+3.3V_ALW
100P_0402_50V8J~D
1
2
1
PR943
PR944
PC941
1
2
PR945
+3.3V_ALW 100K_0402_5%~D
1
D
PQ909
PC942
9> DYN_TUR_CURRNT_SET# 2 0.1U_0402_25V4Z~D
2
G
S 2 1
3
PU903
1
D
PQ910
1
P
4 B 2
O ACAV_IN <16,25,49,63>
2 G
A PROCHOT_GATE <48>
G
3
To preset system to throtlle
Adapter Protection Circuit for Turbo Mode
3
74AHC1G08GW AND~D switching from AC to DC

A A
PU901 22@ PR913 22@ PC934 22@ PR927 22@ PR905 22@ PR906 22@ PC905 22@ PR919 22@
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Charger
WWW.AliSaler.Com
BQ24747 316k_0402_1% 0.1U_0603_25V6 0_0402_5% 0_0402_5% 0_0402_5% 0.1U_0402_25V6 1 +-5% 0603 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
5 4 3 2 1
5 4 3 2 1
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PD1001
1
3
PDS5100H-13_POWERDI5-3~D
PQ907 SI7149DP
+DOCK_PWR_BAR 1
2
5 3
0.47U_0805_25V7K~D
D D
4
1
PC1001
PR1001
330K_0402_5%~D
2
PR1002 @
2
0_0402_5%~D
2 1 STSTART_DCBLOCK_GC
PD1002
2
1
PR1003 3
330K_0402_5%~D
PDS5100H-13_POWERDI5-3~D
1 2 PQ1004 SI7149DP
PQ1002 PBATT+ SI7149DP PQ1003
SI4835DDY-T1-E3_SO8~D 1
8 1 1 2
7 2 2 PBATT_IN_SS 5 3
+VCHGR +PWR_SRC
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
6 3 3 5
1
1K_1206_5%~D
5 PR1004 @
PR1005
0_0402_5%~D
1
PC1002
PC1003
2 1
4
4
C @ PR1006 C
2
1
1U_0603_25V6-K~D
0_0402_5%~D PC1004
1 2 BLK_MOSFET_GC 1U_0805_25V4Z~D
PC1005
2
2
@ PR1007
1
0_0402_5%~D PR1008 @
+DOCK_PWR_BAR 1 2 DK_PWR_BAR 0_0402_5%~D 0_0402_5%~D
@ PR1009
1 2 3301_DC_IN_SS
+DC_IN_SS
DSCHRG_MOSFET_GC
1
@ PR1010 0_0402_5%~D
2
<62> +CHGR_DC_IN
+DC_IN 1 2 CD3301_DCIN
PR1011 47_0805_5%~D
1
PC1006
0.1U_0603_50V4Z~D @
PR1012
2
0_0402_5%~D
P50ALW 1 2
36
35
34
33
32
31
30
29
28
<53> SOFT_START_GC +5V_ALW

PU1001 @ PR1016
PR1013 100K_0402_5%~D 0_0402_5%~D
GPIO Input from NB
NC
DC_IN_SS
GND
NC
DSCHRG_MOSFET_GC
CHARGERVR_DCIN
DK_PWRBAR
BLK_MOSFET_GC
PBatt+
+3.3V_ALW2 1 2 CD_PBATT_OFF 1 2
B SLICE_BAT_ON <48> B
@ PR1017 @ PR1014
1
0_0402_5%~D
2 ACAVDK_SRC
0_0402_5%~D
1 2
Embedded Controller
<46> ACAV_DOCK_SRC# DOCK_AC_OFF <46,48>
1 27
2 DC_IN P50ALW 26 @ PR1019 1 2
1 2 ERC1 3 SS_GC PBATT_OFF 25 DK_AC_OFF 0_0402_5%~D
+SDC_IN ERC1 DK_AC_OFF_EN 1M_0402_5%~D
4 24 3301_ACAV_IN_NB 1 2
ACAVDK_SRC ACAV_IN_NB ACAV_IN_NB <48,49,62> PR1018
@ PR1015 0_0402_5%~D 5 23
CD3301_SDC_IN 6 GND GND 22 DK_AC_OFF_EN 1 2
SDC_IN DK_AC_OFF_EN DOCK_AC_OFF_EC <48>
7 21 SL_BAT_PRES# @ PR1020 0_0402_5%~D
<62> DC_BLOCK_GC ACAVIN 8 DC_BLK_GC SL_BAT_PRES# 20 BLKNG_MOSFET_GC
@ PR1021 P33ALW2 9 ACAV_IN BLKNG_MOSFET_GC 19
P33ALW2 NBDK_DCINSS
EN_DK_PWRBAR
1 2 @
PR1023
<16,25,49,62> ACAV_IN
SS_DCBLK_GC
0_0402_5%~D 0_0402_5%~D
DK_CSS_GC
1 2
SLICE_BAT_PRES# <46,48,53>
PWR_SRC
@ PR1022 @ PR1024
CSS_GC
P33ALW
0_0402_5%~D 37 0_0402_5%~D
TP
ERC3
ERC2
1 2 1 2
GND
+3.3V_ALW2 +NBDOCK_DC_IN_SS
CD3301ARHHR
10
11
12
13
14
15
16
17
18
@ PR1025
<62> CSS_GC
0.1U_0603_25V7K~D
0_0402_5%~D
P33ALW 1 2
ERC2
<62> DK_CSS_GC +3.3V_ALW

1
PC1007
ERC3 @ PR1027
0_0402_5%~D
0.047U_0603_25V7K~D
EN_DK_PWRBAR 1 2
EN_DOCK_PWR_BAR <48>
2
0.1U_0402_25V4Z~D
1 2
PC1008
1M_0402_5%~D
PC1009
STSTART_DCBLOCK_GC
A @ PR1029 @ PR1028 A
0_0402_5%~D
2
@ 3301_PWRSRC 1 2
+PWR_SRC
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Selector
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7931
5 4 3 2 1
5 4 3 2 1
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+VCC_CORE
+VCC_CORE +VCC_GFXCORE Below is 458544_CRV_PDDG_0.5 Table 5-8.
1 1 1 1 1
5 x 22 µF (0805)
PC1101 PC1102 @ PC1148 PC1104 PC1105
Socket Bottom 5 x (0805) no-stuff
2
10U_0805_6.3VAM~D
2
10U_0805_6.3VAM~D
2
10U_0805_6.3VAM~D
2
10U_0805_6.3VAM~D
2
10U_0805_6.3VAM~D
+VCC_GFXCORE sites
D
7 x 22 µF (0805) D
Socket Top 2 x (0805) no-stuff
sites
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1 1 1 1 1 1 1 1 1 1 1 1 1 @
PC1112
PC1113
PC1114
PC1115
PC1116
PC1117
PC1118
PC1106 PC1107 PC1108 PC1109 PC1110 PC1111
10U_0805_6.3VAM~D 10U_0805_6.3VAM~D 10U_0805_6.3VAM~D 10U_0805_6.3VAM~D 10U_0805_6.3VAM~D 10U_0805_6.3VAM~D
2 2 2 2 2 2 2 2 2 2 2 2 2
+1.05V_RUN_VTT
+VCC_CORE
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1 1 1 @1 @1 @1 1 1 1 1 1
@
2
PC1125
PC1126
PC1127
PC1128
PC1129
PC1130
PC1131
PC1132
PC1133
PC1134
PC1135
PC1120 PC1121 PC1122 PC1123 PC1124
2 2 2 2 2 2 2 2 2 2 2
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D 22U_0805_6.3V6M~D 22U_0805_6.3V6M~D 22U_0805_6.3V6M~D 22U_0805_6.3V6M~D 1 1 1 1 1 1
1
PC1136
PC1137
PC1138
PC1139
PC1140
PC1141
2 2 2 2 2 2
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1 1 1 1 1 1 1 1
@ @
2
PC1149
PC1150
PC1151
PC1152
PC1153
PC1154
PC1155
PC1156
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
PC1144 PC1145 PC1146 PC1147 PC1103 @
2 2 2 2 2 2 2 2
470U_D2_2VM_R4.5M
22U_0805_6.3V6M~D 22U_0805_6.3V6M~D 22U_0805_6.3V6M~D 22U_0805_6.3V6M~D 22U_0805_6.3V6M~D
1
1
1 1 1
@
+ + +
PC1157
PC1158
PC1119
C C
2 2 2
330U_X_2VM_R6M~D
330U_X_2VM_R6M~D
330U_X_2VM_R6M~D
1 1 1
2
PC1166
PC1167
PC1168
+ + +
PC1161 PC1162 PC1163 PC1164 PC1165
22U_0805_6.3V6M~D 22U_0805_6.3V6M~D 22U_0805_6.3V6M~D 22U_0805_6.3V6M~D 22U_0805_6.3V6M~D
1
1
2 2 2
2
PC1169 PC1170
22U_0805_6.3V6M~D 22U_0805_6.3V6M~D
1
+VCC_CORE
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
1 1 1 1
+ + + +
PC1173
PC1174
PC1175
PC1176
B 2 2 2 2 B
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
1@ 1@
+ +
PC1177
PC1178
2 2
A A
Title
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Request
I tem Page# Title Date Owner I ssueDescription Solution Description Rev.
1 62 PWR 10/11 Intersil Remove Docking current sense voltage division Remove PR946、PR948 and PR947 X01
2 53 PWR 10/14 Compal Change RTC battery connector Change to SP02000RO00 X01
D D
3 53 PWR 10/14 Compal Add control singnal to control S5 power consumption Add PR23 to connect PCH_ALW_ON singal X01
4 62 PWR 10/14 Compal Change H_PROCHOT# voltage source of Compare reference PR937 connect to 2VREF_6182 X01
5 53 PWR 10/25 Compal Change PQ5 Package for layout space Change footprint from TO252 to SO8_5P X01
6 60 PWR 11/01 Compal Change PC707 PC751 footprint from 0603 to 0402 Change PC707 PC751 footprint to 0402 X01
7 61 PWR 11/01 Compal Remove PJP702 Remove PJP702 X01
8 54,55,57,58 PWR 11/07 Compal Low side MOSFET Gate induce voltage Reserve PC198,PC199,PC299,PC499,PC599,PC791,PC792, X01
,60,61,62 PC793,PC794,PC795,PC796,PC797,PC798,PC999
9 53 PWR 11/07 Compal Reserve 10u and 0.1u Cap with MXM_pwr_src Reserve PC30 and PC31 X01
10 53 PWR 03/01 Compal Reserve PD7 for ESD requirement Reserve PD7 X03
11 53,54,55, PWR 04/03 Compal Change 0 Ω footprint to R0402_0ohm PR1002,PR1004,PR1006,PR1007,PR1008,PR1009,PR1010,PR1012, X06
56,57,58, PR1014,PR1015,PR1016,PR1017,PR1019,PR1020,PR1021,PR1022,
59,59,60, PR1023,PR1024,PR1025,PR1027,PR1029,PR105,PR118,PR206,
61,62,63 PR214,PR226,PR23,PR307,PR311,PR404,PR504,PR509,PR510,PR6,
PR603,PR606,PR611,PR613,PR614,PR713,PR722,PR725,PR727,
PR729,PR731,PR734,PR902,PR903,PR910,PR915,PR935,PR938
12 59 PWR 04/03 Compal Change PL601 Footprint for DFB issue Change PL601 footrpint to TAI-T_VMPI0703AR-1R0M-Z01_2P X06
C C
13 53 PWR 04/03 Compal Battery ESD protect with ESD diodie PD3.3 connect with PBATT1.7 X06
14 54,62 PWR 04/03 Compal Remove jump of co-lay with input choke Remove PJP901 and PJP101 X06
15 60 PWR 05/04 Compal Change PL710 Footprint for DFB issue Change PL701 footrpint to KC_FBMA-L11-453215-121LMA90T_2 X07
16 60 PWR 05/14 Compal Change 0 Ω footprint to R0402_0ohm PR928 X07
B B
A A
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Request
1 16 HW 2011/09/01 COMPAL correct MXM LVDS signals. Swap CHA and CHB signals on JMXM1. 0.2(X00)
D D
2 51 HW 2011/09/01 COMPAL Add current limilt R for Breath LED. Add R956(374ohm). 0.2(X00)
Move D33,C702,CE6 from JDOCK1.146~148 to JDOCK1.149~151.
3 46 HW 2011/09/04 COMPAL for layout routing easy. JDOCK1.146~148 change to dummy pin. 0.2(X00)
Change R934,R939,R942,R955,R941 from 2.2kohm to 1.2kohm.

4 51 HW 2011/09/06 Lite-on to meet LED min workable current(2mA). R943 from 2.2kohm to 374ohm. 0.2(X00)
5 27 HW 2011/09/06 COMPAL Add MXM DDC signals pull up R. pop R1121,R1122. 0.2(X00)
6 45 HW 2011/09/09 COMPAL Add DOCK DP DDC signals control circuit. Add R2144~R2157,C1331,C1332,Q333~Q336,R2161~R2164,Q337. 0.3(X01)
modify JUSH1 pin define for meeting USH/B JUSH1 pin
7 41 HW 2011/09/14 COMPAL define change. change JUSH1 pin define. 0.3(X01)
8 50 HW 2011/09/19 COMPAL modify JBT1 pin define for meeting BT connector change. Swap JBT1 pin1~pin12 pin define to pin12~pin1. 0.3(X01)
9 46,28,50 ME 2011/09/27 COMPAL Change connector follow connector list 0913A. Change JDOCK1 to WD2F144WB5R400,JLVDS1 to 50398-04071-001,JBT1 to 0.3(X01)
50450-0127N-001.
10 52 HW 2011/09/27 COMPAL +3.3V_RUN boot leakage. Pop R929,Q69. 0.3(X01)
C
11 20,48,28 HW 2011/09/28 DELL Drop touch panel. Remove net "USBP13-,USBP13+,TOUCH_SCREEN_PD#" and L11,R429,R430,D86,R419, 0.3(X01) C
JTS1.
12 46 HW 2011/09/28 COMPAL Add pull-down R for DPC_GPU_HPD. Add R773(100K ohm). 0.3(X01)
2011/09/29 COMPAL Change the R518 value to meet the PS8336B input Change R518 from 100k to 10kohm. 0.3(X01)
13 34 HW high-level voltage.
14 52 HW 2011/09/29 COMPAL Solve S4/S5 +MXM_PWR_SRC leakage in DC mode. Change R940 pin1 connect from +PWR_SRC_S to +PWR_SRC_MXM. 0.3(X01)
Change C743,C741 from 22pF to 39pF, CH2,CH3 from 15pF to 18pF,
15 49,17,18 HW 2011/10/04 COMPAL Crystal EA. CH18,CH19 from 12pF to 10pF. 0.3(X01)
16 17 HW 2011/10/12 COMPAL Debug component control for pop them until ST. Add JTAG@ for RH288,RH59,RH44,RH45,RH43,RH47~RH49. 0.3(X01)
Wireless switch needs to be pulled to ALW, Without it
17 48 HW 2011/10/12 COMPAL being pulled to ALW rail AOAC will work incorrect. Add R2158 let WIRELESS_ON#/OFF pull up to ALW, no stuff R766 0.3(X01)
Solve Breath LED flicker when AC-in plug and correct Add Q327 and use"MASK_BASE_LEDS#" to control Breath LED top view.
18 51 HW 2011/10/12 COMPAL Breath LED top and side view work behavior. use"SYS_LED_MASK#" to control Breath LED side view. 0.3(X01)
JLVDS1 connector change,then GND shield shift(different JLVDS2 pin41,42 change to EDP_LVDS_A3-,EDP_LVDS_A3+, pin43~pin46 change
19 28 HW 2011/10/12 COMPAL from original).because JLVDS1 and JLVDS2 co-lay,we need to GND. 0.3(X01)
change pin define.
20 34 HW 2011/10/12 COMPAL Choice DDC active buffer mode.and control switching Mode. Pop R68 and non-pop R58. 0.3(X01)
B
To meet intel spec: T235(power off)= min 40ns). change U4 from RT9801AGE to RT9818A-44GU3,R1622 to 100kohm.add R2159. B
21 50 HW 2011/10/13 COMPAL T08a(power on)= max 90ms. remove R2129~R2134. pop R2142 and non-pop R1623. 0.3(X01)
22 14 ME 2011/10/13 COMPAL Change connector follow connector list 1005A. Change JDIMM3 to 2-2013310-1. 0.3(X01)
23 38 HW 2011/10/19 COMPAL LAN EA. Change T156 to SP050006P0L. 0.3(X01)
24 22 HW 2011/10/19 COMPAL for solving dispaly ripples. 1/2 Change LH1 to 4.7uH inductor. 0.3(X01)
25 40 HW 2011/10/25 COMPAL NEC_TOKIN shortage issue for the flood in Tailand. Change C323,C324 to SGA0000370L(Panasonic). 0.3(X01)
26 34 HW 2011/10/25 COMPAL HDMI EA. pop R451~R456,R458,R459 and non-pop L19,L23,L24,L25. 0.3(X01)
27 51 HW 2011/10/25 COMPAL improve BT_LED behaviour abnormal(BT_LED must dark) change R938 PU from +3.3V_RUN to +3.3V_ALW. 0.3(X01)
in S3/S4/S5.
28 38,51 HW 2011/10/26 COMPAL for ESD Hi-Pot fail. change JLOM1 "pin14 and pin15" from "GND_CHASSIS1 and GND_CHASSIS" to GND. 0.3(X01)
change H5 to NPTH.
29 41 HW 2011/10/26 COMPAL TPM chip to new version chip due to OS Win8 supported 0.3(X01)
problem Change U39 TPM solution to new p/n: SA00004WQ10
30 51 ME 2011/10/26 COMPAL screw hole change follow 1021A ME drawing. Change H5 to 3P2X6P2 and H18,H19,H23,H24 to 4P1. 0.3(X01)
31 51 HW 2011/10/28 COMPAL Solve Breath LED flicker when AC-in plug,follow E4 Remove Q327 and modify EC code from PWM Output to GPIO input on ECE5048 0.3(X01)
solution. (GPIOM3/PWM4).
32 52 HW 2011/10/28 COMPAL For Inrush current issue. Change C1274 from 470pF to 2200pF for meeting OCP.
A
0.3(X01) A
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Request
Change C767 from 4700pF to 470pF for turning proper +3.3V_SUS timing
33 52 HW 2011/10/28 COMPAL For smart card detect issue. begin to +3.3V_RUN. 0.3(X01)
D D
Change CD45 from 0603 size to 0402 for easy move to keep away battery
34 14 HW 2011/10/28 COMPAL For DFX issue. connector. 0.3(X01)
Change D97,D33,D91,D92 to non-pop. D14,D16 change main source(SC30000250L)
35 47,46,32 HW 2011/10/28 COMPAL For ESD request. to SC300002F0L and D88,D89 change main source(SCA00000T0L) to SC300002F0L. 0.3(X01)
40,29
36 46 HW 2011/10/31 COMPAL EMI request,add 33ohm for DOCK DVI signals. Add R2160,R2165~R2179(33ohm) for DOCK DVI port A,B. 0.3(X01)
37 34 HW 2011/10/31 COMPAL EMI request,add reserve C(3.3pF) for HDMI signals. Add reserve C1333~C1340(3.3pF) for HDMI signals. 0.3(X01)
38 21 HW 2011/11/2 COMPAL PCH has internal pull up 20k ohm on (GPIO27) No stuff RH175 0.3(X01)
39 21 HW 2011/11/2 COMPAL Power saving RH362 change from 10K to 100K 0.3(X01)
40 22 HW 2011/11/2 COMPAL for solving dispaly ripples. 2/2 Change CH36 to 22uF_0805 size. 0.3(X01)
41 49 HW 2011/11/2 COMPAL Change board ID to X01 Change R875 to 130K 0.3(X01)
42 52 HW 2011/11/2 COMPAL Power saving R935 change from 20K to 100K 0.3(X01)
43 33,46 HW 2011/11/2 COMPAL reduce layout via. MXM DP lane for Docking direct connect to JDOCK1. 0.3(X01)
44 45 HW 2011/11/3 COMPAL remove double pull low R. remove R2144,R2154. 0.3(X01)
45 16 HW 2011/11/3 COMPAL only 10-bits panel use. change R2095,R2096 to 6@ group. 0.3(X01)
C
46 49 HW 2011/11/3 COMPAL SMBUS EA. change R838,R841 to 2Kohm for rise timing fail. 0.3(X01) C
47 32 LAYOUT 2011/11/7 COMPAL Add TEST point for JCRT PIN11. Add CRT_11 net and test point(T61) for JCRT1.11. 0.3(X01)
48 33 HW 2011/11/7 COMPAL Add space for easy to layout. Remove R2081~R2088 and remove Net DPC_DOCK_LANE_P0~P3,DPC_DOCK_LANE_N0~N3. 0.3(X01)
49 40 HW 2011/11/7 Parade USB3.0 EA fine tune(TX:EQ-->9.5dB,DE-->3.5dB; pop R22,R18,R30,R28 and change R2141 from 4.99kohm to 4.7kohm. 0.3(X01)
RX:EQ-->7.5dB,DE-->5dB).
Vender suggested changed small size from 5.0*3.2mm to Change Y7 from SJ100006R00 to SJ10000CZ0L, C1225 from 10pF to 15pF,
50 30 HW 2011/11/8 H.ELE 3.2*2.5mm. C1226 from 10pF to 12pF. 0.3(X01)
51 30 HW 2011/11/9 compal for satisfy ME space limilt. Change C324 size from D2 to B2. 0.3(X01)
52 46 HW 2011/11/10 COMPAL Just reserve R for EMI team to test DOCK DVI signals. Change R2160,R2165~R2179 to 0ohm for DOCK DVI port A,B. 0.3(X01)
53 40 HW 2011/12/30 COMPAL sourcer request change USB PWR SW from TPS2560 (U45) to G547I2P81U (U642, U643) 0.4(X01)
54 46 EMI 2011/12/30 COMPAL EMI issue. Swap USB signal from port 8 to port 4 on JDOCK1.66 & JDOCK1.68 0.4(X01)
55 42 EMI 2011/12/30 COMPAL EMI issue. Swap USB signal from port 4 to port 8 on JMINI1.36 & JMINI1.38 0.4(X01)
56 35 HW 2011/12/30 COMPAL 2nd source. add R2180 ~ R2184, R2189 ~ R2193 for SATA redriver(U26, U637) 2nd source
and change R1206 from4.99K ohm to 5.1K ohm. 0.4(X01)
B
57 41 HW 2012/01/02 COMPAL Solve +3.3V_RUN Giltch in S5 when AC plugging in. add R2185, R2186, D103 to SP_TPM_LPC_EN. 0.4(X01) B
58 30 HW 2012/01/02 COMPAL Prevent AUX swing overshoot. add R2187, R2188 on AUX signal. 0.4(X01)
59 52 HW 2012/01/02 COMPAL Power sequencing meet 0.7V between +PCH_V5REF_RUN and change C1274 from 2200P to 3300P, and No stuff R2127 0.4(X01)
+3.3V_RUN.
60 34 HW 2012/01/02 COMPAL HDMI no voice issue stuff R58. 0.4(X01)
61 51 HW 2012/01/03 COMPAL Setup Volume mute LED control same as Volume up & down No stuff Q84B 0.4(X01)
62 46 HW 2012/01/03 COMPAL EMI request add 33ohm for DOCK DVI signals. change R2160, R2165 ~ R2179 from 0 ohm to 33 ohm. 0.4(X01)
63 34 HW 2012/01/03 COMPAL EMI request for HDMI. stuff L19, L23, L24, L25, No stuff R451~R456, R458, R459 0.4(X01)
64 32 HW 2012/01/03 COMPAL EMI request for CRT. change CAP from 3.3P to 12P (C12, C13, C21), and stuff. 0.4(X01)
65 28 HW 2012/01/03 COMPAL EMI request for Webcam. stuff L10, No stuff R427, R428 0.4(X01)
66 30,31 HW 2012/01/04 COMPAL RGB panel sequencing issue. change power rail from +3.3V_RUN to+3.3V_AVDD on R2039.1, R2040.1, 0.4(X01)
A R2038.1, C1227.1, U631.3 A
Remove C1269, C1270
add L57
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67 16 HW 2012/01/04 COMPAL Height limitation issue. change cap from SE142106M8L(1206) to SE00000QK0L(0805) 0.4(X01)
D D
68 40 HW 2012/01/05 COMPAL change main source. change main source from SLG55584A to MAX14618 on U2. 0.4(X01)
69 33 HW 2012/01/05 COMPAL Remove DMC function. Remove U14, R329~R335, R337, R338, R342~R345, R2091, R2092, C396, 0.4(X01)
C399~C401, C267, C269, C273~C278.
70 42 HW 2012/01/05 COMPAL Remove DMC function. Remove JMINI1, R493. 0.4(X01)
71 51 ME 2012/01/09 COMPAL update ME drawing. Remove H3. 0.4(X01)
72 40 ME 2012/01/09 COMPAL update ME drawing. change JUSB1, JUSB2 from FOX_UEA111Y1-C5BDA-7H to FOX_UEA111Y1-C1BD1-7H 0.4(X01)
73 17 ME 2012/01/09 COMPAL update ME drawing. change JSPI1 from HRS_FH12-16S-0P5SH(55)~D to TYCO_1-2041070-6~D. 0.4(X01)
74 25 ME 2012/01/09 COMPAL update ME drawing. change JFAN1, JFAN2 from ACES_50228-0047N-001 to ACES_50450-0067N-001. 0.4(X01)
75 30 HW 2012/01/10 COMPAL prevent current leakage. Change Pull up +3.3V_RUN to +3.3V_AVDD on R2036 and R2037. 0.4(X01)
76 49 HW 2012/01/10 COMPAL change Board ID to X02. change R875 to 62K ohm. 0.4(X01)
77 33 HW 2012/01/10 COMPAL prevent material shortage for Thai flood. change material from TC7SET04FU to NC7ST04P5X on U636. 0.4(X01)
C C
78 28 HW 2012/01/10 COMPAL prevent material shortage for Thai flood. change material from TC7SET04FU to M74VHC1GT125DF2G on U3. 0.4(X01)
79 19,20,25, HW 2012/01/10 COMPAL prevent material shortage for Thai flood. change material from TC7SH08FU to 74AHC1G08GW on U7, U10, U15, U50, U58, 0.4(X01)
37,49,50, UC4, UH3.
51
80 35,43 HW 2012/01/10 COMPAL add X76 option for main source and 2nd source of SATA add X761@ on R1201, R1202, R1206, R2136, R2139, R2140. 0.4(X01)
redriver . add X762@ on R2180 ~ R2184, R2189 ~ R2193.
81 25 HW 2012/01/11 COMPAL layout routing swap. change FAN conn from 4 pin to 6 pin, and swap pin 1, pin6 for JFAN1, JFAN2. 0.4(X01)
82 16 HW 2012/01/11 COMPAL For NVDIA request. add R2194, R2195 (No stuff) and pull up to +3.3V_MXM on JMXM1B.268,
JMXM1B.270 0.4(X01)
83 32 HW 2012/01/18 COMPAL EMI request. change CAP to 22P (C20,C22,C23) and 10P (C12, C13, C21), and all stuff. 0.4(X01)
84 46 HW 2012/01/20 COMPAL Solve dock detection issue. change R755 from 100K to 10K. 0.4(X01)
85 49 HW 2012/01/20 COMPAL Avoid material mixture with E3 project 5055 devices. change MEC5055 from SA00003TZ1L to SA00003TZ2L. 0.4(X01)
B
86 11,28,36 HW 2012/01/20 COMPAL Change RC value at Gate of MOS Load SW to modify power RC73 from 100K to 330K; RC79 from 330K to 1M; CC71 from 0.1u to 0.022u 0.4(X01) B
44,52 rail soft start timing. R412 from 100K to 470K; R1632 from 1M to 4.7M; C293 from 0.1u to 0.022u
R515 from 100K to 470K; R2126 from 1M to 4.7M; C416 from 0.1u to 0.022u
R731 from 100K to 470K; R1628 from 1M to 4.7M; C651 from 4700p to 220p
R930 from 100K to 470K; R1611 from 470K to 2.2M; C773 from 2200p to 100p
R2067 from 100K to 470K; C1272 from 2200p to 220p
R2069 from 100K to 470K; C1274 from 470p to 220p
87 16 HW 2012/02/29 COMPAL For NVDIA request. No stuff RV29. 0.5(X01)
88 40 HW 2012/02/29 COMPAL 2nd source. add R2196 ~ R2197, change power rail from +3.3V_RUN to +USB3 on U638.9 0.5(X01)
and U638.25
89 40 HW 2012/02/29 COMPAL Reserve for samsung mobile issue. add Q338 and No stuff. 0.5(X01)
90 51 HW 2012/03/01 COMPAL change MOS to single package. change Q84, Q339 from DMN66D0LDW to SSM3K7002FU. 0.5(X01)
91 25 HW 2012/02/29 COMPAL change FAN conn. change FAN conn from ACES_50450-0067N-001 to ACES_50271-0040N-001 on 0.5(X01)
JFAN1, JFAN2
A A
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Request
92 40 HW 2012/03/01 COMPAL change main source. change main source from MAX14618 to SLG55584A on U2. 0.5(X01)
D D
93 35 HW 2012/03/01 COMPAL For SATA Gen2, Gen3 EA setting. stuff R1173, R1204 and No stuff R1206. 0.5(X01)
94 43 HW 2012/03/01 COMPAL For SATA Gen2, Gen3 EA setting. stuff R2135, R2138 and No stuff R2139. 0.5(X01)
95 31 HW 2012/03/01 COMPAL Meet RGB panel sequencing. stuff L56 and No stuff L57. 0.5(X01)
96 28 HW 2012/03/01 COMPAL change to new manufacturing technology. change from RB751V-40GTE to RB751VM-40TE on D53,D64,D66,D67,D69,D100, 0.5(X01)
D101.
97 29 HW 2012/03/02 COMPAL According to new EIA rule. Change U627 from PS8330BQFN48GTR-A0 to PS8330BQFN48GTR2-A0. 0.5(X01)
98 28 HW 2012/03/05 COMPAL Solve LVDS cable burn out issue. change JLVDS1.4 and JLVDS2.4 to NC. 0.5(X01)
99 16 HW 2012/03/05 COMPAL Meet high level on DGPU_PEX_RST# for N14P. change RV29 to 750 ohm and stuff. 0.5(X01)
100 40 ME 2012/03/05 COMPAL Update Conn list. change JUSB1, JUSB2 from UEA111Y1-C1BD1-7H to AUSB0041-P001A. 0.5(X01)
101 34 HW 2012/03/05 COMPAL Meet AMD HDMI 297 MHz EA setting. stuff R71, R65, R67. 0.5(X01)
102 40 HW 2012/03/06 COMPAL 2nd source. change power rail from +3.3V_RUN to +USB3 on R26.1 0.5(X01)
C C
103 51 ME 2012/03/07 COMPAL ME request. add H27. 0.5(X01)
104 12 HW 2012/03/08 COMPAL layout space limitation. Remove RD12, RD13. 0.5(X01)
105 13 HW 2012/03/08 COMPAL layout space limitation. Remove RD21, RD22. 0.5(X01)
106 28 HW 2012/03/08 COMPAL Solve LVDS cable burn out issue. add one test point on JLVDS1.4 and JLVDS2.4 0.5(X01)
107 28 HW 2012/03/13 COMPAL Wrong CPN for prefix number. change CPN from SM010007O0L to SM070001I0L on L10. 0.5(X01)
108 11 HW 2012/03/13 COMPAL Solve backdrive (follow B4). change CPN from SB00000L800 to SB00000RV00 on QC3. 0.5(X01)
109 16 HW 2012/04/02 COMPAL Solve AUX signal pull to different power rail. Change power rail from +3.3V_RUN to +3.3V_AVDD. 0.6(X02)
110 28 EMI 2012/04/02 COMPAL EMI request.(RGB noise coupling to LVDS cable 224MHz) Reserve C1341, C1342 on LCD_SMBCLK and LCD_SMBDAT. 0.6(X02)
111 7~52 HW 2012/04/05 COMPAL short all reserved 0 Ohm resister. RC24,RC27,RC17,RC18,RC25,RC68,RC69,RC83,RD1,RD2,RD7,RD14, R1157,R1158, 0.6(X02)
RD15,RD16,RD23,RD24,RD25,RD32,RD33,RD34,RD39,RD40,R1169,R1624,R1626
R1970,RH286,RH290,RH307,RH308,RH82,RH83,RH85,RH86,RH88,RH90,RH92,R2089,
RH93,RH95,RH96,RH280,RH281,RH359,RH113,RH323,RH116,RH117,R2090,R2105,R2142
RH320,RH120,RH121,RH122,RH334,RH343,RH335,RH336,RH338,RH339,RH341,RH356,
B
RH259,RH150,RH201,R1187,R551,R552,R2159,RC29,RC34,RC40, B
R555,R1144,R702,R707,R709,R703,R724,R730,R713,R797,R771,R741,R815,RC9,RH1,
R1068,R867,R853,R855,R862,R1180,R1633,R781,R808,RH2,RH309,RH337,R2072,
R289,RH202,RH205,RH211.
112 26 HW 2012/04/05 COMPAL Remove current sensor function. No stuff R1974,R1975,C16,C17,C361,C363. 0.6(X02)
113 25 HW 2012/04/09 COMPAL change VSET from 88 ℃ to 93 ℃. change R406 from 953 ohm to 1.33K ohm. 0.6(X02)
114 49 HW 2012/04/09 COMPAL change Board ID to X03. change R875 from 62K ohm to 33K ohm. 0.6(X02)
115 29 HW 2012/04/09 COMPAL [DF543750]DP->HDMI/DP->S-DVI dongle no function on NV Add TMDS DDC PU schematic on DP port that include Q339, Q340,R2198~2201, 0.6(X02)
units. C1343.
116 42 HW 2012/04/09 COMPAL Add WiGig card function. Add net name WiGi_RADIO_DIS#_R on JMINI4.32, net name BT_RADIO_DIS#_R on 0.6(X02)
JMINI4.51, and reserve R2204, R2205, D104, D105.
117 48 HW 2012/04/09 COMPAL Add WiGig card function. change net name from VOL_MUTE_LED# to WiGi_RADIO_DIS# on U46.A1 0.6(X02)
PU 100K ohm on net WiGi_RADIO_DIS# and BT_RADIO_DIS#.
A A
Title
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Request
118 51 HW 2012/04/09 COMPAL Add WiGig card function. Remove Q339 for WiGig card function usage. 0.6(X02)
D D
119 47 HW 2012/04/09 COMPAL Add WiGig card function. Remove net VOL_MUTE_LED on JIO1.100 0.6(X02)
120 50 HW 2012/04/09 COMPAL Add WiGig card function. change net name from BT_RADIO_DIS# to BT_RADIO_DIS#_D on JBT1.6 0.6(X02)
Add R2206 and reserve D106 on net BT_RADIO_DIS#_D.
121 27 HW 2012/04/09 COMPAL Solve +3.3V_MXM backdrive when disable RUN_GFX_ON. Reserve R1121, R1122. 0.6(X02)
122 44 HW 2012/04/09 COMPAL for power saving in DC mode S3. change R716 to 47K ohm. 0.6(X02)
123 40 HW 2012/04/11 COMPAL Solve kinston storage device re-distinguish issue. stuff R28 and R30. 0.6(X02)
124 16 HW 2012/04/11 COMPAL update MXM conn PCB footprint. change footprint to JAE_MM70-314-310B1-1-_310P-S. 0.6(X02)
125 40 EMI 2012/04/16 COMPAL EMI request. change from DLW21SN900HQ2L to DLW21SN900SQ2L on L39, L41. 0.6(X02)
126 51 HW 2012/04/16 COMPAL Meet LED brightness spec. change R943 from 374 ohm to 240 ohm. 0.6(X02)
change R956 from 374 ohm to 200 ohm.
change R955 from 1.2K ohm to 887 ohm.
change R939, R941 from 1.2K ohm to 680 ohm.
C C
127 28 ME 2012/05/21 COMPAL ME request (DFX issue, cancel boss hole). change JLVDS2 from JAE_FI-M56S1-R1500 to JAE_FI-M56S1-R1500-DT. 1.0(A00)
128 17 HW 2012/05/21 COMPAL Create X76 BOM for 2nd source. Main source is WINBOND, 2nd source is EON. 1.0(A00)
129 17 HW 2012/05/21 COMPAL change to new manufacturing technology. change p/n from W25Q64CVSSIG to W25Q64FVSSIG. 1.0(A00)
130 49 HW 2012/05/21 COMPAL change Board ID to A00. change R875 from 33K ohm to 8.2K ohm. 1.0(A00)
131 42,51 HW 2012/05/22 COMPAL add WiGi_BT LED function. add net name WiGi_BT_LED# on JMINI.46, and add R2207(No stuff). 1.0(A00)
132 7,16 HW 2012/05/31 COMPAL Dalmore 12" warm/cold boot shutdown issue. change main source from NXP to ON on U16, UC1, U634. 1.0(A00)
133 22 HW 2012/05/31 COMPAL TAIYO EOL, change to TAI-TECH. change part from SHI0110BJ0L to SHI0110BJ50 on LH8. 1.0(A00)
134 51 HW 2012/06/05 COMPAL Meet LED brightness spec. change R943 from 240 ohm to 510 ohm. 1.0(A00)
B B
A A
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LA-7931P
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Sheet 70 of 70
1.0

Dell Precision M4700 LA-7931P Rev 10 (A00) Schematics

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Dell Precision M4700 LA-7931P Rev 10 (A00) Schematics

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A B C D E

MB Type BOM P/N Include 6‐bit MB Type BOM P/N Include 10‐bit

TPM 4319FN31L01 1@ 3@ 5@ PXDP@ TPM 4319FN31L02 1@ 3@ 6@ PXDP@

(SA00002EY1L) (SA00005PO00) U53 (SA00004LI00)

(10-bit panel output)

DP(DIS) BGA 989 Balls USB Port 2

P.41 P.17 Smart Card

Current Monitor Docking LAN

P.26 USB3.0 Port 3

SATA 3 ODD 13 Touch Screen

S5 S4/AC don't exist OFF OFF OFF OFF OFF

Lane 2 MINI CARD-1 WLAN/DMC

Lane 5 MINI CARD-3 (Pink Panther)

Lane 6 MINI CARD-2 WWAN/mSATA/GPS

Lane 7 10/100/1G LOM

RUN_GFX_ON SI4835DDY (U45) (Q27) (Q30)

PCH_ALW_ON +5V_USB_PWR1 +5V_HDD +5V_MOD

RT8207 TPS51212 TPS51212

+1.5V_MEM +1.05V_M +1.05V_RUN_VTT

+0.75V_DDR_VTT AO4728L NTGS4141

2.2K 200 DIMM4

1B A4 LCD_SMBDAT 10 Current Monitor

2.2K SMBUS Address

Compal Electronics, Inc.

PCI EXPRESS* - GRAPHICS

C17 PEG_TX[7] J27 PEG_CTX_GRX_C_P8 CC57 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P8 H1 VSS221

+3.3V_ALW_PCH 1 2 SYS_PWROK_XDP +1.05V_RUN_VTT

H_CATERR# AL33 CLK_XDP @ RH1 1 2 0_0402_5%~D

<49> PECI_EC PECI SM_DRAMRST# DDR3_DRAMRST# <12>

<19> H_PM_SYNC PM_SYNC TRST#

10K_0402_5%~D RC46 SM_RCOMP0 1 2

DDR SYSTEM MEMORY B

VAXG_VAL_SENSE AJ31 H16 @ T15 PAD~D

1 2 VSSAXG_VAL_SENSE PAD~D T18 @ AJ26 AR35 attached to Embedded Display Port

PAD~D T24 @ F25

PAD~D T37 @ C30 @ T36 PAD~D

PAD~D T43 @ B31 RSVD20 RSVD51 AK32 @ T42 PAD~D

PAD~D T49 @ J15 AT2 @ T50 PAD~D 10: x8, x8 ‐ Device 1 function 1 enabled ; function 2

WWW.AliSaler.Com JCPU1F CONN@ POWER

PEG AND DDR

VCC89 VCC_SENSE VCCSENSE <60>

WWW.AliSaler.Com +1.5V_CPU_VDDQ Source Solve backdrive (follow B4).

POWER VSS13 VSS93

VAXG26 VDDQ2 VSS44 VSS125

VCCSA_SENSE VCCSA_SENSE <59> VSS79 VSS160

1 C24 VCCSA_VID_1 <59>

A19 VCCP_PWRCTRL_R 1 2 0_0402_5%~D VCCP_PWRCTRL <58>

JDIMM1 STD Type H=5.2 JDIMM1 (Ch A1 H=5.2 STD)

63 64 DDR_A_DQS3 +DIMM0_1_VREF_CPU +V_DDR_REFA_M3

DDR_A_MA13 119 120 M_ODT5

125 126 1 2 0_0402_5%~D

DDR_A_D48 163 164 DDR_A_D52

DDR_A_D49 165 166 DDR_A_D53

173 DQS6 VSS43 174 DDR_A_D50

1 0 DIMM1 DDR_A_D57 183 184

185 186 DDR_A_DQS#7

+3.3V_RUN DDR_A_D63 193 DQ58 DQ62 194 DDR_A_D59

1 1 +0.75V_DDR_VTT 203 204 +0.75V_DDR_VTT

Link CIS OK DELL CONFIDENTIAL/PROPRIETARY

Date: Monday, July 23, 2012 Sheet 12 of 70

WWW.AliSaler.Com JDIMM3 (Ch B1 H=9.2 STD)

All VREF traces should JDIMM2 REV Type H=5.2 JDIMM1 (Ch A1 H=5.2 STD)

DDR_A_D52 163 164 DDR_A_D48