Abhijeet

Summary:
Total 16 years plus of experience in Hardware domain.
● System Verilog /UVM/Verilog HDL/VHDL / VERA
● Module level /Full Chip verification.
● Writing BFM in UVM/System Verilog HDL
● Writing verification component like Scoreboard & Monitor.
● Test / Verification plan development, Automation in environments during regression testing
using LSF and Perl / c-shell scripting
● Functional Coverage, Code Coverage and Fault Coverage.
● RTL Coding.
● Experience in handling and coordinating with different teams across verticals from specifications
to implementation.
● Working in Industry with 6 Years of experience in Project Management.

Technical Skills:
● Technologies: System Verilog, UVM, VHDL, Coverage Driven Verification, Assertion Based
Verification, Functional Coverage, Code Coverage, Writing BFM in Verilog HDL/VHDL / VERA
/System Verilog.
● S/W Languages: Verilog HDL, System Verilog, Verilog, VHDL, C and C++
● Operating Systems: Linux, Unix, Windows-7,10
● Tools: CADENCE, VERILOG-XL / NC-VERILOG, SYNOPSYS VCS/DVE, VERA.
SCIROCCO, MODELSIM, VERFIAULT, DEBUSSY, SIMVISION, VIRSIM.
● BUS protocols: AMBA APB, AHB & AXI, SPI-3, SPI-4, SPI, I2C, PCI, PCIX.
● Scripting Tools: C-shell and Perl

Project Management:
● Managed ODC’s for Intel and Apple customers. Handled Intel project (HPG Val Group)

Project Experience:

Project 1:
I worked as a Senior Staff Engineer DV and was responsible for Pre-silicon verification/ validation of IP
block.
Client: Intel (HPG Group)
Roles and Responsibilities:
Project Management, Verification Planning, IP Top Level Integration and Coverages, Maintain UVM based
environment for AIB IP block with JTAG BFM.

Project 2:
I worked as a Verification Lead. I was responsible for Pre-silicon verification of highly integrated System-
On-Chip (SOCs) and IPs.
Client: Silicon Labs
Roles and Responsibilities:
Maintaining SV/UVM Based Environment Verification Planning, SOC /IP Level Coverages.
Abhijeet

Project 3:
I worked as a Verification Lead. I was responsible for Pre-silicon verification of highly integrated System-
On-Chip (SOCs).
Client: Cisco and Intel
Roles and Responsibilities:
I worked as a Verification Lead for Pre-silicon and Post-silicon validation of highly integrated System-On-
Chip (SOCs) targeted for server applications.

Project 4:
I was responsible for managing the pre-silicon verification and post-silicon validation activities for DFX
group.
Roles and Responsibilities:
These projects involved Pre-silicon validation of block level (functional), System level and use case
scenarios, RTL Simulation, Gate Level Simulation. maintain test bench, verification plan, coverage
planning, to improve on fault coverage, code coverage and doing Automation in environments during
regression testing using LSF, analyzing coverage. MBIST Verification using customized IBM flow. I was also
responsible for coordinating between Verification, Validation and PD teams.

Project 5:
Client: RF Silicon/ LogicFabLtd
I worked as a Verification Lead for Pre-silicon verification of highly integrated System-On-Chip (SOCs) and
RFID Chips.

Project 6:
AHB-DMA Controller:
Client: RF Silicon/ LogicFabLtd
This controller has two channels to perform read/write operations between the memory and
customizable interface (SPI, I2C, USB or SDIO etc.) The DMA can perform only single data transfers (No
burst transactions) across the AHB bus. Each DMA channel enables movement of data from a source AHB
address to the IP or IP to the destination AHB address, for a given programmed count. I was responsible
for maintaining verification environment, verification plan , coverage flow, regressions in System Verilog
and verilogHDL. Analysis and debug for code coverage, functional coverage, automating regression
testing.
I was also responsible in coordination between Verification, Validation and PD teams.

Project 7:
D4385 RFID:
Client: ASICentrum, Prague,Czech Republic
D4385 is ultra-low power 64bit contactless card based on RFID EPC and ISO 18000 for RFID air interface.
D4385 is based on Interrogator/Reader and tag protocol. I was responsible for verification of complete
digital logic, maintain verification environment, verification plan, coverage flow, regressions in VHDL.
Abhijeet

Project 8:
Eagle Reader:
Client: ASICentrum, Prague,Czech Republic
I was involved in developing Eagle STIL reader as a module which accepts IEEE STIL file as input which
generates File in Eagle STIL format. This whole conversion was in VHDL and got tested Eagle tester.

Project 9:
D4233 RFID:
Client: ASICentrum, Prague,Czech Republic
D4233 is ultra-low power 64bit contactless card based on RFID ISO 15693. It has no external supply buffer
capacitor. D4233 supported all optional as well as mandatory commands as mentioned in ISO 15693. I
was responsible for verification of complete digital logic, maintain verification environment, verification
plan, coverage flow, regressions in VHDL.

Project 10:
Fault Grading
Client: Microchip, Bangalore, India
This project basically was coverage improvement for Microcontroller (MICROCHIP).
I was involved in developing test cases for microcontroller to run gate level simulation for controllability
and observability, generate patterns and find faults by Verifault to improve coverage of microcontroller.
I worked here as a Senior Design Engineer for Pre-silicon verification of highly integrated System-On-Chip
(SOCs) and post silicon debug. Analysis and debug for code coverage, functional coverage, automating
regression testing running on remote server using perl and c-shell scripting, analysing coverage analysis
using uniform coverage reporting.

Project 10:
Fault Coverage
Client: TI, Bangalore, India
This project basically was coverage improvement for TI DSP processor for OMAP family.
I was involved in modifying the test cases for DSP block to run functional verification and then gate level
simulation to generate Patterns in TI TDL format which used to validate tests on Tester.

Project 11:
Button Scan Matrix
Client: TI, Dallas, USA
The Button Matrix interface provides a simple mechanism to read a matrix keypad. This interface is
designed to work with a 4X4 matrix to provide 16 button inputs. All the button inputs are denounced
based upon 3 consecutive samples. The sample rate is programmable in 4ms to 255ms.Each button can
be programmed to generate an interrupt on button down and or button up transitions or not at all. I was
responsible for Block design.Design documentation of the design.Develop RTL in
verilogHDL.Configuration write/read register logic State machine coding.Block and Fullchip verification.
Abhijeet

Project 12:
LED Control
Client: TI, Dallas, USA
The LED subsystem provides a means for the ARM9 to turn on, turn off or flash an LED at one of the two
rates (fast or slow) without additional firmware involvement. The system uses two PWM outputs for
controlling the flash rates. Each LED is controlled by two bits that provide the function of the LED.I was
involved in Block design, Develop RTL in verilogHDL,configuration write/read register logic, State machine
coding, Block and Fullchip verification

Project 13:
VBUS To Wishbone and VBUS To Arm IF
Client: TI, Dallas, USA
In this project, Vbusp2Wishbone bridge, converts VBUS protocol to equivalent wishbone protocol.
Vbusp2Armif bridge, converts VBUS protocol to equivalent arm interface protocol. I was involved in block
level verifications of this two interfaces.

Project 14:
ALPS Interface Control Verification
Client: TI, Dallas, USA
This block provides the control signals to print head, DC motor and stepping motor. This block had on one
side VBUS to wishbone interface and on the other side print head and motor interface. I was involved
Module level environment bring up from NC-Verilog to VCS Modified the test bench for module level ,
modified scripts to support to VCS module level test case debug.Top-level verification of all the module
level test cases. Translated module level test cases to top level in C.

Project 15:
Alliance Semiconductor Ltd
I worked here as a Design Engineer for Pre-silicon verification of Wide Area Network Chipvarious blocks
like PCI/PCIX Bridge,SPI-3/SPI-4.

Project 16:
Glue Logic for PCI/PCIX To PCI/PCIX Bridge
To develop RTL code for PCI/PCIX glue logic. This has interface with posted & non posted buffers.Glue
logic controls the data traffic from primary bus to secondary bus via data control buffers to the secondary
bus. Glue logic interfaces COMPAQ PCI/PCIX equivalent signals and data control buffers. Glue has two
state machines, one for posted transactions and other for non-posted transactions.I was involved in Block
design. Design documentation of design
Develop RTL in verilogHDL.Configuration write/read register logic State machine coding in verilog HDL,
block level and fullchip verification.
Abhijeet

Project 17:
SPI-3 and SPI-4 Core Verification
I was involved in the development of SPI-3 and SPI-4 BFM (transmitter and receiver), block and fullchip
verification. I was responsible for maintaining verification environment, verification plan, coverage flow,
regressions in verilogHDL. Analysis and debug for code coverage, functional coverage, automating
regression testing.

Education:
● Master of Science (MSc. Electronics Science) – 1999
University Of Pune, Maharashtra
Percentage: 60:00%
● Diploma In VLSI Design – 1999
Helios Technologies, Pune, Maharashtra
Percentage: 65:00%
● Bachelor of Engineering (BSc. Electronics Science) - 1997
University Of Pune, Maharashtra
Percentage: 59:85%
● Higher Secondary Certificate (H.S.C.) - 1994
N.Wadia College, Maharashtra
Percentage: 61:33%
● Secondary School Certificate (S.S.C.) - 1992
Bharat English School, Maharashtra
Percentage: 79:85%