DEVAGUPTAPU RADHAKRISHNA

Professional Summary

• Professional with 2+ years of experience in Analog & Mixed Signal Layout designing.
• Worked on various types of Analog and Mixed signal projects like Power Management
blocks, LDO, Data Converters, GPIO.
• Having good knowledge on TSMC 3nm FINFET Technology
• Worked on TSMC 3nm FINFET ,45nm, 65nm MOSFET technologies.
• Designed various types of layouts like Differential amplifiers, Current mirrors, Op-amps,
and Bang Gap reference, Standard Cells.
• Worked on Matching the devices by using Inter digitization, Common-Centroid Techniques.
• Worked on Floor planning, Routing and Physical Verification with Calibre tool.
• Hands on fixing Latch-up, EM issues, IR Drop
• Having good knowledge on Cross talk, Shielding, WPE and Antenna violations, STI, LOD and
Signal Integrity.
• Good Knowledge on CMOS fundamentals and its fabrication process
• Good communication with designers to meet design specifications

Education

• B. Tech (Electrical and Electronics Engineering), JNTUK- 2016 with 74%.

• Diploma (Electrical and Electronics Engineering), SBTET- 2013 with 83%.

Technical Skills

• Tool : Cadence
• Verification tools : PVS, Calibre.
• Operating systems : Windows, Linux

Professional Experience

Project Title : GPIO

Client : Seagate
Sub Blocks : Driver pre driver, Level Shifter.
Tools : Cadence Virtuoso for Layout, Calibre for verification.
Technology : 3nm (TSMC)
Role : Floor planning, routings and verification for Sub-Blocks.

Challenges:
• Handled layout Floorplan, Routing with LVS and DRC clean.
• Designed power mesh with higher metals.
Project Title : Low Drop Out (LDO)
Client : Seagate
Sub Block : Op-Amp (Error Amplifier)
Tools : Cadence Virtuoso for Layout, Calibre for verification.
Technology : 45nm (TSMC)
Role : Floor planning for Op-Amp with matching Techniques for BJT’s,
current mirrors & Diff Pair.
Challenges:
• Designed the Layout for LDO using op-amp as error Amplifier with pass element PMOS and
Feedback resistors. In which Matching, Area, Electro migration and constraints are taken into
consideration.
• Layout design for block level (Error-Amp, BGR and Pass element) and top level also.

Project Title : Bandgap Reference

Client : Seagate
Tools : Cadence Virtuoso for Layout, Calibre for verification.
Technology : TSMC 45nm
Role : Floor planning for BGR with common centroid matching for BJT’s &
current legs.
Challenges:
• Designed complete layout design, matching of Current mirrors and differential
amplifiers, take care of EM issues.
• Designed strong power routing with higher metal.

Project Title : Digital Cells

Client : Inhouse
Tools : Cadence Virtuoso for Layout, Assura for verification
Technology : TSMC 65 nm

Challenges:
• Designing of digital cells like 3*8 Decoder, 8*1 MUX, Buffer, Level Shifter, Sensor blocks
and Dec top up to N-2 hierarchy
• Worked on hierarchy and Gained knowledge on use of clones
• Placing pins on PR boundary on top or bottom or left or right based on given constraints
• Routing using only lower metals was challenging. Physical Verification of each block was
done.

Project Title : Standard Cells

Client : Inhouse
Tools : Cadence Virtuoso for Layout, PVS for verification
Technology : TSMC 65nm

Challenges:
• Designing of standard cells like INV, NAND, AND, OR and NOR, EXNOR, EXOR
different drive strength cells like inverter 2x, 4x, 8x, etc. were also designed for the
given Standard height.
• Routing using only lower metals was challenging. Physical Verification of each block was
done.