for download complete version of solution (all chapter 1 to 8 ) click here.

Digital Logic Circuit

Analysis and Design
Second Edition

Problem Solutions Manual

gioumeh.com
Victor P. Nelson
Auburn University

Bill D. Carroll
University of Texas at Arlington

H. Troy Nagle
North Carolina State University

J. David Irwin
Auburn University

Pearson

https://gioumeh.com/product/digital-logic-circuit-analysis-and-design-solution/
© 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist.
No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
 for download complete version of solution (all chapter 1 to 8 ) click here.

Contents

Chapter 1 Number Systems and Digital Codes .......................................... 1

Chapter 2 Logic Circuits and Boolean Algebra ......................................... 27
Chapter 3 Combinational Logic Circuit Design and Analysis ................... 107
Chapter 4 Introduction to Sequential Circuits ....................................... 189
Chapter 5 Synchronous Sequential Circuit Analysis and Design ............. 215
Chapter 6 Asynchronous Sequential Circuit Analysis and Design ........... 265
Chapter 7 Programmable Digital Logic Devices ..................................... 303
Chapter 8 Design of Digital Systems ...................................................... 347

https://gioumeh.com/product/digital-logic-circuit-analysis-and-design-solution/
© 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist.
No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
 Digital Logic Circuit Analysis and Design, 2nd Edition

for download complete version of solution (all chapter 1 to 8 ) click here.

Chapter 1 – Number Systems and Digital Codes

1.1 Calculate A + B , A − B , A× B , and A ÷ B for the following pairs of binary numbers.

(a) 10101, 1011
1 1 1 1 1 0 10 0 10
1 0 1 0 1 1 0 1 0 1
+ 1 0 1 1 ‒ 1 0 1 1
1 0 0 0 0 0 1 0 1 0

1 0 1 0 1 1
× 1 0 1 1 1 0 1 1 1 0 1 0 1
1 0 1 0 1 - 1 0 1 1
1 0 1 0 1 Remainder 1 0 1 0
0 0 0 0 0
1 0 1 0 1
1 1 1 0 0 1 0 1

(b) 1011010, 101111

10 1 10
1 1 1 1 1 1 0 10 0 0 10 0 10
1 0 1 1 0 1 0 1 0 1 1 0 1 0
+ 1 0 1 1 1 1 ‒ 1 0 1 1 1 1
1 0 0 0 1 0 0 1 1 0 1 0 1 1

1 0 1 1 0 1 0 0 1 . 1 1
× 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 0 1 0 . 0 0
1 0 1 1 0 1 0 1 0 1 1 1 1
1 0 1 1 0 1 0 1 0 1 1 0 1 0
1 0 1 1 0 1 0 1 0 1 1 1 1
1 0 1 1 0 1 0 0 1 0 1 0 1 1 0
0 0 0 0 0 0 0 1 0 1 1 1 1
1 0 1 1 0 1 0 0 1 0 0 1 1 1 0
1 0 0 0 0 1 0 0 0 0 1 1 0 1 0 1 1 1 1
Remainder 0 1 1 1 1 1

https://gioumeh.com/product/digital-logic-circuit-analysis-and-design-solution/
1 material is protected under all copyright laws as they currently exist.
© 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This
No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
 Digital Logic Circuit Analysis and Design, 2nd Edition

for download complete version of solution (all chapter 1 to 8 ) click here.

(c) 101, 1011
1
1 1 10 0 10
1 0 1 0 1 0 1
+ 1 0 1 1 ‒ 1 0 1 1
1 0 0 0 0 (1) 1 0 0 0 0
Borrow

1 0 1 0. 0 1 1
× 1 0 1 1 1 0 1 1 1 0 1. 0 0 0
1 0 1 - 1 0 1 1
1 0 1 1 0 0 1 0
0 0 0 - 1 0 1 1
1 0 1 Remainder 0 1 1 1
1 1 0 1 1 1

(d) 10110110, 01011011

1 1 1 1 1 1 10 10
1 0 1 1 0 1 1 0 0 10 0 0 10 0 0 10
+ 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0
1 0 0 0 1 0 0 0 1 ‒ 0 1 0 1 1 0 1 1
0 1 0 1 1 0 1 1

1 0 1 1 0 1 1 0
× 0 1 0 1 1 0 1 1
1 0 1 1 0 1 1 0
1 0 1 1 0 1 1 0
0 0 0 0 0 0 0 0
1 0 1 1 0 1 1 0
1 0 1 1 0 1 1 0
0 0 0 0 0 0 0 0
1 0 1 1 0 1 1 0
0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 1 0 1 1 0 0 1 0

1 0
0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0
1 0 1 1 0 1 1
0 0 0 0 0 0 0 0

https://gioumeh.com/product/digital-logic-circuit-analysis-and-design-solution/
2 material is protected under all copyright laws as they currently exist.
© 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This
No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
 Digital Logic Circuit Analysis and Design, 2nd Edition

for download complete version of solution (all chapter 1 to 8 ) click here.

(e) 1101011, 1010
1 1
1 1 0 1 0 1 1 1 1 0 1 0 1 1
+ 1 0 1 0 ‒ 1 0 1 0
1 1 1 0 1 0 1 1 1 0 0 0 0 1

1 1 0 1 0 1 1 1 0 1 0
× 1 0 1 0 1 0 1 0 1 1 0 1 0 1 1
0 0 0 0 0 0 0 1 0 1 0
1 1 0 1 0 1 1 0 0 1 1 0 1
0 0 0 0 0 0 0 1 0 1 0
1 1 0 1 0 1 1 Remainder 0 1 1 1
1 0 0 0 0 1 0 1 1 1 0

(f) 1010101, 101010

0 10 0 10 0 10
1 0 1 0 1 0 1 1 0 1 0 1 0 1
+ 1 0 1 0 1 0 ‒ 1 0 1 0 1 0
1 1 1 0 0 0 1 0 1 0 1 0 1 1

1 0 1 0 1 0 1 1 0 . 1 1
× 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 . 0 0
0 0 0 0 0 0 0 1 0 1 0 1 0
1 0 1 0 1 0 1 Remainder 0 1 0 0
0 0 0 0 0 0 0
1 0 1 0 1 0 1
0 0 0 0 0 0 0
1 0 1 0 1 0 1
1 1 0 1 1 1 1 1 0 0 1 0

(g) 10000, 1001

1 1 1
1 0 0 0 0 0 10 10 10 10
+ 1 0 0 1 1 0 0 0 0
1 1 0 0 1 ‒ 1 0 0 1
0 0 1 1 1

1 0 0 0 0 1 .1 1
× 1 0 0 1 1 0 0 1 1 0 0 0 0 .0 0
1 0 0 0 0 - 1 0 0 1
0 0 0 0 0 0 1 1 1 0
0 0 0 0 0 1 0 0 1
1 0 0 0 0 0 1 0 1 0
1 0 0 1 0 0 0 0 1 0 0 1

https://gioumeh.com/product/digital-logic-circuit-analysis-and-design-solution/
3 material is protected under all copyright laws as they currently exist.
© 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This
No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
 Digital Logic Circuit Analysis and Design, 2nd Edition

for download complete version of solution (all chapter 1 to 8 ) click here.

Remainder 0 0 0 1
(h) 1011.0101, 110.11
1 1 1 1 1
1 0 1 1. 0 1 0 1 0 10 0 10
+ 1 1 0. 1 1 1 0 1 1. 0 1 0 1
1 0 0 1 0 0 0 0 1 ‒ 1 1 0. 1 1
0 1 0 0. 1 0 0 1

1 0 1 1. 0 1 0 1
× 1 1 0. 1 1
1 0 1 1 0 1 0 1
1 0 1 1 0 1 0 1
0 0 0 0 0 0 0 0
1 0 1 1 0 1 0 1
1 0 1 1 0 1 0 1
1 0 1 1 1 0 0. 0 1 0 1 1 1

1. 1 0
1 1 0. 1 1 1 0 1 1. 0 1 0 1
1 1 0 1 1
1 0 0 1 0 0
1 1 0 1 1
Remainder 0 1 0 0 1 1

1.2 Calculate A + B , A − B , A× B , and A ÷ B for the following pairs of octal numbers.

(a) 372, 156
1 1 6 12
3 7 2 3 7 2
+ 1 5 6 ‒ 1 5 6
5 5 0 2 1 4

3 7 2 2. 2 1
× 1 5 6 1 5 6 3 7 2. 0 0
2 7 3 4 3 3 4
2 3 4 2 3 6 0
3 7 2 3 3 4
6 5 5 5 4 2 4 0
1 5 6
Remainder 6 2

https://gioumeh.com/product/digital-logic-circuit-analysis-and-design-solution/
4 material is protected under all copyright laws as they currently exist.
© 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This
No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
 Digital Logic Circuit Analysis and Design, 2nd Edition

for download complete version of solution (all chapter 1 to 8 ) click here.

(b) 704, 230
6 10
7 0 4 7 0 4
+ 2 3 0 ‒ 2 3 0
1 1 3 4 4 5 4

7 0 4 2. 7 6
× 2 3 0 2 3 0 7 0 4. 0 0
0 0 0 4 6 0
2 5 1 4 2 2 4 0
1 6 1 0 2 0 5 0
2 0 6 1 4 0 1 7 0 0
1 5 2 0
Remainder 1 6 0

(c) 1000, 777

7 7
0 10 10 10
1 0 0 0 1 0 0 0
+ 7 7 7 ‒ 7 7 7
1 7 7 7 0 0 0 1

1 0 0 0 1. 0 0 1
× 7 7 7 7 7 7 1 0 0 0. 0 0 0
7 0 0 0 7 7 7
7 0 0 0 0 0 1 0 0 0
7 0 0 0 7 7 7
7 7 7 0 0 0 Remainder 0 0 0 1

(d) 423, 651

4 11
4 2 3 ‒ 6 5 1
+ 6 5 1 4 2 3
1 2 7 4 ‒ 2 2 6

4 2 3 0. 5 1 3
× 6 5 1 6 5 1 4 2 3. 0 0 0
4 2 3 4 1 1 5
2 5 3 7 1 1 3 0
3 1 6 2 0 6 5 1
3 4 4 2 1 3 2 5 7 0
2 3 7 3
Remainder 1 7 5

https://gioumeh.com/product/digital-logic-circuit-analysis-and-design-solution/
5 material is protected under all copyright laws as they currently exist.
© 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This
No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
 Digital Logic Circuit Analysis and Design, 2nd Edition

for download complete version of solution (all chapter 1 to 8 ) click here.

1.3 Calculate A + B , A − B , A× B , and A ÷ B for the following pairs of hexadecimal
numbers.
(a) 2CF3, 2B
1 E 13
2 C F 3 2 C F 3
+ 2 B ‒ 2 B
2 D 1 E 2 C C 8

2 C F 3 1 0 B
× 2 B 2 B 2 C F 3
1 E E 7 1 2 B
5 9 E 6 0 1 F 3
7 8 C D 1 1 D 9
Remainder 1 A

(b) FFFF, 1000

1
F F F F F F F F
+ 1 0 0 0 ‒ 1 0 0 0
1 0 F F F E F F F

F F F F F. F F
× 1 0 0 0 1 0 0 0 F F F F. 0 0
0 0 0 0 F 0 0 0
0 0 0 0 F F F 0
0 0 0 0 F 0 0 0
F F F F F F 0 0
F F F F 0 0 0 F 0 0 0
Remainder F 0 0

(c) 9A5, D17

C 11
9 A 5 ‒ D 1 7
+ D 1 7 + 9 A 5
1 6 B C 3 7 2

9 A 5 0. B C 9
× D 1 7 D 1 7 9 A 5. 0 0 0
4 3 8 3 8 F F D
9 A 5 A 5 3 0
7 D 6 1 9 D 1 4
7 E 3 E D 3 8 1 C 0
7 5 C F
Remainder B F 1

https://gioumeh.com/product/digital-logic-circuit-analysis-and-design-solution/
6 material is protected under all copyright laws as they currently exist.
© 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This
No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
 Digital Logic Circuit Analysis and Design, 2nd Edition

for download complete version of solution (all chapter 1 to 8 ) click here.

(d) 372, 156
6 12
3 7 2 3 7 2
+ 1 5 6 ‒ 1 5 6
4 C 8 2 1 C

3 7 2 2. 9 4
× 1 5 6 1 5 6 3 7 2. 0 0
1 4 A C 2 A C
1 1 3 A C 6 0
3 7 2 C 0 6
4 9 A 4 C 5 A 0
5 5 8
Remainder 4 8

https://gioumeh.com/product/digital-logic-circuit-analysis-and-design-solution/
7 material is protected under all copyright laws as they currently exist.
© 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This
No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
 Digital Logic Circuit Analysis and Design, 2nd Edition

for download complete version of solution (all chapter 1 to 8 ) click here.

1.4 Convert each of the following decimal numbers to binary, octal, and hexadecimal
numbers.
(a) 27
2 2 7 1 LSD 8 2 7 3 LSD 1 6 2 7 B LSD
2 1 3 1 8 3 3 MSD 1 6 3 1 MSD
2 6 0 0 0
2 3 1 (27)10 = (33)8 (27)10 = (1B)16
2 1 1 MSD
0
(27)10 = (11011)2

(b) 915
2 9 15 1 LSD 8 9 1 5 3 LSD 1 6 9 1 5 3 LSD
2 4 57 1 8 1 1 4 2 1 6 5 7 9
2 2 28 0 8 1 4 6 1 6 3 3 MSD
2 1 14 0 8 1 1 MSD 0
2 57 1 0 (27)10 = (393)16
2 28 0 (915)10 = (1623)8 Or
2 14 0 Or (915)10 = (11 1001 0011)2
27 1 (915)10 = (1 110 010 011)2 = (3 9 3 )16
23 1 = (1 6 2 3 )8
21 1 MSD
0
(915)10 = (1110010011)2

(c) 0.375
0.375 × 2 = 0.750 0.375 × 8 = 3.000 0.375 × 16 = 6.000
0.750 × 2 = 1.500
0.500 × 2 = 1.000 (0.375)10 = (0.3)8 (0.375)10 = (0.6)16

(0.375)10 = (0.011)2

(d) 0.65
.65 × 2 = 1.3 .65 × 8 = 5.2 0.65 × 16 = 10.4
.3 × 2 = 0.6 .2 × 8 = 1.6 0.4 × 16 = 6.4
.6 × 2 = 1.2 .6 × 8 = 4.8 repeat
.2 × 2 = 0.4 .8 × 8 = 6.4
.4 × 2 = 0.8 .4 × 8 = 3.2 (0.375)10 = (0.A4)16
.8 × 2 = 1.6 repeat
repeat
(0.65)10 = (0.51463)8
(0.65)10 = (0.101001)2

https://gioumeh.com/product/digital-logic-circuit-analysis-and-design-solution/
8 material is protected under all copyright laws as they currently exist.
© 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This
No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
 Digital Logic Circuit Analysis and Design, 2nd Edition

for download complete version of solution (all chapter 1 to 8 ) click here.

(e) 174.25
Integer part:
2 1 7 4 0 LSD 8 1 7 4 6 LSD 1 6 1 7 4 14 LSD
2 8 7 1 8 2 1 5 1 6 1 0 10 MSD
2 4 3 1 8 2 2 MSD 0
2 2 1 1 0 (174)10 = (AE)16
2 1 0 0 (174)10 = (256)8 Or
2 5 1 Or (174)10 = (1010 1110)2
2 2 0 (174)10 = (10 101 110)2 =( A E )16
2 1 1 = (2 5 6 )8
0
(174)10 = (10101110)2

Fractional part:
.25 × 2 = 0.5 .25 × 8 = 2.0 0.25 × 16 = 4.0
.5 × 2 = 1.0
(0.25)10 = (0.2)8 (0.25)10 = (0.4)16
(0.25)10 = (0.01)2

Therefore, combining integer and fractional parts:

(174.25)10 = (10101110.01)2 = (256.2)8 = (AE.4)16

(f) 250.8
Integer part:
2 2 5 0 0 LSD 8 2 5 0 2 LSD 1 6 2 5 0 10 LSD
1 1 2 5 1 8 3 1 7 1 6 1 5 15 MSD
2 6 2 0 8 3 3 MSD 0
2 3 1 1 0 (250)10 = (FA)16
2 1 5 1 (250)10 = (372)8 Or
2 7 1 Or (250)10 = (1111 1010)2
2 3 1 (250)10 = (11 111 010)2 =( F A )16
2 1 1 = (3 7 2 )8
0
(250)10 = (11111010)2

Fractional part:
.8 × 2 = 1.6 .8 × 8 = 6.4 0.8 × 16 = 12.8
.6 × 2 = 1.2 .4 × 8 = 3.2 repeats
.2 × 2 = 0.4 .2 × 8 = 1.6
.4 × 2 = 0.8 .6 × 8 = 4.8 (0.8)10 = (0.C)16
repeats repeats

(0.8)10 = (0.1100)2 (0.8)10 = (0.6314)8

https://gioumeh.com/product/digital-logic-circuit-analysis-and-design-solution/
9 material is protected under all copyright laws as they currently exist.
© 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This
No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
 Digital Logic Circuit Analysis and Design, 2nd Edition

for download complete version of solution (all chapter 1 to 8 ) click here.

Therefore, combining integer and fractional parts:

(250.8)10 = (11111010.1100)2 = (372.6314)8 = (FA.C)16

1.5 Convert each of the following binary numbers to octal, hexadecimal, and decimal
numbers using the most appropriate conversion method.
(a) 1101
001 101 1101
1 5 = (15)8 D = (D)16

23 + 22 + 20 = 8 + 4 + 1 = (13)10

(b) 101110
101 110 0010 1110
5 6 = (56)8 2 E = (2E)16

25 + 23 + 22 + 21 = 32 + 8 + 4 + 2 = (46)10

(c) 0.101
.101 .1010
.5 = (.5)8 .A = (.A)16

2-1 + 2-3 = .5 + .125 = (.625)10

(d) 0.01101
.011 010 .0110 1000
.3 2 = (.32)8 .6 8 = (.68)16

2-2 + 2-3+ 2-5 = .25 + .125 + .03125 = (.40625)10

(e) 10101.11
010 101.110 0001 0101 . 1100
2 5 . 6 = (25.6)8 1 5 . C = (15.C)16

24 + 22 + 20 + 2-1 + 2-2 = 16 + 4 + 1 + .5 + .25 = (21.75)10

(f) 10110110.001
010 110 110 . 001 1011 0110 . 0010
2 6 6 . 1 = (266.1)8 B 6 . 2 = (B6.2)16

27 + 25 + 24 + 22 + 21 + 2-3 = 128 + 32 + 16 + 4 + 1 + .125 = (181.125)10

https://gioumeh.com/product/digital-logic-circuit-analysis-and-design-solution/
10 material is protected under all copyright laws as they currently exist.
© 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This
No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
 Digital Logic Circuit Analysis and Design, 2nd Edition

for download complete version of solution (all chapter 1 to 8 ) click here.

1.6 Convert each of the following octal numbers to binary, hexadecimal, and decimal using
the most appropriate conversion method.
(a) 65
(65)8 = (110 101)2
6 5
0011 0101 = (35)16
3 5
6 × 8 + 5 = 48 + 5 = (53)10
(b) 371
(371)8 = (011 111 001)2
3 7 1
1111 1001 = (F9)16
F 9
3 × 8 + 7 × 8 + 1 = 192 + 56 + 1 = (249)10
2

(c) 240.51
(240.51)8 = (010 100 000 . 101 001)2
2 4 0 5 1
1010 0000 . 1010 0100 = (A0.A4)16
A 0 A 4
2 × 8 + 4 × 8 + 5 × 8 + 4 × 8-2 = 128 + 32 + .625 + .0156 = (160.6406)10
2 -1

(d) 2000
(2000)8 = (010 000 000 000)2
2 0 0 0
0100 0000 0000 = (400)16
4 0 0
2 × 8 = 1024 = (1024)10
3

(e) 111111
(111111)8 = (001 001 001 001 001 001)2
1 1 1 1 1 1
1001 0010 0100 1001 = (9249)16
9 2 4 9
8 + 8 + 8 + 8 + 81 + 80 = 32,878 + 4,096 + 512 + 64 + 8 + 1 = (37,449)10
5 4 3 2

(f) 177777
(177777)8 = (001 111 111 111 111 111)2
1 7 7 7 7 7
1111 1111 1111 1111 = (FFFF)16
F F F F
8 + 7 × 8 + 7 × 8 + 7 × 8 + 7 × 8 + 7 = 32,768 + 28,672 + 3,584 + 448 + 56 + 7 = (65,535)10
5 4 3 2

https://gioumeh.com/product/digital-logic-circuit-analysis-and-design-solution/
11 material is protected under all copyright laws as they currently exist.
© 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This
No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
 Digital Logic Circuit Analysis and Design, 2nd Edition

for download complete version of solution (all chapter 1 to 8 ) click here.

1.7 Convert each of the following hexadecimal numbers to binary, octal, and decimal using
the most appropriate conversion method.
(a) 4F
(4F)16 = (0100 1111)2
4 F
001 001 111 = (117)8
1 1 7
4 × 16 + 15 = 64 + 15 = (79)10
(b) ABC
(ABC)16 = (1010 1011 1100)2
A B C
101 010 111 100 = (5,274)8
5 2 7 4
10 × 162 + 11 × 16 + 12 = 2,560 + 176 + 12 = (2,748)10
(c) F8.A7
(F8.A7)16 = (1111 1000 . 1010 0111)2
F 8 A 7
011 111 000 . 101 001 110 = (370.516)8
3 7 0 5 1 6
15×16 + 8 + 10×16-1 + 7×16-2 = 240 + 8 + .625 + .027343750 = (240.6523438)10
(d) 2000
(2000)16 = (0010 0000 0000 0000)2
2 0 0 0
010 000 000 000 000 = (20,000)8
2 0 0 0 0
2×16 = (8,192)10
3

(e) 201.4
(201.4)16 = (0010 0000 0001 . 0100)2
2 0 1 4
001 000 000 001 . 010 = (1001.2)8
1 0 0 1 2
2×16 + 1 + 4×16 = 512 + 1 + .25 = (513.25)10
2 -1

(f) 3D65E
(3D65E)16 = (0011 1101 0110 0101 1110)2
3 D 6 5 E
111 101 011 001 011 110 = (753,136)8
7 5 3 1 3 6
3×164 + 13×163+ 6×162+ 5×16 + 14 = 196,608+2,808+1,536+80+14 = (251,486)10

https://gioumeh.com/product/digital-logic-circuit-analysis-and-design-solution/
12 material is protected under all copyright laws as they currently exist.
© 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This
No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
 Digital Logic Circuit Analysis and Design, 2nd Edition

for download complete version of solution (all chapter 1 to 8 ) click here.

1.8 Find the two's complement of each of the following binary numbers assuming n = 8 .
(a) 101010
N = 00101010
11010101 - complement
+1 - add 1
[N]2 = (11010110)2

(b) 1101011
N = 01101011
10010100 - complement
+1 - add 1
[N]2 = (10010101)2

(c) 0
N = 00000000
11111111 - complement
+1 - add 1
[N]2 = (00000000)2

(d) 11111111
N = 00000000
11111111 - complement
+1 - add 1
[N]2 = (00000000)2

(e) 10000000
N = 10000000
01111111 - complement
+1 - add 1
[N]2 = (10000000)2

(f) 11000
N = 00011000
11100111 - complement
+1 - add 1
[N]2 = (11101000)2

https://gioumeh.com/product/digital-logic-circuit-analysis-and-design-solution/
13 material is protected under all copyright laws as they currently exist.
© 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This
No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.