Your Score:

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The Hashemite University
Computer Engineering Department Final Exam
Digital Logic (110408220) Time: 2 Hours
Sample Final Exam

Student Name: _______________________________

Student ID: _______________________________Section No.: ___________________________

Instructions:
 You are not allowed to use calculators or cell phones.
 You must specify your section number.
 Make sure to fill the answer table shown below clearly.
 There are two bonus questions with 2 points each.
 Please notice that you have one scratch paper on page number10, which will not be graded.

Make sure to answer all 24 exam questions which are distributed among 9 pages.

Part 1 (multiple choice questions):Answers Table (Each with 1.5points)

Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10

Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20

Part 2:
Q21 Q22 Q23(2 pts) Q24(2 pts)
(5 pts) (5 pts) Bonus Question Bonus Question
You score

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1. Convert the following number to hexa: (76.45)8:

a. 3D.A4 b. FE.94 c. 3E.94

d. 314.94 e. None of the above f.

2. The result of the following arithmetic operation assuming 6-bit signed, 2’s complement system is:
1101 – 01011 + 10 = ?? :

a. 100100 b. 110000 c. 000100

d. 1110000 e. Cannot be computed f. Overflow
g. All of the above h. None of the above

3. You have the following number in signed, 2’s complement system: 10011, convert it to signed 1’s
complement system:

a. 01100 b. 1100 c. 11100

d. 00011 e. 10011 f. 10010
g. All of the above h. None of the above

4. The maximum number of codes you get using 5 bits number is:

a. 4 b. 5 c. 16
d. 1024 e. 32 f. 3
g. All of the above h. None of the above

5. The canonical representation of the function F implemented in the following circuit is:
A
B F
C
a. F ( A, B, C )   (0,3,5,6,7) b. F ( A, B, C )   (0,3,5,6) c. F ( A, B, C )   (1,2,4,7)
d. F ( A, B, C )   (1,2,4,7) e. F ( A, B, C )  A.B.C f. F ( A, B, C )  ( A  B  C )'
g. All of the above h. None of the above

6. Simplify F ( A, B, C, D)   (0,2,6,7,10,14)  d (8,12,13,15) as a SOP:

a. B.C' B'.D b. B'.C  B.D' c. A'.B.C' B'.D

d. B.C' A.D  B'.D e. B.C' A.D  A'.B'.D f. None of the above

7. You have a 3-bit adder that has the value of the output C (carry out) equals to 1, the inputs A and
B could be:
a. A = 110, B = 011 b. A = 110, B = 001 c. A = 1110, B = 0011
d. (a) and (b) e. (a) and (c) f. None of the above

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8. The most simplified version of the function F implemented in the following circuit is:
x

z F

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a. F ( x, y, z )  x  y  z b. F ( x, y, z)  x. y' z  x'. y c. F ( x, y, z )  x. y' z  x'. y.z'
d. F ( x, y, z )  1 e. (b) and (c) f. (a) and (b)
g. All of the above h. None of the above

9. A combinational circuit that receives 3 external inputs (x, y, and z where x is the MSB and z is the
LSB). If the value of y is 1 then the output is the XOR of the three inputs. Otherwise (i.e. the value
of y is 0) then the output is a copy of the value of x. The Boolean expression of the output of this
circuit is:
a. x. y' x. y.z  x'. y.z' b. x.( y' z)  x'. y.z' c. x  y  z
d. x e. x  y  z  x f. None of the above

10. The internal design of any multiplexer can be described as:

a. AND-OR circuit b. OR-AND circuit c. NAND-OR circuit
d. One level of minterms e. One level of maxterms. f. None of the above

11. The Boolean expression as a POS of F implemented in the following circuit is (where D3 has the
highest priority in the priority encoder):

a. F ( x, y, z, w)  ( x  y )( y  w) b. F ( x, y, z, w)  ( x  y )( x' y  w)( x' z  w)

c. F ( x, y, z, w)  x'. y' y'.w' x.z'.w' d. F ( x, y, z, w)  ( x  y )( y  w)( x' z  w)
e. F ( x, y, z, w)  0 f. F ( x, y, z, w)  1
g. All of the above h. None of the above

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12. Consider the state table shown below, if the input sequence X = 0111000 what is the output
sequence Z if the starting state is C?
Present state External Input (X)
A 0
A 1
B 0
B 1
C 0
C 1
D 0
D 1
Start
Next state External output (Z)
B 1
A 1
D 0
A 1
C 1
D 0
C 1
A 0

a. Z = 0111011 b. Z = 1001101 c. Z = 0001011

d. Z = 1001010 e. Z = 1000001 f. None of the above

13. The design of counters will be the more efficient and need low number of external gates using:
a. SR latches b. D flip flops c. T flip flops
d. JK Latches e. D latches f. None of the above

14. You are given the following sequential logic circuit, if the present state is Q1 = 0, Q2 = 1 what will
be the values of Q1, Q2, and Z after 3 clock cycles if the applied values of X are as follows: X = 1
in the first and second cycles and X = 0 in the third one:

J1 Q1
X
Z

0 K1
Clear

D2 Q2

clk
a. Q1 = 1, Q2 = 1, Z = 0 b. Q1 = 1, Q2 = 1, Z = 1 c. Q1 = 0, Q2 = 1, Z = 0
d. Q1 = 0, Q2 = 1, Z = 1 e. Q1 = 1, Q2 = 0, Z = 1 f. Q1 = 1, Q2 = 0, Z = 0
g. All of the above h. None of the above

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15. You are given the following state diagram for a sequence detector circuit, which one of the
following sequences is this circuit able to detect where 000 is the initial state?
1/0

1/0
1/0 000
00 0/0
1/0
100 001
01
0/1
0/0 0/0

011
10 010
10
1/0

0/0
a. 00100 b. 11011 c. 0010
d. 1110 e. 11001 f. 00110
g. All of the above h. None of the above

16. You are given the following counter sequential circuit, what is the type of this counter?

1 T0 Q0 T1 Q1 T2 Q2 T3 Q3

clr set clr set clr set clr set

clk

a. Random counter
d. 3 bit up irregular counter
g. 4 bit up irregular counter
Q0
Q1
Q2
Q3
b. 4 bit up regular counter c. 4 bit down regular counter
e. 3 bit down irregular counter f. 4 bit down irregular counter
h. None of the above

17. Which one of the following represents the correct counting sequence of the counter found in
question 16:

a. 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0,1,… b. 10,9,8,7,6,5,10,9,… c. 5,6,7,8,9,5,6,…

d. 0,1,2,3,4,5,6,7,8,9,0,1,… e. 5,6,7,8,9,10,5,6,7… f. 6,7,8,9,6,7,…
g. None of the above

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 18. What is the type of the register implemented in the following sequential circuit?

a. Parallel in/serial out register b. Serial register c. Universal register

d. Parallel register with parallel load. e. Serial in/parallel out register. f. None of the above

19. For the register shown in question 18, how many clock cycles are needed to load the value 10?
a. 2 b. 3 c. 4
d. 1 e. Cannot be determined. f. None of the above

20. If the present states of the flip flips shown next is 111, what will be their states after3 clock pulses?

a. 000 b. 010 c. 100

d. 101 e. 110 f. None of the above

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Q21:You are given the following state diagram for a sequential circuit:
0/01 1/01

1/00 1/00
00 01 10
0/10

0/11

a) (1 pt) How many flip flopsdo you need for this circuit? _____
b) (1 pt) How many external inputs are found in this circuit? ____
c) (1 pt) How many external outputs does this circuit have? ____
d) (1 pt) Assume that you are allowed to use Dflip flops, find the state table of this circuit?

e) (1 pt) Assume that you are allowed to use D flip flops, what are the Boolean equations of all
flip flops inputs?

mplete circuit that represents the state diagram (without the external outputs
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Q22:You are given the following sequential circuit:
x A0 A>B Z
y A1
Magnitude A=B W
1 B0 Comparator
B1 A<B

Q J

Clk

a) (2 pts) Find the state table of this circuit?

b) (1 pt) Find the Boolean expressions of the external outputs (Z and W)?

c) (2 pts) Draw the state diagram of this circuit.

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(2 Bonus questions)
Q23(2 pts): The Boolean expression of Z after analyzing the following circuit is
____________, where X is the MSB input, and Y is the LSB input?

a. Z=YX+YQ' b. Z=Y'X'+YQ
c. Z=Y'X+YQ' d. Z=Y'(X+Q)
e. Z=Y(X+Q) f. Z=Y’X+YQ
g. None of the above.

Q24(2 pts):Construct an 8-to-1 MUX using the minimum possible number of 4-to-1 and 2-to-1
MUXs as building blocks. [2 points]

 GOOD LUCK 

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Name:___________________________ Student ID ________________________
This is a scratch paper (DO NOT DEATTACH )
MUST be submitted and will NOT be graded.

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