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The Hashemite University
Computer Engineering Department
Digital Logic (110408220) Second Exam
Sample Second Exam Time: 60 minutes

Student Name: _______________________________

Student ID: _______________________________Section No.: ___________________________

Instructions:
 You are not allowed to use calculators or cell phones.
 You must specify your section number.
 Make sure to fill the answer table shown below clearly.
 No Questions.
 One scratch paper is given at the end, must be submitted and no additional will be given

Make sure to answer all 14 exam questions which are distributed among 6 pages.

Part 1 (multiple choice questions):Answers Table (Each with 1.5point)

Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12

Part 2:
Q13 Q14
(6 points) (6 points)
You score

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1. Simplify the following function represented by the following K-map:

CD
a. 𝐴′ + 𝐵 + 𝐴𝐵′𝐶′
AB 00 01 11 10
b. 𝐴𝐵′𝐶𝐷′ 00 1 1 X 1
01 1 X 1 1
c. 𝐴 + 𝐵 ′ + 𝐶
11 1 1 1 X
d. 𝐴′ + 𝐵 + 𝐶′ 10 1 X X 0
e. None of the above

2. Simplify the following function:

𝑓 𝐴, 𝐵, 𝐶, 𝐷 = 1,3,5,7,9,12,14 + 𝑑 (8,10,11)

a. 𝐴𝐵 ′ + 𝐴𝐵𝐷′ + 𝐴′𝐷
b. 𝐴′ 𝐷 + 𝐴𝐷′ + 𝐴𝐵′
c. 𝐴′ 𝐷 + 𝐴𝐷′ + 𝐴𝐵′𝐶′𝐷
d. 𝐴𝐵𝐷 + 𝐴′𝐷′
e. None of the above

3. For the function 𝑓 𝐴, 𝐵, 𝐶, 𝐷 = 𝐵𝐷′ + 𝐵 ′ 𝐶𝐷 + 𝐴𝐶′𝐷, what K-map cells will have 0s in them?

a. 0,1,2,5,7,8,10,15 b. 3,4,6,12,13,14,9,11 c. 0,1,2,8,10 d. 5,7,15

e. None of the above

4. What values of X, Y and W will result in F = Z?

a. X=0, Y=0, W=0 I0

0
b. X=0, Y=0, W=1
1 I1 4x1 MUX F
c. X=0, Y=1, W=1
Z I2
d. X=1, Y=1, W=1
Z’ I3 S1 S0
e. None of the above

X S C
Y
Full Adder
W
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5. An 8x3 priority encoderwith active low inputs D0=0, D1=1, D2=0, D3=1, D4=0, D5=1, D6=0,
D7=1. What is the output (A is MSB)?

a. A=1, B=1, C=1, V=1 b. A=1, B=1, C=1, V=0 c. A=1, B=1, C=0, V=1
d. A=0, B=0, C=0, V=1 e. A=1, B=1, C=0, V=0 f. None of the above

6. An Active low SR latch will remember the value 0 when the S-R values are as follows:
a. 00 after 01 b. 00 after 10 c. 11 after 10
d. 11 after 01 e. 01 after 00 f. 10 after 00
g. None of the above

7. The circuit on the right is:

a. Sequential, synchronous, transparent and level-sensitive
b. Sequential, asynchronous, transparent and level-sensitive
c. Sequential, synchronous, transparent and edge-sensitive
d. Sequential, asynchronous, not transparent and edge-sensitive
e. None of the above

8. Consider an8-bit binary adder/subtractor circuit that has the inputs: A = 10111100, B =
01100000, M = 1, then the output is (OV = overflow):
a. S=00011100, OV=0, Cout=1
b. S=00011100, OV=1, Cout=1
c. S=01011100, OV=0, Cout=1
d. S=01011100, OV=1, Cout=1
e. None of the above

9. A J-K flip flop with active low direct RESET and positive edge sensitive has J=0, K=0, RESET= 0.
(Q) will have the following value:
a. 0 on the positive edge b. 1 on the positive edge c. 0
d. 1 e. Cannot be determined f. None of the above

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 Consider the following circuit for answering questions (10 + 11):

B I0
2x1 MUX F1
B F3
I1
C
S0
A
D0
A
D1
B 3x8 D2
Decoder D3
C
D4 F2
D5
D6
E D7

10. What is the simplified Boolean expression of F1?

a. 𝐵 + (𝐵⨁𝐶) b. 𝐵. (𝐵⨁𝐶) c. 𝐴′ 𝐵 + 𝐴𝐵𝐶 ′ + 𝐴𝐵′𝐶

d. 𝐴′ 𝐵 + 𝐵𝐶 ′ + 𝐴𝐵′𝐶 e. 𝐵 ′ 𝐶 + 𝐴′𝐶 f. None of the above

11. If E=0, what is the simplified Boolean expression of F3?

a. 𝑆𝑎𝑚𝑒 𝑎𝑠 𝐹1 b. 𝐵 ′ 𝐶 ′ + 𝐴𝐵𝐶 c. 𝐴′ 𝐵 ′ 𝐶 ′ + 𝐴𝐵 ′ 𝐶 ′ + 𝐴𝐵𝐶

d. 𝐶𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡 𝑜𝑓 𝐹1 e. 𝐵 ′ 𝐶 + 𝐴′𝐶 f. None of the above

12. What is the characteristic equation of a J-K flip-flop?

a. 𝑄 𝑡 + 1 = 𝐽′ 𝑄 + 𝐾𝑄′ b. 𝑄 𝑡 + 1 = 𝐽′ 𝑄 ′ + 𝐾𝑄 c. 𝑄 𝑡 + 1 = 𝐽 + 𝐾
d. 𝑄 𝑡 + 1 = 𝐽𝑄 ′ + 𝐾′𝑄 e. 𝑄 𝑡 + 1 = 𝐽𝑄 + 𝐾′𝑄′ f. None of the above

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13. Given the following clkand Data (D) values that are applied to two different

sequential circuits (a D-Latch, and a D Flip Flop). If you know that the D-Latch is an
active-low enabled latch, and the D Flip Flop is a positive-edge FF, draw the
expected output values Q from these two circuits.

clk

Q
Active low D-Latch

clk

Positive edge D Flip-flop

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14. Design a circuit that takes two 4-bit numbers as inputs (i.e. A = A3A2A1A0, B = B3B2B1B0)
and two control signals (X and Y). If X = 0 then the circuit performs a bitwise logical
ANDing of A and B. If X = 1 and Y = 0 then the circuit addsA to B (i.e. A plus B). If X = 1
and Y = 1 then the circuit subtracts B from A (i.e. A - B).

(Hint: use a 4-bit adder/subtractor and ignore overflow and Cout bits, 2x1 multiplexers,
AND gates ONLY)

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Name: Student ID
This is a scratch paper, MUST be submitted and will NOT be graded.