STAR SMS Synthesis Apnt0304

Synthesis and DFT
APNT - 0304
STAR Memory System® 6.x release
August 2018
Version 2.0
Synthesis and DFT
STAR Memory System 6.x release
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2 Synopsys, Inc. August 2018

Synthesis and DFT
Table of contents
1 Introduction .......................................................................................................................... 5
2 SMS Network Generation ..................................................................................................... 5
3 Clocking and Synchronization .............................................................................................. 9
4 Clock Domain Crossing .......................................................................................................10
5 DFT Operation Table...........................................................................................................11
6 Synthesis and Scan Insertion Procedure .............................................................................13
Wrapper Synthesis and Scan Insertion .......................................................................................................... 13
6.1.1 Wrapper Synthesis and Scan Insertion ................................................................................................ 16
6.1.2 Main Synthesis, RUN_SYN .................................................................................................................. 16
6.1.3 Synthesis Timing Exceptions ............................................................................................................... 17
6.1.4 Compilation Strategy ............................................................................................................................ 17
6.1.5 Scan Insertion and ATPG ..................................................................................................................... 17
Processor Synthesis and Scan Insertion ....................................................................................................... 18
6.2.1 Main Synthesis run_syn ....................................................................................................................... 19
Server Compiler’s JPC and SFP Modules Synthesis and Scan Insertion ...................................................... 21
6.3.1 Main synthesis run_syn ........................................................................................................................ 23
7 Static Timing Analysis .........................................................................................................24

Running Primetime For Wrappers, Processors And Jpc And Sfp Modules.................................................... 24
Netlist Simulation: Gate Level Simulation with SDF Back Annotation ............................................................ 25
8 Appendix A ..........................................................................................................................25
August 2018 Synopsys, Inc. 3

Synthesis and DFT
Revision History
Version Date Note

1.0 April 2015 Migrate and Update
2.0 June 2018 Migrate and Update
Overview
This application note describes the synthesis, scan insertion, fault coverage estimation, ATPG test patterns
generation and netlist simulation concepts, aspects, and techniques used for the SMS Release 6.0. It includes
general information, as well as tool-specific information.

Synthesis and DFT
1 Introduction
This Application Note describes the synthesis, scan insertion, fault coverage estimation, ATPG test patterns
generation and netlist simulation concepts, aspects, and techniques used in the SMS Network Release 6.x. It
includes general information, as well as tool-specific information.
The key steps of the SMS Network EDA Interoperability verification are as follows:
1. Generate memories, Wrappers, Processors, and Server.

2. Bottom-up synthesis of the SMS Network components.
3. Bottom-up scan insertion in the SMS Network components.
4. SMS level STA
5. ATPG
6. Formal equivalence checking of SMS RTL vs. netlist designs.
7. Formal equivalence checking of SMS RTL vs. DFT ready netlist designs.
8. Gate level simulation with SDF annotation.
2 SMS Network Generation

At first the memory instances should be generated via Integrator.
It is necessary to ensure that each of the memories has a MASIS view, which describes the memory information
model and specifies the parameters necessary for SMS Network generation. Before wrapper generation you should
define/customize the SMS Wrapper timing, speed and DFT related options in order for the timing constraints to
comply with the requirements of your design. Customization can be made through the *_custom.glb files (See
Appendix A) of the SMS Network components as well as via the Integrator GUI illustrated below.
The SMS Network clocking and reset options are as follows:
 Memory clock frequency (MHz) mem_clock_freq

 SMS clock (clk_sms) frequency (MHz) clk_sms_freq
 IEEE 1500 clock frequency (MHz) wrck_freq
 Clock multiplexing enable clock_mux_enable
 Enable wrapper level test clock multiplexer wr_test_clock_mux_enable
 SMS Reset type reset_type
mem_clock_freq - The option defines the memory clock frequency in MHz to be reflected in wrapper reference
synthesis scripts as well as in Verilog testbench for post-synthesis simulations.
clk_sms_freq - The option defines the SMS clock (clk_sms) frequency in MHz to be reflected in wrapper reference
synthesis scripts as well as in Verilog testbench for post-synthesis simulations.
 Note: The frequency of SMS clock at STAR Processor level is defined by the frequency of SMS clock
which is slowest among all wrappers’s SMS clocks.
wrck_freq - The option defines the IEEE 1500 clock (WRCK) frequency in MHz to be reflected in wrapper reference
synthesis scripts as well as in the Verilog testbench for post-synthesis simulation. The frequency of IEEE 1500 clock
has to be lower than clk_sms_freq more than 1 times.
 Note: The frequency of IEEE 1500 clock at STAR Processor level is defined by the frequency of WRCK
which is slowest among all wrappers’s WRCK clocks.
clock_mux_enable - If enabled, the option allows generating in the wrapper, a clock multiplexer on the memory
functional clock if the memory does not have a BIST dedicated test clock port. The clock multiplexer is to be controlled
by STAR Processor which automatically will select clk_sms to drive the memory if an instruction different from
BYPASS is applied. The option will be ignored by Wrapper Compiler if the memory has a test clock.
 Note: If the memory does not have a test clock and this option is disabled, clk_sms must be provided
to the memory during SMS BIST operations.

Synthesis and DFT
wr_test_clock_mux_enable - If enabled, the option allows generating in the wrapper a Glitch Free Clock Switching
(GFCS) mechanism for WRCK and clk_sms to have both clocks available at SMS wrapper level and allow users to
connect clk_sms to the local clock source at SMS wrapper level. GFCS is to be controlled by STAR Processor.
reset_type: The reset type of wrapper registers and the active level of rst_sms signal can be manually set during
wrapper configuration via “SMS Reset type” field. Available values are as follows:
1. rst_sms signal is Active Low asynchronous reset and has to remain active for at least 3 (three) WRCK periods.
Both WRCK and clk_sms clocks have to be active during the reset operation. Internal synchronizers are set
on rst_sms signal for both WRCK and clk_sms clock domains and , hence rst_sms signal can not be applied
synchronously to any clock. The wrapper registers have an asynchronous reset.
2. rst_sms signal is Active Low asynchronous reset. rst_sms signal has to be active for at least 3 (three) WRCK
clock cycles. Both WRCK and clk_sms clocks have to be frozen (inactive) during the reset operation and can
be activated only after de-assertion of rst_sms signal. rst_sms signal resets wrapper registers with no
synchronization used. The wrapper registers have an asynchronous reset.
In case if the memory doesn’t have dedicated test clock, and frequencies in test and functional mode are different, a
clock muxing should be added in SMS wrapper by setting the Clock multiplexing enable option value to ‘true’.
Based on these values, the timing constraints and the corresponding input file for STAR Builder are generated.
Figure 1 Wrapper Configurations to Define Clocking and Reset Options

Synthesis and DFT
The SMS Network timing enhancement options are as follows:
 Wrapper input pipeline registers, N pipeline_regs_on_wr_inputs

 Pipe-line output in BIST mode pipe_lined_read
 Pipe-line on BIST-to-memory inputs pipe_lined_bist_inputs
 Pipe-line on error bus pipe_on_err_bus_enable
 RSCOUT negedge flop enable rscout_negedge_enable
pipeline_regs_on_wr_inputs - The option allows to set one and up to 4 stages of pipeline registers on the fast-
clock paths between the processor and wrappers. This option allows extending the processor-to-wrapper path for
up to 3 fast-clock cycle passing distance improving data exchange speed between processor and wrapper.
pipe_lined_read - If enabled, the option generates a pipe-line register on the path from the memory data output to
the BIST logic for timing enhancement. The memory data output functional path is not affected.
pipe_lined_bist_inputs - If enabled, the option generates a stage of pipe-line registers on the path from BIST to
memory inputs (before bist muxes if any) for timing enhancement. This option cannot be disabled for a multi-
instance wrapper (will be enabled automatically).
pipe_on_err_bus_enable - If enabled, the option generates a pipe-line register on the path from interface
modules (data comparator outputs) to the wrapper controller module (error register) for timing enhancement.
rscout_negedge_enable - If enabled, the option sets a negedge flop on the memory reconfiguration register
serial output to resolve hold timing issues on the output propagation paths for particular memories.
Figure 2 Wrapper Configurations to Define Timing Enhancement Options

Synthesis and DFT
The SMS Network DFT options are as follows:
 DFT operations file path dft_ops_file

 External WT mode ext_wt
 Additional DFT coverage (Func. inputs) dft_logic_on_func_inputs
 Enforce Primary Inputs enforce_primary_inputs
dft_ops_file - The option allows defining DFT modes and forcing particular memory inputs as well as wrapper
internal controls to certain values for each DFT mode.
ext_wt - The option allows generating AWT or SWT logic in the wrapper if they are not available in the memory. For
ROM memories, enables generation of ROM Bypass logic (address and control propagation through ROM data
output). If 0, no bypass logic will be generated. If 1 or 2, correspondingly asynchronous or synchronous bypass logic
will be generated in wrapper. dm2, dm1, dm0 wrapper pins are used to enable/disable memory bypass mode in case
when DFT operation modes are declared. In this case the configuration can be defined by user through defining
wt_en_int variable in DFT operation modes.
dft_logic_on_func_inputs - The option generates additional flops on the memory functional control inputs to make
them observable during ATPG scan.
enforce_primary_inputs - The option allows to specify the list of memory input ports that must not be gated in the
wrapper (by DFT related logic). If DFT table option is specified, the memory TestMode ports can be specified in this
list to skip the error message if they are not specified for the DFT insertion mode.
Figure 3 Wrapper Configuration to Define DFT options

Synthesis and DFT
3 Clocking and Synchronization

SMS subsystem provides control over all synchronization issues on the internal and external signals. All signals passing
between slow (WRCK) and fast (clk_sms) clock domains are synchronized with two-stage metastability fli-flops.
Reset synchronizers are implemented on IEEE 1500 interface (WRSTN) reset signals and SMS subsystem (rst_sms)
reset signal.
For both synchronous and asynchronous resets, all synchronization requirements for the reset signal entering the SMS
Network are handled inside the SMS Network components. Data flow diagrams for reset synchronizers with both
synchronous and asynchronous resets are illustrated below.
Figure 4 Reset synchronizers for SRAM Wrapper with asynchronous reset
Figure 5 Reset synchronizers for SRAM Wrapper with synchronous reset

Synthesis and DFT
4 Clock Domain Crossing

In contrast to SMS 5x, where data exchange between fast and slow clock domains happens, in SMS 6x,
due to the clock switching mechanism, communicating components of the system (during data exchange)
are clocked by the same clock signal.
The logic that implements clock switching is called glitch free clock switching mechanism and is shown
below:
Figure 6 Glitch free clock switching mechanism
Clock selection is done by an FSM that is clocked by WRCK slow clock. FSM outputs slow_sel signal which
indicates that either slow or fast clock should be used.
Due to the absence of data exchange between clock domains no constraints specified by set_max_delay
command are needed.
At processor-level, the only CDC exceptions that exist in SMS 6x are false paths from slow clock to fast
clock and vice versa:
set_false_path -from [get_clocks {*clkgrpslow*}] -to [get_clocks {*clkgrp_bist*}]
set_false_path -from [get_clocks {*clkgrp_bist*}] -to [get_clocks {*clkgrpslow*}]
For processor, false paths also exist in fast clock to fast clock paths through specific elements:
set_false_path -from [get_clocks {*clkgrp_bist}] -through [get_pins -quiet -hier -f {full_name =~ *wr_se}] -to
[get_clocks {*clkgrp_bist}]
set_false_path -from [get_clocks {*clkgrp_bist}] -through [get_pins -quiet -hier -f {full_name =~ *wr_si}] -to [get_clocks
{*clkgrp_bist}]
set_false_path -from [get_clocks {*clkgrp_bist}] -through [get_pins -quiet -hier -f {full_name =~ *wr_so}] -to
[get_clocks {*clkgrp_bist}]
set_false_path -from [get_clocks {*clkgrp_bist}] -through [get_pins -quiet -hier -f {full_name =~ *rscen}] -to [get_clocks
{*clkgrp_bist}]
set_false_path -from [get_clocks {*clkgrp_bist}] -through [get_pins -quiet -hier -f {full_name =~ *rscin}] -to [get_clocks
{*clkgrp_bist}]
At wrapper-level, in addition to the fast to slow and slow to fast constraints above, false path constraints from memory
to fast and slow clocks and vice versa exist:
set_false_path -from [get_clocks {clkgrpslow}] -to [get_clocks {clkgrp_mem}]

Synthesis and DFT
set_false_path -from [get_clocks {clkgrp_mem}] -to [get_clocks {clkgrpslow}]

set_false_path -from [get_clocks {clkgrp_mem}] -to [get_clocks {clkgrp_bist}]
set_false_path -from [get_clocks {clkgrp_bist}] -to [get_clocks {clkgrp_mem}]
5 DFT Operation Table

DFT oeprations table is an optional way to have various DFT modes.
DFT operations must be described through TCL commands in a TCL file and the < dft_ops_file> path to this file
is defined to access it. The path must be either an absolute path or a relative to the component (wrapper) folder in
project compout/views directory.
Example (Integrator ISH command):
component wrapper_name set_parameter dft_ops_file

“/remote/john/my_dft_operation_files/sample_dft_operations.tcl”
DFT operations in the TCl file must be specified using the format below:
set dft_op_table(dft_mode_name:dm_pin_values) { memory_port_name:port_value …
wrapper_control_name:ctrl_value}
set dft_insertion_mode dft_insertion_mode_name
where:
dft_mode_name: is the name of a DFT mode to be specified by user.
dm_pin_values: represent the values of dm2, dm1, dm0 signals for which the dft_mode_name DFT mode
should be activated. Note, that 000 is reserved for BIST and functional modes and cannot be specified in DFT
table.
memory_port_name: is the name of memory port to be assigned (forced) to port_value during the DFT mode.
wrapper_control_name: is the name of wrapper special control (see below) signal to be forced to ctrl_value
during DFT mode.
port_value and ctrl_value: are the values to which the memory port or the wrapper internal control signal
must be assigned (forced) during the DFT mode. port_value and ctrl_value can be either binary digits (e.g. 0,
1, 1010, etc.) or “force_active” or “force_inactive”.
In case if “force_active” or “force_inactive” are used, the wrapper will automatically detect the memory port
active level from MASIS (based on ActiveLevel parameter or SafeValue accordingly) or use High (1) and Low
(0) by default in case if the parameters are not specified in MASIS.
dft_insertion_mode_name is the name of the DFT mode for which the scan insertion must be done. The mode
must be set as one of the modes specified by dft_op_table parameter.
Example:
set dft_op_table(bist_basic_ATPG:100) {DFTMODE:1}
set dft_op_table(mem_bypass_ATPG:010) {TD:force_inactive
wr_tclk_en_int:force_active RME:force_active RM:force_inactive
DFTMODE:force_active mem_chain_bypass:force_inactive}
set dft_op_table(non_scan_ATPG:111) {MEB:force_active SE:force_active CD:0 TADR:0}
set dft_insertion_mode bist_basic_ATPG
 Note: For better readability purposes it is allowed to use whitespaces between signal name and value.
Example (DS : force_inactive).

Synthesis and DFT
Setting specific wrapper internal signals in DFT table
If the memory does not have BIST interface on its hard macro, the multiplexers will be set on memory data, address,
control and clock inputs. If the memory does not have internal AWT or SWT function, AWT or SWT function can be
generated in the soft wrapper RTL (see ““External WT mode”” Wrapper compiler option).
In addition, the reconfiguration register in the wrapper can be included in ATPG scan chain and be observable in
predefined DFT modes.
In this case, the following wrapper internal signals can also be defined in dft_op_names array allowing improvement of
ATPG coverage of BIST logic:
scan_mode - Control signal that controls the memory DFT related inputs, enables AWT/SWT, puts the memory
chains into scan mode (sets TestMode signals to active) if the mentioned controls are not specified otherwise in the
DFT table. Additionally, scan_mode if is set active (High) bypasses the reset synchronizers on asynchronous reset if
available in design.
mem_chain_bypass – Control signal available in the DFT table, allows generating additional multiplexers on the
memory chain outputs in the wrapper. If set 1 (or force_active) for particular DFT mode, the memory chains will be
bypassed for that particular mode. Otherwise, if set 0 (or force_inactive) the memory chains will be included into
ATPG scan chain. Not defining this signal for particular DFT mode means the memory chains will not be bypassed for
that DFT mode.
bist_en_int – Control signal to the multiplexer switching memory data, address and control input signals. If set to 1,
the signals from BIST logic take the control over the memory, otherwise, the memory is controlled by the user's input
signals. If this signal is not included in a particular array for particular DFT mode, the signal will be toggling during that
particular mode by default.
tclk_en_int – Control signal to the multiplexer switching the memory clocks. If set to 1, the BIST clock signal is
provided to the memory, otherwise, if set to 0, the functional clock signal is provided to the memory. If this signal is
not included in particular array for particular DFT mode, the signal will be set to 1 during that particular mode by
default.
 Note: During the functional mode this signal is set to 0 to provide the functional clock to the memory.
wt_en_int – Control signal enabling Write Through Mode. If this signal is not included in a particular array for
particular DFT mode, the signal will be set to 1 during that particular mode by default, i.e. Write Through Mode will be
enabled.
wr_tclk_en_int – Control signal to the multiplexer switching clocks to wrapper DFT related sequential logic
(observable flops, SWT, if available). If set to 1, the BIST clock signal is provided to the wrapper DFT related logic,
otherwise, if set to 0, the functional clock signal is provided to the wrapper DFT related logic. If this signal is not
included in particular array for particular DFT mode, the signal will be set to 1 during that particular mode by default.
Note: During the functional mode this signal is set to 1 to provide clk_sms to the wrapper flops.
freeze_rr_int – Control signal protecting the content of reconfiguration register. If set to 1, keeps the content of
reconfiguration register unaffected. Otherwise, if set to 0, releases the reconfiguration register for ATPG scan. If this
signal is not included in particular array for particular DFT mode, the signal will be set to 1 during that particular mode
by default.
To set this signal to 0, freeze_rr_int must be added to the disable list of a DFT mode (see above section). During the
functional and BIST modes, this signal is 0.
Note: DFT table may contain port names that are not available for a particular memory. To avoid the error message,
ignore_dft_table_mpr_errors option must be set “true”. This can be used for specifying DFT table for multiple
memories that have different ports to be specified in DFT table. STAR Wrapper compiler will automatically filter not
relevant ports.

Synthesis and DFT
6 Synthesis and Scan Insertion Procedure
There are two main stages of synthesis and scan insertion using Synopsys DC/DFT Compilers:
 Data preparation
 Block-level synthesis, scan chains insertion and stitching
Synthesis and scan insertion should be run for the following sequence of modules:
 Wrappers
 Processors
 Server
Wrapper Synthesis and Scan Insertion

During wrapper generation, the following tree of synthesis and scan insertion specific files and folders is created:
eda_verify
add_search_pat
constr mem_virt_views test_scripts run_lib run_syn run_pt run_fm run_fm_dft run_tetramax run_all
h.tcl
<WrName>_tim.
std_cells.v mem_lib.tcl
sdc
msff_annot.tcl std_cells.lib wr_syn.tcl
mem_arcs_dis.tc
std_cells.max wr_pt.tcl
l
mem_dt.tcl std_cells.fs_lib wr_dft.tcl
mem_exc.sdc <MemName>.lib tetramax.tcl
<MemName>_ct <MemName>.m create_mem_ctl.

l.tcl ax tcl
<WrName>_int_ <MemName>_at create_wr_int_c

ctl.tcl pg_netlist.v tl.tcl
<WrName>_dft.t
std_lib.tcl
cl
wr_rtl_gate.fms
wr_rtl_postdft.f
ms
Figure 7 Files and Folders tree after wrapper generation

Synthesis and DFT
File name Description
mem_lib.tcl Memory virtual/real timing library compilation script
wr_syn.tcl DC synthesis script for Wrappers
wr_pt.tcl PrimeTime STA script for Wrappers
wr_dft.tcl DFTC scan insertion script for Wrappers
tetramax.tcl Tetramax ATPG script for Wrappers

Main DFTC script, which creates memory CTL model. This file is
create_mem_ctl.tcl
generated when memories’ MASIS view contains IntScanChain section.
DFTC script, which creates CTL model for <wr_name>_int module. This
create_wr_int_ctl.tcl file is generated, when memories’ MASIS description contains
IntScanChain section.
std_lib.tcl Integrated memory std_cells library compilation script
wr_rtl_gate.fms RTL vs. Gate formal equivalence checking script for Synopsys Formality.
RTL vs. Post-DFT formal equivalence checking script for Synopsys
wr_rtl_postdft.fms
Formality.
Table 1: Scripts (test_scripts folder)
< WrName>_tim.sdc Timing constraints for wrappers
msff_annot.tcl Metastability flip-flop’s timing checks annotation files

Memory timing arcs’ timing disabling file for using when compiling
mem_arcs_dis.tcl
wrappers
Memory timing arcs’ timing disabling file for using when compiling
mem_dt.tcl
processor
mem_exc.sdc Memory timing exception file for using when compiling processor
Script identifying the memory test-related pins, constraints and existing
scan chains. This file is generated when memories’ MASIS view
<MemName>_ctl.tcl
contains IntScanChain section and is used in create_mem_ctl.tcl main
script.
Script identifying the <WrName>_int module test-related pins and
< WrName >_int_ctl.tcl constraints. This file is generated when memories’ MASIS view contains
IntScanChain section and is used in create_wr_int_ctl.tcl main script.
Script identifying the <WrName> module test-related pins and
< WrName >_dft.tcl
constraints. This file is used in wr_dft.tcl main script.
Table 2: Constraints and Exceptions (constr folder)
run_lib Library compilation run command file

Synthesis and DFT
run_syn Main synthesis run command file
run_pt PrimeTime STA run command file
run_fm RTL vs. Gate Formality verification run command file
run_fm_dft RTL vs. Post-DFT Formality verification run command file
run_tetramax Run Tetramax script
run_all Runs all “run” command files
add_search_path.tcl Contains search paths for the component runs
.synopsys_dc.setup Synopsys DC setup file
.synopsys_pt.setup Synopsys PT setup file
.synopsys_fm.setup Synopsys FM setup file
.synopsys_lc.setup Synopsys LC setup file

Table 3: Command File and DC/PT/FM Setup
For wrapper synthesis and DFT verification purposes, the following types of virtual memory description files are
required.
1. Memory timing model libraries
2. Memory ATPG netlists
3. Memory Tetramax models
4. Verilog, timing, Tetramax and FastScan models of standard cells library
All of the above-mentioned types are generated based on MASIS description. Those files are located in
eda_verify/mem_virt_views folder. In case if there are no real memory models, these virtual models are used for
verification purposes.

Verilog model of standard cells used in <MemName>_atpg_netlist.v for
std_cells.v
ATPG patterns simulation.
Timing model of standard cells used in <MemName>_atpg_netlist.v for
std_cells.lib
creating memory CTL model.
Standard cells Tetramax model used in <MemName>_atpg_netlist.v for
std_cells.max
Synopsys Tetramax ATPG patterns generation.
Standard cells Mentor ATPG library used in <MemName>_atpg_netlist.v
std_cells.fs_lib
for Mentor Fastscan ATPG patterns generation.
<MemName>.lib Virtual memory timing model library.
<MemName>.max Virtual memory core Tetramax model.

Virtual memory combinational logic netlist Verilog description
(test_input/user_input, bypass). If MASIS contains IntScanChain section,
<MemName>_atpg_netlist.v then <MemName>_atpg_netlist.v contains scan chains description also.
This file provides DFT DRC rules for memory and serves as basis for
memory CTL model generation.
Table 4: mem_virt_views Folder

Synthesis and DFT
6.1.1 Wrapper Synthesis and Scan Insertion
 Preparation of timing model for std_cells library

 Preparation of CTL models for memories
 Preparation of timing models for memories
 Preparation of CTL models for SMS < WrName >_int module
Preliminary SMS synthesis and DFT verification can be done with memory virtual models located in
eda_verify/mem_virt_views folder.
To perform data preparation run run_lib command file from eda_verify directory. As a result, mem_db and logs
folders are created in eda_verify folder. In case if memory MASIS view contains IntScanChain section, mem_ctl
folder will be created also.
Memory CTL models <MemName>.ctl are created based on <MemName>_atpg_netlist.v file and std_cells.lib
library.
mem_db folder contains <MemName>.db compiled timing and test model of the memory. This model is based on the
results of <MemName>.lib and <MemName>.ctl compilation.
mem_ctl folder also contains CTL test model of wrapper’s <WrName>_int module when at least one chain is reused
in the Comparator section. This module will be used for stitching memories shared scan chains (BIST and DFT
modes).
logs folder contains compilation log files.
The above mentioned operation can be done by invoking run_lib script with -virt option. To implement it with real
models run_lib should be run without command line arguments. In this case, the project will be synthesized with real
memory timing model library, path to which should be written manually in <mem_lib.tcl> file in appropriate location.
For Synopsys memories those paths are generated automatically.
Generated memory CTL model is used for scan chain stitching between hard and soft macros. It can be applied as
test model during reading memory Synopsys .lib file. For example,
read_lib <MemoryName>.lib -test_model <MemoryName>.ctl
 Note: Some memories can have shared scan chain for functional and DFT purposes, with shared
ScanEnable and ScanIn inputs. Those memories can be differentiated from MASIS description. For not
shared memories, ports described as ScanEnable and DataScanIn in the MASIS’s IntScanChain section
have tag None.
6.1.2 Main Synthesis, RUN_SYN
To perform the main synthesis run run_syn file from eda_verify directory. It will run synthesis and scan insertion of
wrappers. After compilation, syn_out, syn_out_dft and reports subfolders will be created in eda_verify folder. The
following files will be generated in syn_out folder:
<WrName>_dc.sdc Synopsys Design Constraints (SDC) file for wrapper netlist
<WrName>.ddc Synopsys .ddc of the memory wrapper
<WrName>.vs Memory wrapper netlist

Table 5: Output Files after Synthesis

Synthesis and DFT
Files containing timing and area reports will be generated in reports folder. The synthesis log file will be created in
the logs folder.
6.1.3 Synthesis Timing Exceptions
There are false paths in the design and for some memories there are timing arcs that should be disabled during
synthesis and timing analysis.
The list of these timing exceptions are reflected in the corresponding generated files <WrName>_tim.sdc,
mem_arcs_dis.tcl, mem_dt.tcl, mem_exc.sdc in constr folder. mem_dt.tcl, mem_exc.sdc are used during
processor synthesis. mem_dt.tcl is a PrimeTime script and is dedicated for disabling some timing arcs of the
memory. mem_exc.sdc file is a memory exceptions file for using from SMS level.
6.1.4 Compilation Strategy
Synopsys uses top-down compile strategy for wrappers. Synthesis script is wr_syn.tcl, which is located in the
test_scripts folder.
6.1.5 Scan Insertion and ATPG
Wrapper scan insertion is performed by wr_dft.tcl script which uses < WrName >_dft.tcl constraint file located in
constr folder, and an already generated CTL test model <WrName>_int.ctl and located in the mem_ctl folder. The
sequential run of all the above mentioned scripts can be performed via run_syn file. The following files will be
generated in syn_out_dft folder:

Wrapper scan chain inserted netlist Verilog file. It can be used for ATPG
<WrName>_dft.vs
and test pattern simulation
Wrapper CTL test model. This model can be used for scan insertion from
<WrName>_dft.ctl
upper level
<WrName>_dft.spf Wrapper STIL procedure file for stand-alone wrappers Tetramax ATPG
<WrName>_dft.ddc Synopsys .ddc of the dft-inserted memory wrapper

Table 6: Scan Insertion Output Files
eda_verify
logs mem_db mem_ctl syn_out reports syn_out_dft
Figure 8 Added Files and Folders tree after synthesis’s for wrapper

Synthesis and DFT
Processor Synthesis and Scan Insertion
During Processor generation the following tree of synthesis specific files and folders is created:
eda_verify
constr test_scripts run_wrappers run_syn run_pt run_fm run_fm_dft run_tetramax run_all
<ProcName>_s
mem_lib.tcl
tp_tim.sdc
<ProcName>_s
sms_syn.tcl
ms_tim.sdc
<ProcName>_s
tp_dft_constrai stp_syn.tcl
nts.tcl
msff_annot.tcl sms_pt.tcl
disable_timing
stp_dft.tcl
_proc.tcl
mem_dt.tcl tetramax.tcl
proc_rtl_gate.f
mem_exc.sdc
ms
proc_rtl_postdf
t.fms
area_rpt.tcl
char_pt.tcl
sms_gca.tcl
Figure 9: Files and Folders Tree after Processor Generation
sms_syn.tcl DC synthesis script for SMS
stp_syn.tcl DC synthesis script for Processor
sms_pt.tcl PrimeTime STA script for SMS
stp_dft.tcl DFTC scan insertion script for Processor
tetramax.tcl Tetramax ATPG script for Processor
proc_rtl_gate.fms RTL vs. Gate formal equivalence checking script for Synopsys Formality
proc_rtl_postdft.fms
Formality
area_rpt.tcl Script for generating area reports
char_pt.tcl Area and frequency report (in spreadsheet) generation script
sms_gca.tcl PT Galaxy Constraint Analyzer script

Synthesis and DFT
<ProcName>_sms_tim.sdc Timing constraints for SMS
<ProcName>_stp_tim.sdc Timing constraints for STP

Script which identifies the Processor test-related pins and constraints.
<ProcName>_stp_dft_constraints.tcl
This file is used in stp_dft.tcl main script.
disable_timing_proc.tcl TCL procedure for disabling memory timing arcs
mem_dt.tcl Memory timing arcs’ timing disabling file
mem_exc.sdc Memory timing exception file

run_fm Formality RTL vs. Gate verification run command file
run_fm_dft Formality RTL vs. Post-DFT netlist verification run command file
run_tetramax Run Tetramax script
run_wrappers Wrappers compilation run command file
run_all Runs all “run” run command files
.synopsys_gca.setup PT Galaxy Constraint Analyzer variable setups
6.2.1 Main Synthesis run_syn
After Wrappers compilation is finished, the main synthesis and scan insertion of the Processor can be performed by
running run_syn file from eda_verify directory. This will run synthesis and scan insertion of processor. After
synthesis, folders syn_out and reports will be created in eda_verify. The following files will be generated in syn_out
folder:

Synthesis and DFT
<ProcName>_sms.ddc Synopsys.ddc of the SMS
<ProcName>_sms.vs SMS netlist (wrapper(s) and processor)
<ProcName>_sms_top.vs Processor’s top-level file
<ProcName>_sms_dc.sdc Synopsys Design Constraints (SDC) file for SMS netlist
<ProcName>_stp.ddc Synopsys .ddc of the STP
<ProcName>_stp.vs STP netlist
<ProcName>_stp_dc.sdc Synopsys Design Constraints (SDC) file for STP netlist

Files containing timing and area reports will be generated in the reports folder. The synthesis log file will be created
in the logs folder.
Wrapper synthesis can be run from Processor’s eda_verify folder by running run_wrappers file. If it is preferable to
run the whole process of Wrappers and Processor synthesis and scan insertion from Processor’s eda_verify folder
then run_all file should be run. This run_all file is intended to run all scripts needed to synthesize at first Wrappers
and after that Processor.
There are false paths in the design and for some memories there are timing arcs which should be disabled during
synthesis and timing analysis.
The list of these timing exceptions is reflected in the corresponding generated files <ProcName>_sms_tim.sdc,
<ProcName>_stp_tim.sdc, mem_dt.tcl, mem_exc.sdc in constr folder. mem_dt.tcl and disable_timing_proc.tcl
are PrimeTime scripts and are dedicated for disabling memory some timing arcs. mem_exc.sdc is a memory
exceptions file.
Synopsys uses bottom-up compile strategy for internal verification. For SMS design each wrapper and STP are
compiled separately, and later are incorporated in the top-level design. The top-level constraints are applied and the
whole design is checked for violations. Synthesis scripts stp_syn.tcl and sms_syn.tcl are located in the
test_scripts directory.
To get the complete top-level constraints to be used in customer’s design scripts, STAR Builder’s Script_Gen plug-in
must be used, which is described in the STAR Builder documentation.
eda_verify
logs syn_out reports syn_out_dft
Figure 10: Added Files and Folders Tree after Synthesis’s for Processor

Synthesis and DFT
Processor scan insertion is performed by stp_dft.tcl script which uses <ProcName>_stp_dft_constraints.tcl

constraint file located in constr folder. <ProcName>_stp_dft_constraints.tcl is a DFTC script, which contains dm0,
dm1, dm2 ports, asynchronous reset and test clocks description specific commands for processor scan insertion.
dm0, dm1 and dm2 signals’ values are determined by the corresponding ports value of wrappers. This combination
provides DFT DRC for processor. In case if those ports are missing for all of the wrappers or only dm2 port exists,
DFT DRC for processor is provided by dm2 only. After running stp_dft.tcl script, the following files will be generated
in the syn_out_dft folder:

Processor scan chain inserted netlist Verilog file. It can be used for
<ProcName>_dft.vs
Simulation by ATPG tools
Processor CTL test model. This model can be used for insertion from
<ProcName>_dft.ctl
upper level.
Processor STIL procedure file for stand-alone processor Tetramax
<ProcName>_dft.spf
ATPG
Tetramax simulation and fault coverage estimation is done by tetramax.tcl script. Results are located in
eda_verify/reports/tetramax folder.
Server Compiler’s JPC and SFP Modules Synthesis and Scan Insertion
During JPC/SFP generation, the following tree of synthesis specific files and folders is created:
eda_verify
constr test_scripts run_fm_dft run_fm run_pt run_syn run_tetramax run_dft run_all
jpc_sfp_tim.s
fuse_lib.tcl
dc
jpc_sfp_dft_c jpc_sfp_syn.t
onstr.tcl cl
msff_annot.t
jpc_sfp_pt.tcl
cl
jpc_sfp_dft.tc
l
jpc_sfp_tmax
.tcl
tap.tcl
jpc_gca.tcl
srv_sfp_rtl_g
ate.fms
srv_rtl_postd
ft.fms
Figure 11: Files and Folders Tree after JPC/SFP Generation

Synthesis and DFT
fuse_lib.tcl Efuse library compilation script
jpc_sfp_syn.tcl DC synthesis script for JPC/SFP
jpc_sfp_pt.tcl PrimeTime STA script
jpc_sfp_dft.tcl DFTC JPC/SFP scan insertion script
jpc_sfp_tmax.tcl Tetramax script for fault coverage estimation
tap.tcl Design Compiler script for TAP synthesis
jpc_gca.tcl PT Galaxy Constraint Analyzer script for JPC
srv_sfp_rtl_gate.fms RTL vs. Gate formal equivalence checking script for Synopsys Formality
srv_rtl_postdft.fms
Formality
jpc_sfp_tim.sdc Timing constraints

Script which identifying the JPC/SFP test-related pins and constraints.
jpc_sfp_dft_constr.tcl
This file is used in jpc_sfp_dft.tcl main script
run_fm RTL vs. Gate Formality verification run command file
run_fm_dft RTL vs. Post-DFT Formality verification run command file
run_tetramax Implements test with tetramax
run_dft Scan insertion script
run_all Script that calls all other synthesis-related scripts
.synopsys_gca.setup PT Galaxy Constraint Analyzer variable setups
.synopsys_lc.setup Synopsys LC setup file

Synthesis and DFT
6.3.1 Main synthesis run_syn
To perform the main synthesis run run_syn file from eda_verify directory. It will run synthesis of JPC and SFP
modules. After synthesis, syn_out and reports subfolders will be created in eda_verify folder. The following files will
be generated in syn_out folder:
<ServerName>_jpc_sfp_dc.sdc Synopsys Design Constraints (SDC) file for JPC and SFP netlist
<ServerName>_jpc_sfp_top_dc.sdc
Synopsys Design Constraints (SDC) file for top level netlist
(SMS 6.x only)
<ServerName>_jpc_sfp.ddc Synopsys .ddc of JPC and SFP modules
<ServerName>_jpc_sfp_top.ddc Synopsys .ddc of top-level netlist
<ServerName>_jpc_sfp.vs JPC and SFP netlist
<ServerName>_tap.ddc Synopsys .ddc of TAP netlist
<ServerName>_tap.vs TAP netlist

Files containing timing and area reports will be generated in reports folder files. The synthesis log file will be created
in logs folder.
There are false paths in the design and that should be disabled during synthesis and timing analysis. The list of these
timing exceptions is reflected in the corresponding generated files jpc_sfp_tim.sdc in the constr folder.
Synopsys uses top-down compile strategy for JPC and SFP modules. Synthesis script jpc_sfp_top_syn.tcl is located
in the test_scripts folder.
To get the complete top level constraints to be used in customer’s design scripts, STAR Builder’s Script_Gen plug-in
must be used, which is described in the STAR Builder documentation.
eda_verify
logs syn_out reports syn_out_dft
Figure 12: Added Files and Folders Tree after Synthesis for JPC/SFP

Synthesis and DFT

If SFP module exists then scan insertion is done by jpc_sfp_top_dft.tcl script, which uses
jpc_sfp_top_dft_constr.tcl constraint file located in constr folder. Otherwise, the corresponding files are named
jpc_dft.tcl and jpc_dft_constr.tcl. jpc_sfp_dft_constr.tcl/jpc_dft_constr.tcl is a DFTC script, which contains
dft_mode, asynchronous reset and test clocks description specific commands for processor scan insertion. After
running jpc_sfp_dft.tcl/jpc_dft.tcl script, the following files will be generated in syn_out_dft folder:

Scan chain inserted netlist Verilog file. It can be used for ATPG and test
<ServerName>_jpc_sfp_(top)_dft.vs
pattern simulation
CTL test model. This model can be used for Scan insertion from upper
<ServerName>_jpc_sfp_(top)_dft.ctl
level
<ServerName>_jpc_sfp_(top)_dft.spf STIL procedure file for stand-alone sc_jpc_sfp module Tetramax ATPG
Tetramax simulation and fault coverage estimation is done by jpc_sfp_tmax.tcl/jpc_tmax.tcl script. Results are
located in eda_verify/reports/tetramax folder.
7 Static Timing Analysis
Running Primetime For Wrappers, Processors And Jpc And Sfp Modules
Before performing static timing analysis, ensure that synthesis standard cell library, design and scripts are ready and
paths in the .synopsys_pt.setup file are set correctly.
In order to perform static timing analysis run_pt should be run from eda_verify folder. This step must be done if
further gate level simulation has to be performed, because .sdf data for simulation is being prepared by PrimeTime.
Therefore before project generation, syn_fix_hold_enable parameter must be set to “1” in integrator processor GUI
or _custom.glb file for generating portions of the script related to hold time fixing and preparing .sdf data. After STA
is performed by PrimeTime, the following timing reports will be generated in the reports/timing_bist folder:
check_timing.rpt Possible timing problems for design
timing_max.rpt Maximum path reports
timing_min.rpt Minimum path reports
constraint.rpt Constraints violations
exceptions.rpt Exceptions, ignored exceptions
coverage.rpt Coverage report

Table 17: Output Files after Static Timing Analysis
The pt.log file will be created in logs folder.

Synthesis and DFT
Netlist Simulation: Gate Level Simulation with SDF Back Annotation

In SMS Network design synchronizers were used to transfer signals between different clock domains. Signals
crossing clock boundaries through a synchronizer may experience setup and hold violations. When doing gate-level
simulations on a multi-clock design, the library models of flip-flops are modeled with setup and hold time expressions
to match the timing specifications of the actual flip-flops. Libraries typically model flip-flops to drive “X”s (unknown
values) on the flip-flop outputs when a timing violation occurs. When simulating gate-level synchronizers, setup and
hold time violations might cause libraries to issue setup and hold time error messages and the offending signals are
driven to an “X” value. These “X”-values propagate to the rest of the design causing problems when verifying the
functionality of the gate-level design.
The above-mentioned problem can be solved in the following way:
Using Synopsys PrimeTime command to modify the SDF output for the setup and hold time on just the first stages of
the synchronizers’ flip-flop cells in the design (these are *dwsms_*_met_signal_r and *dwsms_clk2_sel_sync_pr* ):
set_annotated_check 0 -setup –hold –clock rise –from register/clock –to register/data

register/clock – flip-flop instance names and clock pin
register/clock – flip-flop instance names and clock pin
These commands are in the file msff_annot.tcl which is located in the

/compout/views/<ComponentName>/<eda_verify>/constr folder.
To generate SDF files required these portions of code syn_fix_hold_enable parameter must be set to “true” in GUI or
“1” in *custom.glb file.
Gate level simulation is done using the Synopsys VCS simulator. There are corresponding lines in wrappers’,
processor’s and JPC and SFP testbenches that invoke the SDF back annotator. In order to invoke the SDF back
annotator, add the following command from the NCVerilog command line: +define GATE_LEVEL.
`ifdef GATE_LEVEL
//======== sdf annotation block ========================
initial
begin
$sdf_annotate(”<eda_verify/syn_out/ProjName>_ModuleName.sdf”,
<instance_name>);
end
//======== sdf annotation block ========================
`endif
8 Appendix A
Parameters name in glb/$Parameters name in the GUI = $User_value
List of parameters, default values and brief description of usage:
Note: int_verif parameter ( Enable EDA verification in GUI) enables or disables

all synthesis parameters in dialog box. Setting this parameter to false
disables eda_verify folder generation.
Parameters name: int_verif

Parameters name in GUI: Enable EDA verification
Default value: TRUE
Description: Enables or disables synthesis, dft constraints and verification scripts
Parameters name: use_defaults

Parameters name in GUI: Using target library default values
Default value: 1
Description: Setting this parameter to FALSE allows modifying default values

Synthesis and DFT
Parameters name: syn_lib_file_name

Parameters name in GUI: Target library file name
Default value: tcbn28hpbwp35wc
Description: Sets the target library file name
Parameters name: verilog_file_name

Parameters name in GUI: Target library Verilog file name
Default value: tcbn28hpbwp35.v
Description: Sets the target library Verilog file name
Parameters name: syn_lib_name

Parameters name in GUI: Target library name
Default value: tcbn28hpbwp35wc
Description: Sets the target library name
Parameters name: syn_lib_db_path

Parameters name in GUI: Target library db path
Default value: /remote/proj_sp013b/lib/work/tcbn28hpbwp35_100a
Description: Sets the path of target library db file
Parameters name: syn_lib_verilog_path

Parameters name in GUI: Target library Verilog path
Default value: /remote/proj_sp013b/lib/work/tcbn28hpbwp35_100a
Description: Sets the path of target library Verilog file
Parameters name: syn_op_condition

Parameters name in GUI: Operating condition name
Default value: WCCOM
Description: Sets the operating condition name
Parameters name: syn_wire_load_select_group

Parameters name in GUI: Wire load group name
Default value: WireAreaForZero
Description: Sets the wire load group name
Parameters name: syn_driving_cell_name

Parameters name in GUI: Driving cell name
Default value: BUFFD1BWP35
Description: Sets the driving cell name
Parameters name: syn_driving_cell_pin_name

Parameters name in GUI: Driving cell output pin name
Default value: Z
Description: Sets the driving cell output pin name
Parameters name: syn_dont_use_cells

Parameters name in GUI: dont use cell list
Default value: "tcbn28hpbwp35wc/*CKLH*
tcbn28hpbwp35wc/*CKLN*
tcbn28hpbwp35wc/*TIE*
tcbn28hpbwp35wc/*DEL*"
Description: Sets the dont use cell list
Parameters name: syn_wire_load_mode

Parameters name in GUI: Type of wire load mode
Default value: enclosed
Description: Sets the type of wire load mode used for synthesis

Synthesis and DFT
Parameters name: syn_max_fanout

Parameters name in GUI: Max fanout value
Default value: 15
Description: Sets the max fanout
Parameters name: syn_pin_load

Parameters name in GUI: Pin load value
Default value: 0.001
Description: Sets the pin load value
Parameters name: syn_max_transition

Parameters name in GUI: Max transitinon value
Default value: 0.5
Description: Sets the max transitinon
Parameters name: syn_clock_uncertainty

Parameters name in GUI: Clock uncertainty value
Default value: 0.1
Description: Sets the clock uncertainty
Parameters name: syn_input_delay_percent

Parameters name in GUI: Input delay percent
Default value: 0.5
Description: Sets input delay in percentage of clock period for BIST domain
Parameters name: syn_output_delay_percent
Parameters name in GUI: Output delay percent
Default value: 0.5
Description: Sets output delay in percentage of clock period for BIST domain
Parameters name: syn_user_input_delay

Parameters name in GUI: USER domain input delay
Default value: 0.3
Description: Sets input delay for USER domain
Parameters name: syn_user_output_delay

Parameters name in GUI: USER domain output delay
Default value: 0.3
Description: Sets output delay for USER domain
Parameters name: syn_fix_hold_enable

Parameters name in GUI: Enable fix hold violations
Default value: 0
Description: Enables or disables fix hold violations
Parameters name: env_sdc_enable

Parameters name in GUI: Enable *_env.sdc files
Default value: 0
Description: Enables or disables generation of *_env.sdc files
Parameters name: syn_enable_change_names

Parameters name in GUI: Enable change names
Default value: 1
Description: Enables or disables change names before writing netlist
Parameters name: syn_custom_name_rule_file_path

Parameters name in GUI: Customer name rule file path
Default value: ./custom_name_rule

Synthesis and DFT
Description: Sets the path of customer name rule file
Parameters name: syn_rule_name

Parameters name in GUI: Name rule
Default value: verilog
Description: Specifies a name rule
Parameters name: en_rec_rem_check

Parameters name in GUI: Enable DC recovery and removal timing checks
Default value: 1
Description: Enables or disables Synopsys DC recovery and removal timing check
Parameters name: smscdc

Parameters name in GUI: -
Default value 0
Description: Create a set of duplicate CDC clocks in parallel to the normal SMS and
IEEE1500 clocks, but make them ideal.

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Synthesis and DFT

STAR Memory System® 6.x release

Copyright Notice and Proprietary Information

2 Synopsys, Inc. August 2018

7 Static Timing Analysis .........................................................................................................24

August 2018 Synopsys, Inc. 3

Version Date Note

4 Synopsys, Inc. August 2018

1. Generate memories, Wrappers, Processors, and Server.

2 SMS Network Generation

The SMS Network clocking and reset options are as follows:

 Memory clock frequency (MHz) mem_clock_freq

August 2018 Synopsys, Inc. 5

Figure 1 Wrapper Configurations to Define Clocking and Reset Options

6 Synopsys, Inc. August 2018

The SMS Network timing enhancement options are as follows:

 Wrapper input pipeline registers, N pipeline_regs_on_wr_inputs

Figure 2 Wrapper Configurations to Define Timing Enhancement Options

August 2018 Synopsys, Inc. 7

The SMS Network DFT options are as follows:

 DFT operations file path dft_ops_file

Figure 3 Wrapper Configuration to Define DFT options

8 Synopsys, Inc. August 2018

3 Clocking and Synchronization

Figure 4 Reset synchronizers for SRAM Wrapper with asynchronous reset

Figure 5 Reset synchronizers for SRAM Wrapper with synchronous reset

August 2018 Synopsys, Inc. 9

4 Clock Domain Crossing

Figure 6 Glitch free clock switching mechanism

set_false_path -from [get_clocks {clkgrpslow}] -to [get_clocks {clkgrp_mem}]

10 Synopsys, Inc. August 2018

set_false_path -from [get_clocks {clkgrp_mem}] -to [get_clocks {clkgrpslow}]

5 DFT Operation Table

Example (Integrator ISH command):

component wrapper_name set_parameter dft_ops_file

August 2018 Synopsys, Inc. 11

Setting specific wrapper internal signals in DFT table

12 Synopsys, Inc. August 2018

6 Synthesis and Scan Insertion Procedure

Wrapper Synthesis and Scan Insertion

msff_annot.tcl std_cells.lib wr_syn.tcl

mem_dt.tcl std_cells.fs_lib wr_dft.tcl

mem_exc.sdc <MemName>.lib tetramax.tcl

<MemName>_ct <MemName>.m create_mem_ctl.

<WrName>_int_ <MemName>_at create_wr_int_c

Figure 7 Files and Folders tree after wrapper generation

August 2018 Synopsys, Inc. 13

File name Description

mem_lib.tcl Memory virtual/real timing library compilation script

wr_syn.tcl DC synthesis script for Wrappers

wr_pt.tcl PrimeTime STA script for Wrappers

wr_dft.tcl DFTC scan insertion script for Wrappers

tetramax.tcl Tetramax ATPG script for Wrappers

File name Description

< WrName>_tim.sdc Timing constraints for wrappers

msff_annot.tcl Metastability flip-flop’s timing checks annotation files

File name Description

run_lib Library compilation run command file

14 Synopsys, Inc. August 2018

run_syn Main synthesis run command file

run_pt PrimeTime STA run command file

run_fm RTL vs. Gate Formality verification run command file

run_fm_dft RTL vs. Post-DFT Formality verification run command file

run_tetramax Run Tetramax script