STAR Mem System Integration Apnt0235

STAR Memory System integration
STAR Memory System 4.x, 5.x, 6.x
July 2018
Version 2.0
SMS integration flow
STAR Memory System 4.x, 5.x, 6.x release
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2 Synopsys, Inc. July 2018

Revision 2.0
Revision History
Version Date Note

1.0 November 4, 2014 Initial version, Narine Martirosyan
2.0 July 2018 Review and update
July 2018 Synopsys, Inc. 3

Revision 2.0
Table of Contents
1 Introduction ............................................................................................................................................................. 5
2 The SMS integration flow into the design ................................................................................................................5
3 Test scenario .......................................................................................................................................................... 5
3.1 Design file set ..................................................................................................................................................5
3.2 Libraries used in the RTL design ..................................................................................................................... 6
3.3 Design Partitioning ...........................................................................................................................................6
4 Read design ............................................................................................................................................................ 6
4.1 Examples ......................................................................................................................................................... 7
4.1.1 Creating workspace “encoder” ...............................................................................................................7
4.1.2 Compiling down_sampling library ...........................................................................................................7
4.1.3 Compiling deinterleave library ................................................................................................................7
4.1.4 Reading encoder design as SubChip/SoC ............................................................................................. 7
4.1.5 Closing workspace .................................................................................................................................7
5 Extract memory instances hierarchy ....................................................................................................................... 8
5.1 Examples ......................................................................................................................................................... 8
5.1.1 Input file content .....................................................................................................................................8
5.1.2 Output file content ..................................................................................................................................8
6 Create SMS project .................................................................................................................................................9
6.1 Examples ......................................................................................................................................................... 9
7 Integrate SoC/Sub-chip ......................................................................................................................................... 10
7.1 Examples ....................................................................................................................................................... 11
7.1.1 Creating/Integrating “down_sampling” SubChip ................................................................................... 11
7.1.2 Creating/Integrating “deinterleaving” SubChip ..................................................................................... 11
7.1.3 Creating/Integrating “conversion” SubChip .......................................................................................... 12
7.1.4 Creating/Integrating “encoder” SoC ...................................................................................................... 12
8 Known limitations for Builder 2014.09 for Macro usage ........................................................................................ 13
8.1 If macro is defined in separate file ................................................................................................................. 13
8.2 If macro defines the module port list .............................................................................................................. 13
9 Quick Verification of the integrated RTL design .................................................................................................... 13
9.1 Examples ....................................................................................................................................................... 13
9.1.1 SubChip simulation .............................................................................................................................. 13
9.1.2 SoC simulation ..................................................................................................................................... 13
10 General Post-insertion verification means generated by Builder (Yield Accelerator and Builder) .................. 14
10.1 design.lst, design_sv.lst and design_vhdl.lst ............................................................................................. 14
10.2 hier_names.txt .......................................................................................................................................... 14
10.3 <server_name>_uds.uds .......................................................................................................................... 14
10.4 <server_name>_ chip_param.cpf ............................................................................................................. 14
10.5 hier_names_sms.txt .................................................................................................................................. 14

Revision 2.0
1 Introduction
This application note is intended to outline the SMS integration flow into the RTL design. The goal is to provide
Builder tool commands user needs to run to compile necessary libraries, read the RTL design, create SMS project,
and integrate the SMS into the RTL design. Builder allows to accomplish the integration via GUI, where all the steps
performed in the STAR Builder GUI are journalized in the <project_name>_rcl.log file. By using Builder shell and
rcl.log file the same GUI actions can be reproduced.
2 The SMS integration flow into the design

The block diagram below shows the steps to be accomplished to achieve the SMS integration into the RTL design.
Read Design
Extract memory instances hierarchy
Create SMS project
Integrate SoC/Subchip
Verification of the integrated RTL design
Figure 1 SMS integration
3 Test scenario
This section describes the test scenario that is considered through this document. The test case contains RTL design
with VHDL/SVerilog/Verilog mixed. Please note that there is no test case attached to this document, and file names
are given as examples.
3.1 Design file set

File name Description
S256x64_MEM.v Sverilog S256x64_MEM memory model
common.v Verilog file, defines “common” memory functional wrapper module instantiating
S512x64_MEM
encoder_top_cfg.vhd VHDL file, RTL design top configuration file defining the bindings
encoder_top.vhd VHDL file, RTL design top entity/architecture. Here all the blocks are instantiated

Revision 2.0
encoder_top.v Verilog file, defines module which is instantiated in the encoder_top.vhd. Here one
S256x64_MEM is instantiated
deinterlieaving_cfg.vhd VDHL encoder configuration, provides the bindings
deinterlieaving.vhd VHDL encoder entity/architecture. Here “common” module is instantiated
deinterlieaving.v Verilog file, defines module which is instantiated in the encoder.vhd
down_sampling.vhd VHDL down_sampling entity/architecture. Here “common” module is instantiated
down_sampling.v Verilog file, defines the module which is instantiated in the down_sampling.vhd
conversion.v Verilog file, defines the module which is instantiated in the encoder_top.
conversion_ctrl.v Verilog file, defines internal logic for the color conversion block. Here one
S1024x64_MEM is instantiated
Table 1 RTL Design files list
3.2 Libraries used in the RTL design

Partitions “deinterleaving” and “down_sampling“ will be compiled into the separate libraries named correspondingly.
“encoder_top” will be compiled into the “encoder_top” library, which depends on the libraries “deinterleaving and
“down_sampling”.
3.3 Design Partitioning

deinterleaving, conversion, down_sampling – to be different SubChips.
encoder_top – to be SoC.
encoder_top (SoC)
deinterleaving down_sampling conversion
(VHDL/Verilog/SVerilog) (VHDL/Verilog/SVerilog) (Verilog/Sverilog)
S256x64_MEM
S512x64_MEM S512x64_MEM S1024x64_MEM
Figure 2 RTL design partitioning
4 Read design
Builder configuration RTL Design file set Design options
Read Design (Builder)
Builder
Database
.
Figure 3 Design Read

Revision 2.0
Figure 3 above, shows the RTL read diagram. The input blocks used in the figure are described below:
Builder configuration - includes Builder project options, such as Enable DC SMS Parser, Enable Comments, and
path to the compout directory, etc.
RTL Design file set - design files grouped by HDL type should be provided.
Design options – these sets include information as VHDL libraries to be compiled/used, macros definitions, include
directories, etc.
The result of the RTL design read is the Builder Database loaded.
The very first step is to read RTL design into the Builder Database. If RTL design uses libraries, then libraries should
be built prior to SMS integration.
For this purpose, the RTL design file set needs to be provided, so those can be analyzed. Here any additional
information necessary for the design processing should be provided such as include directories, VHDL top
configuration, libraries names and storage location, etc.
The section below represents the steps to be performed to read the RTL.
4.1 Examples
The examples below explain the “down_sampling” and “deinterleave” libraries compilation. Once the libraries are built
and stored, the SubChip/SoC will be created to read the RTL design. This code can be used for tasks like the
extraction of memory instances hierarchies.
Note that codes from the sections below should be sequentially performed in one RCL file.
4.1.1 Creating workspace “encoder”

set wks_tcl [workspace new "encoder"]
workspace $wks_tcl enable_dc_sms_parser
4.1.2 Compiling down_sampling library

set tmp_tcl [workspace $wks_tcl add_library "down_sampling" -vhdl “down_sampling.vhd” –sverilog
“S512x64_MEM.v” “common.v” –verilog “down_sampling.v”]
library $tmp_tcl store_design_lib down_sampling ./lib_down_sampling
library $tmp_tcl read
4.1.3 Compiling deinterleave library

set tmp_tcl [workspace $wks_tcl add_library "deinterleave" -vhdl “deinterleave.vhd” “deinterleave_cfg.vhd” –sverilog
“S512x64_MEM.v” “common.v” –verilog “deinterleave.v”]
library $tmp_tcl store_design_lib deinterleave ./lib_deinterleave
library $tmp_tcl top_configuration_name "deinterleave_cfg"
4.1.4 Reading encoder design as SubChip/SoC

set subchip_tcl [workspace $wks_tcl add_subchip "encoder_top" –vhdl “encoder_top.vhd” “encoder_top_cfg.vhd”
–sverilog “S256x64_MEM.v”–verilog “encoder_top.v” “conversion.v” “conversion_ctrl.v”]
subchip $tmp_tcl add_vhdl_library down_sampling ./lib_down_sampling
subchip $tmp_tcl add_vhdl_library deinterleave ./lib_deinterleave
subchip $tmp_tcl store_design_lib encoder_top ./lib_encoder_top
subchip $tmp_tcl top_configuration_name "encoder_top_cfg"
subchip $subchip_tcl read
4.1.5 Closing workspace

workspace close $wks_tcl
Note: Each library/SubChip/SoC that depends on other libraries should be created in the same workspace where the
other libraries were read. In the example above, “down_sampling” and “deinterleave” libraries compilation is done in
the workspace named “encoder”. Note that in the same workspace the “encoder_top” SubChip/SoC is created.

Revision 2.0
5 Extract memory instances hierarchy

Builder configuration RTL Design file set Design options Memories set
Extract Memory instances hierarchy (Builder)
File containing list of the

memory instances
Figure 4 Extract Memory instances
The diagram above represents the necessary information to provide to Builder tool to analyze the RTL design and
output the memory instances information.
Here are the input blocks descriptions:
Builder configuration - includes Builder project options, such as Enable DC SMS Parser, Enable Comments, and
path to the compout directory, etc.
Design options – these sets include such information as VHDL libraries to be compiled/used, macros definitions,
include directories, etc.
Memories set – is the file containing list of the memories to be analyzed by Builder.
The output is the file containing information on the instances hierarchical path in the RTL design. This file also
contains information on whether the particular memory is instantiated in the RTL design.
Builder “Extract Hierarchical Paths” options dumps the memory instances hierarchy into the user specified file.
Once the RTL design is read, the following line will output the memory instances:
subchip $tmp_tcl extract_instances existing_file_mem_list output_ext_mem
where,
existing_file_mem_list - is the file containing memories list to be analyzed.
output_ext_mem – is the output file containing the RTL design memory instantiations path.
5.1 Examples
5.1.1 Input file content

S256x64_MEM
S512x64_MEM
S1024x64_MEM
5.1.2 Output file content

S256x64_MEM:
encoder_top.enc_mem1
S512x64_MEM:
encoder_top.i_deinterleaving.mem1
encoder_top.i_down_sampling.mem1
S1024x64_MEM:encoder_top.i_conversion.conv_mem1
In the output file all the memories used in the RTL design can be found. Per each memory instantiation the full
hierarchical path is provided.

Revision 2.0
6 Create SMS project

Components configuration Compilers storage
Create SMS project (Integrator)
SMS project generated
Figure 5 Create SMS project

The diagram above shows the inputs and outputs for the Integrator tool.
Components info - components to be created and their configuration
Compilers storage - location where all the necessary components compilers are located.
SMS project generated - the result is the generated SMS project.
Integrator allows to configure and to create Memories, Wrappers, Processors and Server components.
6.1 Examples
The block diagram below represents an example on how the SMS project can be architected for the “encoder_top”
design.
encoder_top
(server)
deinterleaving
(processor)
wrap_S512x64_1
(wrapper)
down_sampling S512x64_MEM
(processor) (memory)
wrap_S512x64_2
(wrapper)
conversion
(processor) S512x64_MEM
(memory)
wrap_S1024x64
(wrapper)
encoder
(processor) S1024x64
(memory)
wrap_S256x64
(wrapper)
S256x64_MEM
(memory)
Figure 6 Design Hierarchy
Here 3 processors are created named correspondingly to the partitioning provided in the section 3. “Test Scenario”.
“deinterleaving” and “down_sampling“ are the processors dedicated for the VHDL/Verilog/SVerilog mixed partitions,

Revision 2.0
and “conversion” is the processor dedicated for Verilog/Sverilog partition only. These 3 blocks will be designed as
separate SubChips/processor.
The processor “encoder” is designed to be added to the SoC level as flat. It’s dedicated for the S256_MEM memory
integration.
Note that S512x64_MEM memory is reused for the processors “deinterleaving” and “down_sampling“.
7 Integrate SoC/Sub-chip
Builder configuration RTL Design file set Design options SMS project
Integrate SMS into the RTL design (Builder)
SMS integrated into the

RTL design
Figure 7 SMS integration
The block diagram represents data to be provided to Builder tool.

Builder configuration - includes the Builder project options, such as Enable DC SMS Parser, Enable Comments,
and path to the compout directory, etc. The integration design block level information also should be provided here,
such as whether it is SubChip or SoC.
Design options – these set includes such information as VHDL libraries to be compiled/used, macros definitions,
include directories, etc.
SMS project – is the path to the “compout” directory.
Once the RTL design has been read into Builder Database and SMS project is ready (section Read Design),
integration can be started. The integration can be carried out at two levels: SubChip and SoC.
The Subchip can be integrated into the other SubChips or SoC.
Note: After adding Wrappers, Top Wrapper should be added over if:
- SMS project contains shared Wrapper
- Memory is set to Wrapper side by side
Note: Default top level port names can be modified and tie-off values can be set up for test ports.
Note: During SMS addition to SubChip, Subchip level top connections should be specified for
IEEE1500ports.
Note: In case internally connected pins have to be visible as top pins, their top port mapping should be provided, e.g.
this rule affects clk_sms. This will allow Builder to correctly generate the constraints.

Revision 2.0
7.1 Examples
Please note that the same compout directory should be used in all the SubChips/SoC creation.
7.1.1 Creating/Integrating “down_sampling” SubChip

set wks_tcl [workspace new "down_sampling"]
workspace $wks_tcl compout_dir “path_to_compout"
set tmp_tcl [workspace $wks_tcl add_subchip "down_sampling" -vhdl “down_sampling.vhd” –sverilog
subchip $tmp_tcl store_design_lib down_sampling ./lib_down_sampling
subchip $tmp_tcl read
set tmp_tcl_wrap [subchip $tmp_tcl add_wrapper …]

set tmp_tcl_sms [subchip $tmp_tcl add_sms …]
…
wrapper $tmp_tcl_wrap insert
sms $tmp_tcl_wrap insert
# “enable_modify_copied_files” command provides file uniquification.

# This means that all the files that are affected by integration
# will be copied and renamed.
# This command is used as there is file “common.v” used by
# downsampling and deinterleaving SubChips.
subchip $tmp_tcl enable_modify_copied_files
# "add_module_prefix" command adds the specified prefix to all

# Verilog modules and VDHL entities in the design tree.
# -only_edited option allows to rename only those modules/entities which are
# affected by the integration.
subchip $tmp_tcl add_module_prefix down_sampling_ -only_edited
subchip $tmp_tcl write

7.1.2 Creating/Integrating “deinterleaving” SubChip

set wks_tcl [workspace new "deinterleave"]
set tmp_tcl [workspace $wks_tcl add_subchip "deinterleave" -vhdl “deinterleave.vhd” “deinterleave_cfg.vhd” –sverilog
subchip $tmp_tcl store_design_lib deinterleave ./lib_deinterleave
subchip $tmp_tcl top_configuration_name " deinterleave_cfg"

…
# "enable_modify_copied_files" commands provides file uniquification.

# This means that all the files that are affected by integration
# will be copied and renamed.
# This command is used as there is file “common.v” used by
# down_sampling and deinterleaving SubChips.
# "add_module_prefix" command adds the specified prefix to all

# Verilog modules and VDHL entities in the design tree.
# -only_edited option allows to rename only those modules/entities which are
# affected by the integration.
subchip $tmp_tcl add_module_prefix deinterleave _ -only_edited


Revision 2.0
7.1.3 Creating/Integrating “conversion” SubChip

set wks_tcl [workspace new "conversion"]
set tmp_tcl [workspace $wks_tcl add_subchip "conversion" –sverilog “S1024x64_MEM.v” –verilog “conversion.v”
“conversion_ctrl.v”]

…

7.1.4 Creating/Integrating “encoder” SoC

set wks_tcl [workspace new "encoder"]
set tmp_tcl [workspace $wks_tcl add_library "down_sampling" -vhdl “down_sampling.vhd” –sverilog

library $tmp_tcl store_design_lib down_sampling ./lib_down_sampling
set tmp_tcl [workspace $wks_tcl add_library "deinterleave" -vhdl “deinterleave.vhd” “deinterleave _cfg.vhd” –sverilog
library $tmp_tcl store_design_lib deinterleave ./lib_deinterleave
library $tmp_tcl top_configuration_name " deinterleave_cfg"
set subchip_tcl [workspace $wks_tcl add_soc "encoder_top" –vhdl “encoder_top.vhd” “encoder_top_cfg.vhd” –

sverilog “S256x64_MEM.v” –verilog “encoder_top.v”]
subchip $tmp_tcl add_vhdl_library down_sampling ./lib_down_sampling
subchip $tmp_tcl add_vhdl_library deinterleave ./lib_deinterleave
subchip $tmp_tcl store_design_lib encoder_top ./lib_encoder_top
subchip $tmp_tcl top_configuration_name "encoder_top_cfg"
workspace $wks_tcl import_subchips "." "down_sampling" "down_sampling_top_module_name"

workspace $wks_tcl import_subchips "." "deinterleave" "deinterleave_top_module_name"
workspace $wks_tcl import_subchips "." "conversion" "conversion_top_module_name"
# "enable_modify_copied_files" commands provides file uniquification. This means

# that all the files that are affected by the integration will be copied and renamed.
subchip $subchip_tcl read

set tmp_tcl_server [subchip $tmp_tcl add_server …]

sms $tmp_tcl_sms insert
server $tmp_tcl_server insert
subchip $luminor_core_tcl write

Revision 2.0
8 Known limitations for Builder 2014.09 for Macro usage
8.1 If macro is defined in separate file

If a macro is defined in a file that isn’t included in any RTL files, then the file containing macro definition should be
specified while reading a design. Note that in this case the following steps should be performed:
1. When defining the file set used to read a design, the files containing macro definitions should be provided
before the RTL files using those macros.
2. enable_single_dc_analyze command should be used:

> subchip $tmp_tcl enable_single_dc_analyze
8.2 If macro defines the module port list

Currently the incorrect RTL syntax will be generated in case if:
- Macro defines the port:
`define my_macro ,input data
module top (input clk `my_macro);
- Macro defines parenthesis or semicolon, or both together.

The parenthesis example is given below:
`define parenth )
module top(input clk, input data `parenth ;
9 Quick Verification of the integrated RTL design

Once the SMS project is integrated into the RTL design, the verification environment can be generated. SubChip and
SoC level verification are supported. For SubChip and SoC level integrity checking, testbench and simulation
environment will be generated. For SubChip level, additional production tests will be generated.
9.1 Examples
9.1.1 SubChip simulation

set wks_tcl [workspace open "downsampling"]
set tmp_tcl [workspace $wks_tcl get_subchip]
subchip $tmp_tcl generate_simulation_scripts "sim_downsampling/"
9.1.2 SoC simulation

set wks_tcl [workspace open "encoder"]
set tmp_tcl [workspace $wks_tcl get_soc]
subchip $tmp_tcl generate_simulation_scripts "sim_encoder/"

Revision 2.0
10 General Post-insertion verification means generated by

Builder (Yield Accelerator and Builder)
This sub-section is dedicated to showcase the inputs for the post-insertion verification generated by Builder tool. After
insertion is done, Builder can generate design verification related files. These files can be used by Verifier, Vecgen,
Yield Accelerator (si_debug) tools for test-benches generation.
Builder
design.lst
design_sv.lst hier_names.txt UDS CPF
design_vhdl.lst
Manual change
is needed
Testbench Generation (Yield Accelerator, Vecgen, Verifier)
Chip level testbench and simulation environment
Figure 8 Testbench generation
10.1 design.lst, design_sv.lst and design_vhdl.lst

The design list files contain Verilog/SVerilog/VHDL files from compout and RTL design. These files are used by other
tools to generate the testbench and simulation environment.
10.2 hier_names.txt
This file contains the hierarchical path information of memory instances. This information is necessary for fault
injection mechanism.
10.3 <server_name>_uds.uds
SMS project contains the uds files, which is created during the components generation in the compout directory.
Builder can generate the updated uds file by using the compout data by adding SMS related sections. Also sections
for signals and sequence are updated according to the RTL design data.
Manual changes are required to be done in order to fix the TAP related input/output definition in uds files. The
changes should apply to the following ports definition: tdo, tdi, tck, tms, trstn. Also the sequences here are defined by
using these signals, which may need to be changed. Also please make sure that uds file doesn’t contain TAP related
signals defined as e.g.“input tck”.
10.4 <server_name>_ chip_param.cpf

SMS project contains the cpf file, which contains chip parameters definition. The parameters used in cpf file are
described in the Yield Accelerator documentation. Here all the parameters can be changed by user to achieve
necessary results, e.g. TCK_SHAPE, SMS_CKL_PERIOD, etc.
10.5 hier_names_sms.txt
This file provides hierarchical path information of processor, wrapper and memory instances. This is used to show
SMS hierarchy view from the top in Yield Accelerator tool.

Revision 2.0

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STAR Memory System integration

STAR Memory System 4.x, 5.x, 6.x

Copyright Notice and Proprietary Information

2 Synopsys, Inc. July 2018

Version Date Note

July 2018 Synopsys, Inc. 3

4 Synopsys, Inc. July 2018

2 The SMS integration flow into the design

Extract memory instances hierarchy

Create SMS project

Verification of the integrated RTL design

Figure 1 SMS integration

3.1 Design file set

S256x64_MEM.v Sverilog S256x64_MEM memory model

S512x64_MEM.v Sverilog S512x64_MEM memory model

S1024x64_MEM.v Sverilog S1024x64_MEM memory model

July 2018 Synopsys, Inc. 5

deinterlieaving_cfg.vhd VDHL encoder configuration, provides the bindings

deinterlieaving.vhd VHDL encoder entity/architecture. Here “common” module is instantiated

deinterlieaving.v Verilog file, defines module which is instantiated in the encoder.vhd

down_sampling.vhd VHDL down_sampling entity/architecture. Here “common” module is instantiated

3.2 Libraries used in the RTL design

3.3 Design Partitioning

Figure 2 RTL design partitioning

Read Design (Builder)

Figure 3 Design Read

6 Synopsys, Inc. July 2018

4.1.1 Creating workspace “encoder”

4.1.2 Compiling down_sampling library

4.1.3 Compiling deinterleave library

4.1.4 Reading encoder design as SubChip/SoC

4.1.5 Closing workspace

July 2018 Synopsys, Inc. 7

5 Extract memory instances hierarchy

Extract Memory instances hierarchy (Builder)

File containing list of the

Figure 4 Extract Memory instances

5.1.1 Input file content

5.1.2 Output file content

8 Synopsys, Inc. July 2018

6 Create SMS project

Create SMS project (Integrator)

SMS project generated

Figure 5 Create SMS project

Figure 6 Design Hierarchy

July 2018 Synopsys, Inc. 9

Integrate SMS into the RTL design (Builder)

SMS integrated into the

Figure 7 SMS integration

The block diagram represents data to be provided to Builder tool.

10 Synopsys, Inc. July 2018

7.1.1 Creating/Integrating “down_sampling” SubChip

set tmp_tcl_wrap [subchip $tmp_tcl add_wrapper …]

# “enable_modify_copied_files” command provides file uniquification.

# "add_module_prefix" command adds the specified prefix to all

subchip $tmp_tcl write

7.1.2 Creating/Integrating “deinterleaving” SubChip

set tmp_tcl_wrap [subchip $tmp_tcl add_wrapper …]

# "enable_modify_copied_files" commands provides file uniquification.

# "add_module_prefix" command adds the specified prefix to all

subchip $tmp_tcl write

July 2018 Synopsys, Inc. 11

7.1.3 Creating/Integrating “conversion” SubChip

set tmp_tcl_wrap [subchip $tmp_tcl add_wrapper …]