Lecture 3

Fault Models

Usha Gogineni
7th August 2023
Review Questions
Question 1: What does "ATE" stand for in the context of VLSI testing?
Question 2: What is the purpose of Automatic Test Equipment (ATE) in VLSI testing?
a) To design VLSI circuits
b) To manufacture VLSI chips
c) To perform functional testing on VLSI devices
d) To analyze VLSI market trends
Question 3: Which type of ATE is used for testing analog and mixed-signal circuits in VLSI?
a) Digital ATE
b) FPGA-based ATE
c) RF ATE
d) Memory ATE
Question 4: True or False - Probe cards are used for testing packaged VLSI devices on the wafer directly.
Question 5: Which approach is commonly used to balance test cost and quality in VLSI testing?
a) Conducting exhaustive testing on all VLSI devices
b) Reducing test coverage to minimize cost
c) Utilizing statistical sampling for testing
d) Eliminating all functional tests
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Review Questions
Question 6: True or False - ATE systems are only used for wafer-level testing and not for packaged VLSI devices.
Question 7: What is the primary function of a tester interface board (TIB) in ATE systems?
a) To provide a user interface for operating the ATE
b) To serve as a connector between the device under test and the ATE
c) To process and analyze test data
d) To generate test patterns for VLSI devices
Question 8: What is the significance of burn-in testing in VLSI manufacturing?
a) To validate the design of VLSI circuits
b) To test VLSI devices under high-temperature conditions to identify early failures
c) To test VLSI devices for their functional correctness
d) To test VLSI devices for their power consumption
Question 9: What is the primary goal of Design for Testability (DFT) techniques in VLSI design?
a) To ensure that VLSI devices can only be tested by expensive equipment
b) To make VLSI devices immune to manufacturing defects
c) To enhance the manufacturability of VLSI devices
d) To improve the ease and efficiency of testing VLSI devices
Question 10: What is the primary goal of wafer probing during VLSI testing?
a) To detect manufacturing defects in VLSI devices
b) To program the VLSI devices with specific configurations
c) To measure the power consumption of VLSI circuits
d) To package the VLSI chips for commercial use
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Defect, Fault, Error and Failure

Defect: Unintended difference between the implemented hardware and its intended design.

Types of Defects:
 Process Defects – missing contact windows, parasitic transistors, oxide breakdown, etc.
 Material Defects – bulk defects (cracks, crystal imperfections), surface impurities, etc.
 Age Defects – dielectric breakdown, electromigration, etc.
 Package Defects – contact degradation, seal leaks, etc.

Fault: Representation of a “defect” at the abstracted function level.

Error: Happens when a defect in hardware causes a line or a gate output to have a wrong value.

Failure: Occurs when a defect causes a misbehavior in the functionality of a system that cannot be reversed
or recovered.
Defect  Error  Failure

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Why Model Faults?

Fault models simplify circuit analysis and enable test automation

 Defects are numerous and often not analyzable
 Models limit the scope of test generation – create tests only for the modeled faults
 Fault models quantify test quality. Number of faults in a circuit can be easily calculated
 Fault Reduction reduces test time
 Fault Simulation estimates Fault Coverage
 Automatic Test Pattern Generation

A good fault model

 has a close correspondence with the actual defects
 Is easy to represent in a computer program
 is as brief as possible for an optimized computer processing time.

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Faults at Various Levels of Abstraction in VLSI
Instruction Correct Faulty
lda AC ← Abus AC ← Abus

add AC ← ABus + AC AC ← (ABus + AC) | ABus

S Correct Faulty

0 W=A W=A
1 W=B W=A or B

S Correct Faulty

0 W=1 W=1
1 W=0 W=Z

Switch T2 open

Short between
G and S

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Functional Faults

 Functional fault is a fault that affects the functionality of a system.

 Gate level: Results in different truth table and alters functionality. Eg: NAND changing to NOR
 System level: System performs a different function than what it was originally designed for
 Eg: ADD instruction executed as subtraction in a processor
 Functional fault of a component at a certain level of abstraction
 Ignores lower level details of the component
 Only considers input – output behavior of the component
 At an abstraction level, the exact cause of the faulty behavior is irrelevant
 Functional fault models are often used in memories

 Disadvantages of Functional fault models

 For a given source defect, analysis required to arrive at the model can be very involved.
 Does not consider interconnection faults outside the faulty component

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Structural Faults

 Assumes that components forming a hardware module are fault free, and only the
interconnection of the components may be faulty.
 The faults in components on either end of the intersection are lumped into the intersection fault.

Faults on line a and w Faults on all lines. Faults on all buses.

Transistors are fault free Gates are fault free. Gates are fault free.

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Single Stuck-at Fault Model
 Most common fault model.
 Assumptions:
 Only one line is faulty
 Faulty line is permanently set to 0 or 1
 Fault can be at an input or output of a gate
 Number of faults is linear to circuit size.
 2 faults per node  2n SSF faults in a circuit of n nodes.

Which test
patterns would you
pick for 100% fault
coverage?

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How many single stuck-at faults in these circuits?

Fanouts give rise to additional fault sites

No of fault sites = #PI + #gates + # Fanout branches.
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Multiple Stuck-at Faults
 Several Stuck-at Faults occur at the same time.
 Important in high density circuits
 Each fault site can be stuck-at 0, stuck-at 1, or be fault free.
 Number of multiple faults = 3n – 1, where n is number of fault sites in the circuit.
 Multiple fault model is more accurate than the single fault assumption.
 Number of possible faults becomes impracticably large even for moderate size circuits.
 Tests for single stuck-at faults cover a very high percentage (>99.6%) of multiple stuck-at faults.
 Hence multiple stuck-at faults not usually considered in practice.
 Exceptions:
 Circuits with redundant single stuck-at faults, where one fault masks another
 Situations where fault locations need to be diagnosed.

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Advantages of Single Stuck-at Fault Model

 Complexity is greatly reduced.

 Many different physical defects may be modeled by the same logical single stuck-at fault.
 Single stuck-at fault is technology independent.
 Can be applied to TTL, ECL, CMOS, etc.
 Single stuck-at fault is design style independent.
 Gate Arrays, Standard Cell, Custom VLSI
 Even when single stuck-at fault do not accurately model some physical defects, the tests
derived for logic faults are still valid for most defects.
 Single stuck-at tests cover a large percentage of multiple stuck-at faults.

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Bridging Fault Models
 A short between two elements is called a bridging fault.
 Between transistor terminals or connections between transistors and gates.
 Number of Bridging Faults = nC2
 Number reduced by identifying the neighboring signals from layout.
 Bridging faults are technology dependent.
 Popular Models for CMOS:
 Wired OR (1-dominant)
 Wired AND (0-dominant)
 Feedback bridging faults produce memory states in combinational logic.

 Bridging faults can be detected by

 IDDQ testing
 Test vectors that provide high stuck-at
fault coverage

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Delay Fault Models

 Some defects change circuit timing but not function.

 eg: Resistive Opens, Resistive Bridging, Cross-talk
 Delay faults cause excessive delay along a path such that the
total propagation delay falls outside the specified limit.
 Delay faults need two pattern test
 V1: Initialize circuit state
 V2: propagate fault effect to output
 Gate delay fault: Increased delay of single logic gate
 Transition fault: slow-to-rise and slow-to-fall
 Path delay fault: Cumulative propagation delay of a
combinational path increases beyond the specified limit.

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Transistor Level Faults
 MOS transistor is considered to be an ideal switch.
 Stuck-Open Faults:
 Faulty Transistor is permanently in open state.
 May cause floating output. Can turn circuit into sequential.
 Requires two vector tests to detect. First vector initializes while
the second vector detects the fault.

 Stuck-Short (Stuck-on) Faults:

 Transistor is permanently in closed state.
 Forms a conducting path between VDD and GND.
 Output logic value depends on relative impedance of the
transistor.
 Detected using IDDQ testing,

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Fault Detection

A test pattern detects a fault if Output of faulty circuit ≠ Output of good circuit

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Fault Activation and Propagation
A fault is detected if two conditions are satisfied:
1. Fault Activation:
 Create different values at the fault site in the presence (vf) and absence of faults (v).
2. Fault Propagation:
 Propagate the error to a primary output by making all the lines along atleast one path
between the fault site and the output have different v and vf values,

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References

1. Essentials of Electronic Testing by Bushnell and Agrawal

2. Digital System Test and Testable Design by Z. Navabi

3. VLSI Test Principles and Architectures by Laung-Terng Wang

4. VLSI Testing lectures by Prof. James Chien-Mo Li, Nanyang Technological Universty

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