Professional Documents
Culture Documents
STM32F103R6
STM32F103R6
STM32F103x6
Low-density performance line, ARM-based 32-bit MCU with 16 or
32 KB Flash, USB, CAN, 6 timers, 2 ADCs, 6 com. interfaces
Datasheet − production data
Features
■ ARM 32-bit Cortex™-M3 CPU Core
– 72 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1) TFBGA64 (5 × 5 mm) LQFP64 (10 × 10 mm)
performance at 0 wait state memory LQFP48 (7 × 7 mm)
access
– Single-cycle multiplication and hardware
division
■ Memories
UFQFPN48 (7 × 7 mm) VFQFPN36 (6 × 6 mm)
– 16 or 32 Kbytes of Flash memory
– 6 or 10 Kbytes of SRAM
■ Debug mode
■ Clock, reset and supply management
– Serial wire debug (SWD) & JTAG interfaces
– 2.0 to 3.6 V application supply and I/Os
■ 6 timers
– POR, PDR, and programmable voltage
detector (PVD) – Two 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter and
– 4-to-16 MHz crystal oscillator
quadrature (incremental) encoder input
– Internal 8 MHz factory-trimmed RC
– 16-bit, motor control PWM timer with dead-
– Internal 40 kHz RC time generation and emergency stop
– PLL for CPU clock – 2 watchdog timers (Independent and
– 32 kHz oscillator for RTC with calibration Window)
■ Low power – SysTick timer 24-bit downcounter
– Sleep, Stop and Standby modes ■ 6 communication interfaces
– VBAT supply for RTC and backup registers – 1 x I2C interface (SMBus/PMBus)
■ 2 x 12-bit, 1 µs A/D converters (up to 16 – 2 × USARTs (ISO 7816 interface, LIN, IrDA
channels) capability, modem control)
– Conversion range: 0 to 3.6 V – 1 × SPI (18 Mbit/s)
– Dual-sample and hold capability – CAN interface (2.0B Active)
– Temperature sensor – USB 2.0 full-speed interface
■ DMA ■ CRC calculation unit, 96-bit unique ID
– 7-channel DMA controller ■ Packages are ECOPACK®
– Peripherals supported: timers, ADC, SPIs,
I2Cs and USARTs Table 1. Device summary
■ Up to 51 fast I/O ports Reference Part number
– 26/37/51 I/Os, all mappable on 16 external STM32F103C4, STM32F103R4,
STM32F103x4
interrupt vectors and almost all 5 V-tolerant STM32F103T4
STM32F103C6, STM32F103R6,
STM32F103x6
STM32F103T6
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 14
2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 14
2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.5 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 14
2.3.6 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.9 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.10 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.11 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.13 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.14 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 17
2.3.15 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.16 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.17 Universal synchronous/asynchronous receiver transmitter (USART) . . 19
2.3.18 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.19 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.20 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.21 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.22 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.23 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.24 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 20
4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 33
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 33
5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 54
5.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.3.17 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.3.18 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.3.19 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 84
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
List of tables
List of figures
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F103x4 and STM32F103x6 low-density performance line microcontrollers. For
more details on the whole STMicroelectronics STM32F103xx family, please refer to
Section 2.2: Full compatibility throughout the family.
The low-density STM32F103xx datasheet should be read in conjunction with the low-,
medium- and high-density STM32F10xxx reference manual.
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.
For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
2 Description
The STM32F103x4 and STM32F103x6 performance line family incorporates the high-
performance ARM Cortex™-M3 32-bit RISC core operating at a 72 MHz frequency, high-
speed embedded memories (Flash memory up to 32 Kbytes and SRAM up to 6 Kbytes),
and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All
devices offer two 12-bit ADCs, three general purpose 16-bit timers plus one PWM timer, as
well as standard and advanced communication interfaces: up to two I2Cs and SPIs, three
USARTs, an USB and a CAN.
The STM32F103xx low-density performance line family operates from a 2.0 to 3.6 V power
supply. It is available in both the –40 to +85 °C temperature range and the –40 to +105 °C
extended temperature range. A comprehensive set of power-saving mode allows the design
of low-power applications.
The STM32F103xx low-density performance line family includes devices in four different
package types: from 36 pins to 64 pins. Depending on the device chosen, different sets of
peripherals are included, the description below gives an overview of the complete range of
peripherals proposed in this family.
These features make the STM32F103xx low-density performance line microcontroller family
suitable for a wide range of applications such as motor drives, application control, medical
and handheld equipment, PC and gaming peripherals, GPS platforms, industrial
applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms, and
HVACs.
Flash - Kbytes 16 32 16 32 16 32
SRAM - Kbytes 6 10 6 10 6 10
Timers
General-purpose 2 2 2 2 2 2
Advanced-control 1 1 1
SPI 1 1 1 1 1 1
Communication
I2C 1 1 1 1 1 1
USART 2 2 2 2 2 2
USB 1 1 1 1 1 1
CAN 1 1 1 1 1 1
GPIOs 26 37 51
1. On the TFBGA64 package only 15 channels are available (one analog input pin has been replaced by
‘Vref+’).
TRACECLK
TRACED[0:3] TPIU Trace
as AS pbu s POWER
Trace/trig Controlle r
NJTRST SW/JTAG VDD = 2 to 3.6V
VOLT. REG.
JTDI VSS
Flash obl
Ibus 3.3V TO 1.8V
Cortex-M3 CPU
interface
JTCK/SWCLK Flash 32 KB
JTMS/SWDIO
64 bit @VDD
JTDO
Fmax : 7 2M Hz Dbus
as AF
BusM atrix
SRAM
NVIC Syst em
10 KB @VDD
PCLK1 OSC_IN
GP DMA PLL & XTAL OSC OSC_OUT
PCLK2
CLOCK 4-16 MHz
7 ch annels HCLK MANAGT
RC 8 MHz
IWDG
RC 40 kHz
@VDDA
Stand by
@VDDA in terface
SUPPLY VBAT
NRST SUPERVISION
@VBAT
VDDA POR / PDR Rst OSC32_IN
VSSA XTAL 32 kHz
AHB2 AHB2 OSC32_OUT
PVD Int
APB2 APB 1 Back up
RTC TAMPER-RTC
reg
EXTI AWU
51AF
WAKEUP Backu p i nterf ace
3 co mpl. channels as AF
TIM1
ETR and BKIN bx CAN
USBDP/CAN_TX
MOSI,MISO, USBDM/CAN_RX
SCK,NSS as AF SPI
USB 2.0 FS
RX,TX, CTS, RTS,
Smart Card as AF USART1 SRAM 512B
@VDDA
WWDG
12bit ADC1 IF
16 AF
VREF+
12bi t ADC2 IF
Temp sensor
ai15175c
8 MHz
HSI RC HSI USBCLK
USB 48 MHz
Prescaler to USB interface
/2 /1, 1.5
HCLK
72 MHz max to AHB bus, core,
Clock memory and DMA
Enable (3 bits)
/8 to Cortex System timer
PLLSRC SW
PLLMUL FCLK Cortex
HSI free running clock
..., x16 SYSCLK AHB APB1
36 MHz max PCLK1
x2, x3, x4 PLLCLK 72 MHz
Prescaler Prescaler
to APB1
PLL max /1, 2..512 /1, 2, 4, 8, 16 peripherals
Peripheral Clock
HSE
Enable (13 bits)
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
64 MHz.
2. For the USB function to be available, both HSE and PLL must be enabled, with USBCLK running at 48
MHz.
3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.
144 5 × USARTs
4 × 16-bit timers, 2 × basic timers
100
3 × SPIs, 2 × I2Ss, 2 × I2Cs
3 × USARTs USB, CAN, 2 × PWM timers
2 × USARTs 3 × 16-bit timers
64 3 × ADCs, 2 × DACs, 1 × SDIO
2 × 16-bit timers 2 × SPIs, 2 × I2Cs, USB, FSMC (100 and 144 pins)
1 × SPI, 1 × I2C, USB, CAN, 1 × PWM timer
48 CAN, 1 × PWM timer 2 × ADCs
2 × ADCs
36
1. For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7),
the reference datasheet for electrical characteristics is that of the STM32F103x8/B medium-density
devices.
2.3 Overview
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher
than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
Refer to Table 11: Embedded reset and power control block characteristics for the values of
VPOR/PDR and VPVD.
2.3.13 DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose and
advanced-control timers TIMx and ADC.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently of the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes. The counter
can be frozen in debug mode.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated for OS, but could also be used as a standard downcounter. It
features:
● A 24-bit downcounter
● Autoreload capability
● Maskable system interrupt generation when the counter reaches 0
● Programmable clock source
BOOT0
VDD_3
VSS_3
PC12
PC11
PC10
PA15
PA14
PD2
PB9
PB8
PB7
PB6
PB5
PB4
PB3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VBAT 1 48 VDD_2
PC13-TAMPER-RTC 2 47 VSS_2
PC14-OSC32_IN 3 46 PA13
PC15-OSC32_OUT 4 45 PA12
PD0 OSC_IN 5 44 PA11
PD1 OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9 LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA 12 37 PC6
VDDA 13 36 PB15
PA0-WKUP 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PA3
VSS_4
PC4
PC5
VDD_4
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
ai14392
PC14- PC13-
A OSC32_IN TAMPER-RTC PB9 PB4 PB3 PA15 PA14 PA13
PC15-
B OSC32_OUT VBAT PB8 BOOT0 PD2 PC11 PC10 PA12
AI15494
BOOT0
VDD_3
VSS_3
PA15
PA14
PB9
PB8
PB7
PB6
PB5
PB4
PB3
48 47 46 45 44 43 42 41 40 39 38 37
VBAT 1 36 VDD_2
PC13-TAMPER-RTC 2 35 VSS_2
PC14-OSC32_IN 3 34 PA13
PC15-OSC32_OUT 4 33 PA12
PD0-OSC_IN 5 32 PA11
PD1-OSC_OUT 6 LQFP48 31 PA10
NRST 7 30 PA9
VSSA 8 29 PA8
VDDA 9 28 PB15
PA0-WKUP 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13 14 15 16 17 18 19 20 21 22 23 24
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
ai14393b
0!
0!
0"
0"
0"
0"
0"
0"
0"
6"!4 6$$?
0#
4!-0%2
24# 633?
0#
/3#?). 0!
0#
/3#?/54 0!
0$
/3#?). 0!
0$
/3#?/54 0!
1&0.
.234 0!
0!
633!
0"
6$$!
0"
0!
7+50
0"
0!
0!
0"
0"
0"
0"
0"
0"
633?
6$$?
0!
0!
0!
0!
0!
-36
BOOT0
VSS_3
PA15
PA14
PB7
PB6
PB5
PB4
PB3
36 35 34 33 32 31 30 29 28
VDD_3 1 27 VDD_2
OSC_IN/PD0 2 26 VSS_2
OSC_OUT/PD1 3 25 PA13
NRST 4 24 PA12
QFN36
VSSA 5 23 PA11
VDDA 6 22 PA10
PA0-WKUP 7 21 PA9
PA1 8 20 PA8
PA2 9 19 VDD_1
10 11 12 13 14 15 16 17 18
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
VSS_1
ai14654
I / O Level(2)
Main
Type(1)
UFQFPN48
VFQFPN36
TFBGA64
LQFP48/
function(3)
LQFP64
Pin name
(after reset) Default Remap
1 1 B2 - VBAT S VBAT
PC13-TAMPER-
2 2 A2 - I/O PC13(6) TAMPER-RTC
RTC(5)
3 3 A1 - PC14-OSC32_IN(5) I/O PC14(6) OSC32_IN
PC15-
4 4 B1 - I/O PC15(6) OSC32_OUT
OSC32_OUT(5)
5 5 C1 2 OSC_IN I OSC_IN PD0(7)
6 6 D1 3 OSC_OUT O OSC_OUT PD1(7)
7 7 E1 4 NRST I/O NRST
- 8 E3 - PC0 I/O PC0 ADC12_IN10
- 9 E2 - PC1 I/O PC1 ADC12_IN11
- 10 F2 - PC2 I/O PC2 ADC12_IN12
- 11 - - PC3 I/O PC3 ADC12_IN13
- - G1 - VREF+ (8) S VREF+
8 12 F1 5 VSSA S VSSA
9 13 H1 6 VDDA S VDDA
WKUP/USART2_CTS/
10 14 G2 7 PA0-WKUP I/O PA0 ADC12_IN0/
TIM2_CH1_ETR(9)
USART2_RTS/
11 15 H2 8 PA1 I/O PA1
ADC12_IN1/ TIM2_CH2(9)
USART2_TX/
12 16 F3 9 PA2 I/O PA2
ADC12_IN2/ TIM2_CH3(9)
USART2_RX/
13 17 G3 10 PA3 I/O PA3
ADC12_IN3/TIM2_CH4(9)
- 18 C2 - VSS_4 S VSS_4
- 19 D2 - VDD_4 S VDD_4
SPI1_NSS(9)/
14 20 H3 11 PA4 I/O PA4
USART2_CK/ADC12_IN4
15 21 F4 12 PA5 I/O PA5 SPI1_SCK(9)/ ADC12_IN5
SPI1_MISO(9)/
16 22 G4 13 PA6 I/O PA6 TIM1_BKIN
ADC12_IN6/TIM3_CH1(9)
SPI1_MOSI(9)/
17 23 H4 14 PA7 I/O PA7 TIM1_CH1N
ADC12_IN7/TIM3_CH2(9)
- 24 H5 PC4 I/O PC4 ADC12_IN14
I / O Level(2)
Main
Type(1)
UFQFPN48
VFQFPN36
TFBGA64
LQFP48/
LQFP64
I / O Level(2)
Main
Type(1)
UFQFPN48
VFQFPN36
TFBGA64
LQFP48/
LQFP64
4 Memory mapping
The memory map is shown in Figure 8.
0xFFFF FFFF
APB memory space
0xFFFF FFFF
reserved
0x4002 3400
CRC
7 0x4002 3000
reserved
0xE010 0000 0x4002 2400
Cortex-M3 Internal
Peripherals Flash Interface
0xE000 0000 0x4002 2000
reserved
0x4002 1400
RCC
0x4002 1000
6 0x4002 0400
reserved
DMA
0x4002 0000
0xC000 0000 reserved
0x4001 3C00
USART1
0x4001 3800
reserved
0x4001 3400
5 SPI
0x4001 3000
TIM1
0x4001 2C00
0xA000 0000 ADC2
0x4001 2800
ADC1
0x4001 2400
reserved
4 0x1FFF FFFF 0x4001 1800
Port D
reserved
0x1FFF F80F 0x4001 1400
Port C
0x8000 0000 Option Bytes 0x4001 1000
Port B
0x1FFF F800 0x4001 0C00
Port A
0x4001 0800
EXTI
3 System memory 0x4001 0400
AFIO
0x4001 0000
0x1FFF F000 reserved
0x6000 0000 0x4000 7400
PWR
0x4000 7000
BKP
0x4000 6C00
2 reserved
0x4000 6800
bxCAN
reserved 0x4000 6400
Peripherals shared 512 byte
0x4000 0000 USB/CAN SRAM
0x4000 6000
USB Registers
0x4000 5C00
reserved
0x4000 5800
1 I2C
0x4000 5400
reserved
0x4000 4800
0x2000 0000 SRAM
0x4000 4400 USART2
0x0801 FFFF
reserved
0x4000 3400
IWDG
0 Flash memory
0x4000 3000
WWDG
0x4000 2C00
RTC
0x0000 0000 0x0800 0000 0x4000 2800
Aliased to Flash or system reserved
memory depending on 0x4000 0800
0x0000 0000 BOOT pins 0x4000 0400 TIM3
ai15177c
5 Electrical characteristics
STM32F103xx pin
STM32F103xx pin
C = 50 pF
VIN
ai14141
ai14142
VBAT
Backup circuitry
Po wer swi tch (OSC32K,RTC,
1.8-3.6V
Wakeup logic
Backup registers)
Level shifter
OUT
IO
GP I/Os Logic
IN Kernel logic
(CPU,
Digital
VDD
VDD & Memories)
1/2/3/4/5 Regulator
5 × 100 nF VSS
+ 1 × 4.7 µF 1/2/3/4/5
VDD
VDDA
VREF VREF+
Analog:
10 nF 10 nF ADC
RCs, PLL,
+ 1 µF + 1 µF VREF- ...
VSSA
ai15496
IDD_VBAT
VBAT
IDD
VDD
VDDA
ai14126
VDD+
Standard IO –0.3
0.3
Table 13. Maximum current consumption in Run mode, code with data processing
running from Flash
Max(1)
Symbol Parameter Conditions fHCLK Unit
TA = 85 °C TA = 105 °C
72 MHz 45 46
48 MHz 32 33
Table 14. Maximum current consumption in Run mode, code with data processing
running from RAM
Max(1)
Symbol Parameter Conditions fHCLK Unit
TA = 85 °C TA = 105 °C
72 MHz 41 42
48 MHz 27 28
Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals enabled
45
40
35
30
Consumption (mA)
72 MHz
25
36 MHz
16 MHz
20
8 MHz
15
10
0
– 45°C 25 °C 70 °C 85 °C 105 °C
Temperature (°C)
Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals disabled
30
25
Consumption (mA)
20
72 MHz
36 MHz
15
16 MHz
8 MHz
10
0
– 45°C 25 °C 70 °C 85 °C 105 °C
Temperature (°C)
Table 15. Maximum current consumption in Sleep mode, code running from Flash
or RAM
Max(1)
Symbol Parameter Conditions fHCLK Unit
TA = 85 °C TA = 105 °C
72 MHz 26 27
48 MHz 17 18
Table 16. Typical and maximum current consumptions in Stop and Standby modes
Typ(1) Max
Symbol Parameter Conditions
VDD/VBAT VDD/VBAT VDD/VBAT TA = TA = Unit
= 2.0 V = 2.4 V = 3.3 V 85 °C 105 °C
Regulator in Run mode, low-speed
and high-speed internal RC
- 21.3 21.7 160 200
oscillators and high-speed oscillator
Supply current OFF (no independent watchdog)
in Stop mode Regulator in Low Power mode, low-
speed and high-speed internal RC
- 11.3 11.7 145 185
oscillators and high-speed oscillator
OFF (no independent watchdog)
IDD
Low-speed internal RC oscillator and
- 2.75 3.4 - - µA
independent watchdog ON
Supply current Low-speed internal RC oscillator
- 2.55 3.2 - -
in Standby ON, independent watchdog OFF
mode
Low-speed internal RC oscillator and
independent watchdog OFF, low- - 1.55 1.9 3.2 4.5
speed oscillator and RTC OFF
Backup
IDD_VBAT domain supply Low-speed oscillator and RTC ON 0.9 1.1 1.4 1.9(2) 2.2
current
1. Typical values are measured at TA = 25 °C.
2. Based on characterization, not tested in production.
Figure 15. Typical current consumption on VBAT with RTC on versus temperature at different
VBAT values
2.5
Consumption ( µA )
1.5 2V
2.4 V
1
3V
0.5 3.6 V
0
–40 °C 25 °C 70 °C 85 °C 105 °C
Temperature (°C)
ai17351
Figure 16. Typical current consumption in Stop mode with regulator in Run mode versus
temperature at VDD = 3.3 V and 3.6 V
120
100
80
Consumption (µA)
3.3 V
60
3.6 V
40
20
0
–45 °C 25 °C 85 °C 105 °C
Temperature (°C)
Figure 17. Typical current consumption in Stop mode with regulator in Low-power mode versus
temperature at VDD = 3.3 V and 3.6 V
90
80
70
60
Consumption (µA)
50
3.3 V
40 3.6 V
30
20
10
0
–45 °C 25 °C 85 °C 105 °C
Temperature (°C)
4.5
3.5
3
Consumption (µA)
2.5 3.3 V
2 3.6 V
1.5
0.5
0
–45 °C 25 °C 85 °C 105 °C
Temperature (°C)
Table 17. Typical current consumption in Run mode, code with data processing
running from Flash
Typ(1)
Symbol Parameter Conditions fHCLK All peripherals All peripherals Unit
enabled(2) disabled
72 MHz 31.3 24.5
48 MHz 21.9 17.4
36 MHz 17.2 13.8
24 MHz 11.2 8.9
16 MHz 8.1 6.6
(3)
External clock 8 MHz 5 4.2 mA
4 MHz 3 2.6
2 MHz 2 1.8
1 MHz 1.5 1.4
500 kHz 1.2 1.2
Supply 125 kHz 1.05 1
IDD current in
Run mode 64 MHz 27.6 21.6
48 MHz 21.2 16.7
36 MHz 16.5 13.1
Table 18. Typical current consumption in Sleep mode, code running from Flash or
RAM
Typ(1)
Symbol Parameter Conditions fHCLK Unit
All peripherals All peripherals
enabled(2) disabled
TIM2 1.2
TIM3 1.2
USART2 0.35
APB1 mA
I2C 0.39
USB 0.65
CAN 0.72
GPIO A 0.47
GPIO B 0.47
GPIO C 0.47
GPIO D 0.47
APB2 ADC1(2) 1.81 mA
ADC2 1.78
TIM1 1.6
SPI 0.43
USART1 0.85
1. fHCLK = 72 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral.
2. Specific conditions for ADC: fHCLK = 56 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/4, ADON bit
in the ADC_CR2 register is set to 1.
VHSEH
90%
10%
VHSEL
tr(HSE) tW(HSE) t
tf(HSE) tW(HSE)
THSE
ai14143
VLSEH
90%
10%
VLSEL
tr(LSE) tW(LSE) t
tf(LSE) tW(LSE)
TLSE
ai14144b
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 21). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2. Refer to the application note AN2867 “Oscillator design guide for ST
microcontrollers” available from the ST website www.st.com.
ai14145
RF Feedback resistor 5 MΩ
Recommended load capacitance
C versus equivalent serial RS = 30 KΩ 15 pF
resistance of the crystal (RS)
VDD = 3.3 V
I2 LSE driving current 1.4 µA
VIN = VSS
gm Oscillator transconductance 5 µA/V
TA = 50 °C 1.5
TA = 25 °C 2.5
TA = 10 °C 4
VDD is TA = 0 °C 6
tSU(LSE)(3) Startup time s
stabilized TA = -10 °C 10
TA = -20 °C 17
TA = -30 °C 32
TA = -40 °C 60
1. Based on characterization, not tested in production.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Note: For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to
15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2, are
usually the same size. The crystal manufacturer typically specifies a load capacitance which
is the series combination of CL1 and CL2.
Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where
Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
between 2 pF and 7 pF.
Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended
to use a resonator with a load capacitance CL ≤ 7 pF. Never use a resonator with a load
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF,
then CL1 = CL2 = 8 pF.
Resonator with
integrated capacitors
CL1
OSC32_IN fLSE
Bias
32.768 kH z RF controlled
resonator gain
OSC32_OU T STM32F103xx
CL2
ai14146
1. The wakeup times are measured from the wakeup event to the point in which the user application code
reads the first instruction.
Read mode
fHCLK = 72 MHz with 2 wait 20 mA
states, VDD = 3.3 V
IDD Supply current Write / Erase modes
5 mA
fHCLK = 72 MHz, VDD = 3.3 V
Power-down mode / Halt,
50 µA
VDD = 3.0 to 3.6 V
Vprog Programming voltage 2 3.6 V
1. Guaranteed by design, not tested in production.
0.1 to 30 MHz 12 12
30 to 130 MHz 22 19 dBµV
SEMI Peak level VDD = 3.3 V, TA = 25 °C
130 MHz to 1GHz 23 29
SAE EMI Level 4 4 -
TA = +25 °C
Electrostatic discharge
VESD(HBM) conforming to 2 2000
voltage (human body model)
JESD22-A114
V
Electrostatic discharge TA = +25 °C
VESD(CDM) voltage (charge device conforming to II 500
model) JESD22-C101
1. Based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
● A supply overvoltage is applied to each power supply pin
● A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Standard IO
input low level - - 0.28*(VDD-2 V)+0.8 V(1)
voltage
VIL Low level input voltage IO FT(3) input
- - 0.32*(VDD-2V)+0.75 V(1)
low level voltage
All I/Os except
- - 0.35VDD(2)
BOOT0
Standard IO V
(1)
input high level 0.41*(VDD-2 V)+1.3 V - -
voltage
IO FT(3) input
VIH High level input voltage
high level 0.42*(VDD-2 V)+1 V(1) - -
voltage
All I/Os except
0.65VDD(2) - -
BOOT0
Standard IO Schmitt
trigger voltage 200 - -
Vhys hysteresis(4) mV
IO FT Schmitt trigger
5% VDD(5) - -
voltage hysteresis(4)
VSS ≤ VIN ≤ VDD
- - ±1
Input leakage current Standard I/Os
Ilkg (6) µA
VIN = 5 V
- - 3
I/O FT
Weak pull-up
RPU VIN = VSS 30 40 50
equivalent resistor(7)
kΩ
Weak pull-down
RPD VIN = VDD 30 40 50
equivalent resistor(7)
CIO I/O pin capacitance - 5 - pF
1. Data based on design simulation.
2. Tested in production.
3. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be
disabled.
4. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
5. With a minimum of 100 mV.
6. Leakage could be higher than max. if negative current is injected on adjacent pins.
7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 23 and Figure 24 for standard I/Os, and
in Figure 25 and Figure 26 for 5 V tolerant I/Os.
6)(6), 6 !REA NOT
DETERMINED
6 $$
M E N T 6 )(
UIRE
ARD REQ 6
STAND 6 )( $$ NS
#-/3 N DE SI GN SIMULATIO
O
"ASED
TION
N PRODUC 6
4ESTED I 6), $$ ULATIONS
7)(MIN DESIGN SIM
"ASED ON
6
MENT 6 ), $$
7),MAX #-/3 STAN DARD REQUIRE
DUCT ION
4ESTED IN PRO
6$$ 6
AIC
6)(6), 6 !REA NOT
DETERMINED
6 ),6 $$ NS
IGN SIMULATIO
ES
"ASED ON D
7),MAX
44, REQUIREMENTS 6),6
6$$ 6
AIB
6)(6), 6 !REA NOT
DETERMINED
6 $$
NTS 6 )(
DARD REQUIREME
#-/3 STAN
6 )(6 $$ SIMULATIONS
D ON D ES IGN
TION "ASE
P RODUC
4ESTED I
N 6 ),6 $$ ATIONS
ESIGN SIMUL
"ASED ON D
6 $$
ENT 6 ),
DARD REQUIRM
#-/3 STAN
DUCTION
4ESTED IN PRO
6$$ 6
6$$
AIC
6)(6), 6
!REA NOT
DETERMINED
44, REQUIREMENT 6 )(6
6 $$
6 )(
SI GN SIMULAT
IONS
O N DE
"ASED
6 ),
6 $$ IMULATIONS
DESIGN S
7)(MIN "ASED ON
7),MAX
44, REQUIREMENTS 6 ),6
6$$ 6
AIB
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 27 and
Table 37, respectively.
Unless otherwise specified, the parameters given in Table 37 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 9.
90% 10%
50% 50%
10% 90%
External
Output tr(I O)out tr(I O)out
on 50pF
T
Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%)
when loaded by 50 pF
ai14131
VDD
External
reset circuit(1)
RPU Internal reset
NRST(2)
Filter
0.1 µF
STM32F10x
ai14132d
1 tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 72 MHz 13.9 ns
0 fTIMxCLK/2 MHz
Timer external clock
fEXT
frequency on CH1 to CH4 f
TIMxCLK = 72 MHz 0 36 MHz
ResTIM Timer resolution 16 bit
16-bit counter clock period 1 65536 tTIMxCLK
tCOUNTER when internal clock is
selected fTIMxCLK = 72 MHz 0.0139 910 µs
Rp Rp 34-&X
Rs
3$!
)£# BUS Rs
3#,
3TART REPEATED
3TART
3TART
TSU34!
3$!
TF3$! TR3$! TSU3$!
3TOP TSU34/34!
TH34! TW3#,, TH3$!
3#,
TW3#,( TR3#, TF3#, TSU34/
AIE
400 0x801E
300 0x8028
200 0x803C
100 0x00B4
50 0x0168
20 0x0384
1. RP = External pull-up resistance, fSCL = I2C speed,
2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external
components used to design the application.
NSS input
tc(SCK)
tSU(NSS) th(NSS)
CPHA= 0
SCK Input
CPOL=0
tw(SCKH)
CPHA= 0 tw(SCKL)
CPOL=1
Figure 31. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input
tSU(NSS) tc(SCK) th(NSS)
CPHA=1
SCK Input
CPOL=0
tw(SCKH)
CPHA=1 tw(SCKL)
CPOL=1
ai14135
High
NSS input
tc(SCK)
CPHA= 0
SCK Input
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
SCK Input
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INP UT MS BIN BI T6 IN LSB IN
th(MI)
MOSI
M SB OUT B I T1 OUT LSB OUT
OUTUT
tv(MO) th(MO)
ai14136
USB characteristics
The USB interface is USB-IF certified (Full Speed).
Input levels
Output levels
Figure 33. USB timings: definition of data signal rise and fall time
Crossover
points
Differen tial
data lines
VCRS
VS S
tf tr
ai14137
Driver characteristics
tr Rise time(2) CL = 50 pF 4 20 ns
tf (2)
Fall time CL = 50 pF 4 20 ns
trfm Rise/ fall time matching tr/tf 90 110 %
VCRS Output signal crossover voltage 1.3 2.0 V
1. Guaranteed by design, not tested in production.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
The formula above (Equation 1) is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
V V
[1LSBIDEAL = REF+ (or DDA depending on package)]
4096 4096
EG
(1) Example of an actual transfer curve
4095
(2) The ideal transfer curve
4094 (3) End point correlation line
4093
(2)
ET=Total Unadjusted Error: maximum deviation
ET between the actual and the ideal transfer curves.
7 (3) EO=Offset Error: deviation between the first actual
(1) transition and the first ideal one.
6
EG=Gain Error: deviation between the last ideal
5 transition and the last actual one.
EO EL ED=Differential Linearity Error: maximum deviation
4 between actual steps and the ideal one.
3 EL=Integral Linearity Error: maximum deviation
ED between any actual transition and the end point
2 correlation line.
1 LSBIDEAL
1
VDD STM32F103xx
Sample and hold ADC
VT converter
0.6 V
RAIN(1) RADC(1)
AINx 12-bit
converter
IL±1 µA
Cparasitic VT
VAIN 0.6 V
CADC(1)
ai14150c
Figure 36. Power supply and reference decoupling (VREF+ not connected to VDDA)
34-&XX
62%&
SEE NOTE
&