INTRODUCTION TO MICROPROCESSORS

• ADDRESS BUS WIDTH AND DATA BUS WIDTH

• NUMBER OF INSTRUCTIONS – INSTRUCTION SET – ISA –
VOCABULARY OF INSTRUCTIONS
• REGISTERS
ARE COMPONENTS OF ARCHITECUTRE.

 MIPS - MILLION INSTRUCTION PER SEC

 MOPS MILLION OPERATIONS PER SEC
 FLOPS MFLOPS MILLION FLOATING POINT OPERATIONS
PER SEC

➞ Machine languages differ from machine to machine , and are quite similar to one
another, because there are a few basic operations that all machines must
provide
➞ Computer designers have a common goal to find a language that makes it easy to
build the hardware and the compiler while maximizing performance at minimum
cose
➞ The “ simplicity of the equipment” is a valuable consideration for the machine
design ( cisc v/s risc ) . Hence our goal should be to design an instruction set
that follows this logic showing both how it is represented in the hardware and
the relationship between high level languages
➞ TYPE DATA BUS WIDTH MEM SIZE ADDRESS BUS WIDTH CLOCK MHS
8048 8 2K INTERNAL --- ---
8051 8 8K INTERNAL --- ---
8085A 8 64 K --- ---
8086 16 1M 20 5
8088 8 1M 20 5
8096 16 8K INTERNAL --- ---
80186 16 1M 20 6
80188 8 1M -- --
80286 16 16 M 24 8
80386 DX 32 4G 32 16
80386 SL 16 32 M 25 16

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 80386 SX 16 16 M 24 16
80486 DX 32 4G 32 25
80486 SX 32 4G 32 20
PENTIUM 32/64 4G

➞ Unlike programs in high level languages, the operands of arithmetic instructions

cannot be any variables; they must be from a limited number of special locations
called registers.
➞ Registers are the bricks of computer construction, for registers are primitives
used in hardware design that are also visible to the programmer
➞ The reason for limiting registers is ‘smaller is faster’
➞ High level languages have complex data structures which can contain many more
data elements than there are registers in a machine
How to represent them ?
these data structures are stored in memory and processor should be able to
access them, these are called ‘data transfer’ instruction

2 - 10

1 - 110
0 - 001

PROCESSOR MEMORY

➞ To access a word in memory the instruction must supply the memory address.
LOAD ; MEMORY REGISTER

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➞ Words must always start at addresses that are multiple of 4. This requirement
is called alignment restriction
➞ “Bigendian and Littleendian”
➞ Converse of load is STORE ; REGISTER MEMORY
➞ The process of putting less commonly used variable ( or those needed later )
into memory is called spilling registers
➞ Instructions for making decision – conditional branches
Branch if equal , branch if not equal
➞ Unconditional branching jump
➞ Compare instructions
➞ AND, OR, SUB, ADD, SLT( set less than ) - R –type instructions
➞ Breaking the instruction execution
1. Instruction fetch step IR = MEM[PC]; PC = PC+4;
2. Instruction decode & register fetch step
A = Reg[IR[25-21]]
B = Reg[IR[20-16]]
Aluout = PC + (sign extended(IR[15-0]<<2))
After this clock cycle, determining the action to take can depend on the
instruction contents.
3. Execution, memory address computation or branch completeion.
This is the first cycle during which the datapath operation is determined by the
instruction class
The ALU is operating on the operands prepared in the previous step, performing
one of these three functions.
a. Memory reference b. A L instruction ( R-type ) c. Branch and jump
4. Memory access or R-type instruction completion step
During this step, a load, or store instruction accesses memory and an AL
instruction writes its result, when a value is retrieved from memory it is stored
into the MDR, where it must be used on the next clock cycle
a. Mem – reference
MDR = Memory[ALUout] ; load or
Memory[ALUout] = b ; store
b. Arithmetic – logic instruction ( R – Type)
Reg[IR[15-11]] = ALUout ;
Place the contents of ALUout, which corresponds to the output of the

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 ALU operation in the previous cycle, into the result register
5. Memory read completion step
During this step, load completed by writing back the value from memory
LOAD ; Reg[IR[20-16]] = MDR.

GENERAL STRUCTURE OF THE MICROPROCESSOR

SEGMENT
GENERAL
REGISTERS
REGISTERS
INSTRUCTION POINTER

ADDRESS
MULTIPLEXED BUS GENERATION AND
BUS CONTROL

OPERANDS

INSTRUCTION
QUEUE

ALU

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kumar 4
 FLAGS

EU
A SIMPLE ARCHITECTURE for Illustration :

MSB LSB
7 REGISTER A 0

CPU MSB LSB

7 REGISTER B 0

MSB INSTRUCTION POINTER REGISTER LSB

15 0

ADDRESS FFFF CONTENTS OF ADDRESS FFFF

ADDRESS FFFE CONTENTS OF ADDRESS FFFE
--- ---

VARIABLE OR FIXED DATE

LAST CODE ADDRESS LAST CODE BYTE

MEMORY
--- ---

64 K MEMORY SPACE

ADDRESS 0001 SECOND CODE BYTE

ADDRESS 0000 FIRST CODE BYTE

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 Register A ; Performs all operations in the CPU
Register B ; Stores numbers temporarily
Register IP ; Holds the address of the next instruction to be executed in code
Memory

• This is an 8-bit computer because Reg A & B can hold 1 byte

• Memory address range is 64 k , IP - 16 bits , 0000h to FFFFh

• Memory can contain any mix of code and data

INSTRUCTIONS :

There are nine instructions in the simple architecture considered above :

Instruction Data Machine code CPU

Mnemonic location in hex Action

MOV A, num 3Dh,num Move the byte number num to A.

Num is any 1 byte number in the range
00h to FFh

MOV A, [addr] 3Eh, addr Move the byte contents of address

Addr to A, addr is any 2 byte address
Number in memory
[ ] = address contents

MOV [addr], A 3Fh, addr Move the byte number in A to the

Contents of address addr.

MOV B, A 4Ch Move contents of Reg A to Reg B

MOV A, B 4Dh B to A

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AND A, B F3h Logical AND, Results in Reg A
OR A, B 9Ah Logical OR, Results in Reg A

NOT A 67h Complements the contents of A

GO addr 77h,addr Set IP equal to 2 byte number addr

Example:

Mov A, 01h ; put the number 1 in A

Mov [1000h], A ; store in memory location 1000h
Mov A, 02h ; put number 2 in A
Mov [1001h], A ; store in memory location 1001h
Mov A, 03h ; put number 3 in A
Mov [1002h], A ; store in memory location 1002h
Go 0000h ; set IP back to start program

ASSEMBLY PROCESS:

Code Memory Contents of code Address

Address Memory address Instruction

0000h 3Dh Mov A, 01h

0001h 01h

0002h 3Fh Mov [1000h], A

0003h 00h
0004h 10h

0005h 3Dh Mov A, 02h

0006h 02h

0007h 3Fh Mov [1001h], A

0008h 01h
0009h 10h

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 000Ah 3Dh Mov A, 03h
000Bh 03h

000Ch 3Fh Mov [1002h], A

000Dh 02h
000Eh 10h

000Fh 77h Go 0000h

0010h 00h
0011h 00h

8086 CPU Registers:

15 0 15 0
POINTS TO CODE STORES CERTAIN
IP FLAGS RESULTS
INSTRUCTION POINTER AF CF DF IF OF PF SF TF ZF

SPECIAL USES
VARIOUS MATHS., 15 AX 0
I/O DATA 7 AH 0 7 AL 0

POINTER TO 15 BX 0
MEMORY 7 BH 0 7 BL 0
WORKING
(GENERAL
15 CX 0 PURPOSE)
COUNTING
7 CH 0 7 CL 0 REGISTERS
I/O ADDRESSES

VARIOUS 15 DX 0
MATHEMATICS 7 DH 0 7 DL 0

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 15 DI 0 15 SP 0
DESTINATION INDEX REG STACK POINTER REG
DATA
POINTING
REGISTERS
15 SI 0 15 BP 0
SOURCE INDEX REG BASE POINTER REG

GENERAL MEMORY POINTER STACK SEGMENT POINTER

SEGMENT 15 0
REGISTERS CS
CODE SEGMENT REGISTER

15 0
DS
DATA SEGMENT REGISTER

15 0
SS
STACK SEGMENT REGISTER

15 0
ES
EXTRA SEGMENT REGISTER

FLAGS : AF[S] AUXILIARY CARRY FLAG CF[S] CARRY FLAG

DF[C] DIRECTION FLAG IF[C] INTERRUPT FLAG
OF[S] OVERFLOW FLAG PF[S] PARITY FLAG
SF[S] SIGN FLAG TF[S] TRAP FLAG

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 ZF[S] ZERO FLAG [S] = STATUS , [C] = CONTROL
MEANING OF THE FLAG IF SET TO 1 ;

AF ; a carry out of the result or a borrow into the low nibble of a result
CF ; a carry out of the MSB of a result or a borrow into the result
DF ; forces certain opcodes to process data in memory from high to low
Addresses
IF ; allows the CPU to be interrupted by an externally generated interrupt
OF ; applies only to signed numbers used in a program indicated that the
Result is too large for the signed number range chosen
PF ; the operation generated a result with even number of 1 s in the LSByte
SF ; the result of an operation contains a 1 bit in the MSB position
TF ; performs a software interrupt at the end of the next instruction
ZF ; the last CPU operation resulted in a quantity that contain all binary 0 s

SOFTWARE MODEL OF 8086 MICROPORCESSOR ;

00000h
MEMORY
IP

CS CODE SEGMENT
DS (64 K BYTES)

SS
ES
DATA SEGMENT
( 64 K BYTES)
AH AL AX
BH BL BX
STACK SEGMENT
CH CL CX
(64 K BYTES)
DH DL DX
EXTRA SEGMENT
SP (64 K BYTES)
BP FFFFFh

SI
DI
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 STATUS REGISTER
ADDRESS SPACE OF 1 M BYTES OF EXTERNAL MEMORY;

FFFFF
FFFFE
FFFFD
FFFFC
FFFFB
FFFFA
FFFF0
- --
- --
- --
- --

00003
00002
00001
00000

 Even- or odd- addressed bytes of data can be independently accessed

 Any two consecutive bytes can be accessed as a word of data
 Lower addressed byte is the LSByte
 Higher addressed byte is the MSByte

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 Addressed Memory ( binary ) Memory ( hex )

00725 0101 0101 5 5

00724 0000 0010 0 2

5502 hex = 0101010100000010 binary

 Least significant bit of the address, determines the type of word boundary
0  even address boundary
A word at an even address boundary corresponds to 2 consecutive bytes
With the lease significant byte located at even address .

In the example above, LSByte 00724 is an even address boundary.

Example :

What is the data word shown in fig ?

Express the result in hexadecimal form. Is it stored at an even – or odd
address boundary?
Address memory ( binary )

0072Ch 11111101

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 0072Bh 10101010
Solution :

MSByte of the work stores at address 0072Ch and equals 11111101 binary = FDh
LSByte is at 0072Bh and is 10101010 binary = AAh

Together the word is FDAA h = 1111110110101010 binary

Binary equivalent of the LSByte address 0072Bh is 00000000011100101011 binary

Since LSB of the address is 1 this corresponds to odd – addressing boundary in
memory

 Pointer  a double word data

 a two word address element

used to access data or code outside the current segment of the memory.

The word of the pointer that is stored at the higher address is called the
Segment-base address and the word at the lower address is called the offset
Value

Address Memory ( Binary ) Mem ( hex )

00007h 0011 1011 3 B

00006h 0100 1100 4 C

00005h 0000 0000 0 0

00004h 0110 0101 6 5

Segment Address 3B4C hex

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Offset Address 0065 hex
Example :

How should the pointer with segment-base address equal to A000h and offset
address 55FFh be stored at an even-address boundary starting at 00008h ?

Solution :

Address Memory ( Hex )

0000Bh A 0
0000Ah 0 0
00009h 5 5
00008h F F

STORAGE CAN BE IN UNPACKED BCD BYTE OR PACKED BCD BYTE

D3 D0
UNPACKED BCD BYTE
MSB LSB

D7 D4 D3 D0
PACKED BCD BYTE

BCD DIGIT 1 BCD DIGIT 0

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