Circuit Theory Apps - 2022 - Shaw

Received: 23 June 2022 Revised: 6 September 2022 Accepted: 21 September 2022
DOI: 10.1002/cta.3464
ORIGINAL PAPER
A new family of high gain boost DC-DC converters with

reduced switch voltage stress for renewable energy sources
Priyabrata Shaw 1 | Marif Daula Siddique 2 | Saad Mekhilef 3 | Atif Iqbal 2
1
Electronics and Control Department,
Research and Development (R&D), Shakti Abstract
Pumps (India) Ltd., Pithampur, Madhya In this paper, a new family of non-isolated boost dc-dc converters with high
Pradesh, India
voltage gains is proposed. The proposed boost topologies exhibit very high volt-
2
Department of Electrical Engineering,
age gains at moderate duty cycles and lower switch voltage/current stresses
Qatar University, Doha, Qatar
3
School of Software and Electrical
with reduced component counts. Here, a total of four new non-isolated boost
Engineering, Swinburne University of topologies are proposed using four-terminal PWM high-gain switch cells with
Technology, Melbourne, Victoria, an inductor-switch network. Among these four topologies, two converters have
Australia
identical voltage gain with opposite load voltage polarities and likewise other
Correspondence two exhibit similar nature (i.e., equal but opposite load voltage) but have
Saad Mekhilef, School of Software and
higher gain than the former topologies. The detailed operating principle,
Electrical Engineering, Swinburne
University of Technology, Melbourne, steady-state analysis, and design methodology are presented for the proposed
Victoria, Australia. positive output very high-gain converter, which can be easily extended to the
Email: smekhilef@swin.edu.au
rest of the topologies. An exhaustive comparison study has been presented for
the proposed topologies with the existing step-up converters to highlight their
advantages. Finally, the mathematical analysis, analytical studies, and high
boosting feature of the proposed positive output high-gain boost converter are
verified using a 250 W, 50 kHz prototype. The experimental results are pres-
ented for different duty cycles with fixed input voltage to verify the efficacy of
the proposed structures in terms of higher boosting capability.
KEYWORDS
boost dc-dc converter, energy sources, four-terminal PWM high-gain switch cell, high
voltage gain, low switch voltage stress, renewable energy integration
1 | INTRODUCTION
Renewable energy is becoming more widely used around the world on a daily basis, with the goal of reducing the envi-
ronmental destruction caused by fossil-fuel-based power generation technologies. Solar PV with battery, fuel cell, and
other nonconventional energy sources are the most commonly used renewable sources. In order to meet the local
power needs, residential customers rely on these renewable sources with a power output of a few watts to 10s of
kilowatts. However, the main issue with these sources is the low output voltage and they cannot be directly connected
to the utility grid.1,2 For integrating sources of low voltage input to high voltage applications, boost dc-dc converters are
used. The conventional boost converter (CBC) is the most widely used topology due to its simple structure and non-
pulsating source current nature.3 However, the limitations on voltage gain and switch stress are the primary drawbacks
of the CBC, notwithstanding its recent application. Figure 1 shows a typical use of a high step-up dc-dc converter in a
renewable energy system. In the last decade, a number of isolated and non-isolated high step-up dc-dc converters have
Int J Circ Theor Appl. 2023;51:1265–1285. wileyonlinelibrary.com/journal/cta © 2022 John Wiley & Sons Ltd. 1265
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1266 SHAW ET AL.
FIGURE 1 Renewable energy integration with utility grid using high-gain dc-dc converter
been reported in the literature. The saturation of the transformer core, the increased number of components, and the
reduced efficiency of isolated type converters are key drawbacks in low and medium power applications. Thus, the
non-isolated type high voltage gain dc-dc converters play an elementary role as interface devices between the low volt-
age energy sources and the utility grid.
To address these issues in CBC, multi-stage, multi-switch, and multi-element-based topologies are becoming popu-
lar.4,5 Though the multi-element as well as the multi-stage based topologies form the higher-order systems, but with
them, it is easy to meet the performance requirements as enforced by the loads.4–33 The key desirable performance goals
of these converters are (i) single-switch or two-switch solutions which are easy to drive, (ii) very high boost factor even
at low and moderate duty ratios, (iii) non-pulsating source current, (iv) reduced voltage and current stresses across
semiconductor switches and storage elements, and (v) better efficiency even at higher loads.
Numerous high gain step-up converter topologies have been recently reported in the literature to achieve some of
the above performance requirements. In Axelrod et al.,6 a switched-inductor (SL) based boost topology is proposed to
achieve a high voltage conversion ratio. However, the low voltage gain and high voltage stress on switch/diodes are
some of the limitations. Another high gain step-up converter has been reported in Rong et al.7 having voltage gain
identical to SL-based boost converter with four energy storage elements. But a higher number of diodes and high
switch voltage stress are its major limitations. A fourth-order step-up converter with equal voltage gain as SL-based
boost is also suggested in Wu et al.8 However, the negative load voltage polarity is one of its major limitations. Hav-
ing identical voltage gain as SL-based boost converter and the topology reported in previous works,7,8 various step-up
boost dc-dc converters are also reported in recent literature.9–11,21,22 However, in these topologies, higher numbers of
passive elements are utilized to achieve a lower boost factor. A KY boost converter is suggested in Hwu and Yau12 to
achieve high voltage gain at a lower and moderate duty ratio by utilizing two switches, two inductors, and three
capacitors. This topology has the advantage of continuous input and output current, but low voltage gain and high
voltage stress across capacitors are its disadvantages. To achieve the high voltage gain, different versions of SL-cell
are utilized in many recent topologies.6,13,14 Similarly, switched-capacitor (SC) and voltage multiplier networks are
used in various dc-dc converter topologies to attain a very high voltage conversion ratio.6,8,15,16 Some hybrid dc-dc
converter topologies having very high voltage gain also reported in the literature that uses both SL-cells and
SC-cells.17,18
The SC and SL cells are also adopted for the conventional buck, boost, buck-boost, Cuk, Sepic, and Zeta converters
to provide new dc-dc converters with a high voltage conversion ratio.6,15,23,24 In these converter topologies, the induc-
tances of the inductors are chosen to be equal to each other. However, the major drawbacks of these structures are the
voltage across the switch is equal to the output voltage. In Sadaf et al.,25 an SL-cell based two-switch boost converter is
proposed that exhibits reduced switch voltage stress as the output voltage is divided across both switches. However, the
voltage gain of this topology is not very high (i.e., (1 + D)/(1 D)) as it can achieve a gain of ‘3’ at ‘0.5’ duty cycle.
Thus, attaining a very high voltage gain with this boost topology is not possible without operating the converter in
extreme duty cycles. Similarly, an improved gain modified SEPIC topology is reported in26 using a dual-switch based
active SL-cell,27 which exhibits higher voltage gain than the conventional SEPIC and modified SEPIC,10 but it is unable
to achieve very high voltage gain at low and moderate duty cycles. In literature,28,29 many such different converters are
reported using SL-cells to achieve very high voltage gain. However, the topology reported in Shaw and Sahoo28 has the
drawbacks like a higher number of switches, and high switch and diode voltage stresses. Similarly, the topology
SHAW ET AL. 1267
reported in Bao et al.29 has also the disadvantages of high voltage stress and a large number of semiconductor devices.
Additionally, these topologies have the major drawback that the maximum duty ratio is limited by ‘0.5’ instead of ‘1’ as
their denominator of voltage gain contains (1–2D) term. In Alrahrani et al.,16 in order to increase the voltage conversion
ratio, an SC cell has been utilized. This converter has the merits of the structures presented in previous studie6,15 with a
difference that due to the placing of a switch at the input of the topology, the input current becomes discontinuous, and
assessing the maximum power from the input source is not possible unless a filter is utilized. In literature,13 a high gain
step-up converter has been presented. In the suggested topology, the higher voltage gain at the lower duty cycle and the
reduced voltage/current stresses on the semiconductor devices are some of the key advantages. Recently, an SC-based
step-up converter is reported in Cui et al.21 to achieve high voltage gain with reduced output capacitor voltage
stress. Conversely, to achieve lower capacitor voltage stress along with high voltage gain, higher numbers of
components are used in this topology. Nevertheless, most of the boost dc-dc converters reported so far suffer from the
following limitations: (b) low voltage gain, (b) higher number of L-C components, (c) higher number of diodes leading
to lower efficiency, (d) higher device voltage and current stresses, and (e) discontinuous input current. The proposed
four-terminal PWM high-gain switch (FTPHGS) cell based high-gain boost dc-dc converters have the following
advantages.
a. Very high voltage gain at low and moderate duty ratio.

b. Reduced passive and switching components count.
c. Low voltage and current stresses on switches.
d. Reduced capacitor voltage stress.
e. Non-pulsating source current.
2 | D E V E L O P M E N T O F H I G H S T E P - UP DC - D C C O N V E R T E R S U S I N G
MODIFIED FOUR-TERMINAL P WM HIGH-GAIN S WITCH CELL
Figure 2 shows the evolution of four improved high-gain step-up dc-dc converters using different four-terminal PWM
high-gain switch (FTPHGS) cells23 and an inductor-switch network. The first two topologies are developed from the
positive output FTPHGS cell based boost converter as shown in Figure 2A. The topology shown in Figure 2A utilizes
FTPHGS cell to achieve a gain of (1 + D)/(1 D) and exhibits positive output voltage.23 These FTPHGS cell based
topologies have a significant advantage of low switch-voltage stress, which makes them suitable for high voltage gain
applications. In order to enhance the voltage gain of the topology shown in Figure 2A, an inductor-switch network
(L2 and S2) has been employed in the return path near source Vin as shown in Figure 2B. With this modification, the
voltage gain of the proposed topology-1 (PT-1) is improved to (1 + 3D)/(1 D). Furthermore, the voltage gain of this
topology is extended by replacing the load side inductor L3 by a diode D3 as presented in Figure 2C. The proposed
topology-2 (TP-2) able to achieve very high voltage gain along with low voltage stress across both the switches (S1
and S2), which is one of the attractive feature of the topology shown in Figure 2A. Similarly, another high gain boost
dc-dc converter has been developed in23 using a different FTPHGS cell as shown in Figure 2D. This topology has the
same voltage gain that of the converter shown in Figure 2A, but has opposite load voltage polarity. Similar to previ-
ous development, by using an inductor in the return path with switch S2, the gain of this topology (PT-3) is extended
to (1 + 3D)/(1 D) (see Figure 2D). Moreover, by replacing the inductor L3 by a diode D3, the voltage gain of PT-3
has been further extended to (3 + D)/(1 D). The circuit of the proposed topology-4 (PT-4) is shown in Figure 2F.
As compared to the topology suggested in Figure 2C, the load voltage of polarity is reversed in PT-4, and thus, the
diode D3 is connected in opposite direction as shown in Figure 2F. This ultra-high gain feature of the PT-2 and PT-4
is achieved here by adding the inductor-switch network in the return path and replacing load side inductor by a
diode, in addition to the low switch voltage stress benefit of the topologies reported in Ismail et al.23 (shown in
Figure 2A,D).
Here, the PT-1 and PT-2 exhibit positive output voltage polarity, conversely the PT-3 and PT-4 show negative
load voltage polarity. The voltage gains of the PT-1 and PT-3 are same but lower than that of the PT-2 and PT-4
with gain (3 + D)/(1 D). The operating principle and steady-state analysis of all four proposed topologies are
almost the same and hence, this paper presents the detailed mathematical analysis and experimental validation for
PT-2 (see Figure 2C) as it has the superior benefit of the positive output voltage and higher voltage gain as com-
pared to other topologies.
1268 SHAW ET AL.
F I G U R E 2 Developments of the proposed high-gain boost converter topologies. (A) Positive output high-gain boost topology.23
(B) Proposed topology-1 (PT-1). (C) Proposed topology-2 (PT-2). (D) Negative output high-gain boost topology.23 (E) Proposed topology-3
(PT-3). (F) Proposed topology-4 (PT-4)
3 | PROPOS ED HIGH-G AIN STEP-U P C ONVERTERS: OPERATION

PRINCIPLE A ND STEADY-STATE ANALYSIS
Figure 2 shows the structure of all the proposed step-up dc-dc converters employing the FTPHGS cells and the LS net-
work. Here, the working principle and thorough analysis is presented for only PT-2, which can be extended easily to
other three topologies. The power circuit of the PT-2 with positive output voltage is essentially derived by adding an
inductor-switch network to the FTPHGS based boost converter23 and swapping the load side inductor by a diode. The
PT-2 shown in Figure 2C is a two-switch topology and consists of five energy storage elements (two inductors: L1 and
L2, and three capacitors: C1, C2, and C3) and three diodes (D1, D2, and D3). The converter analysis can be performed
SHAW ET AL. 1269
under continuous conduction mode (CCM). In order to analyze the converter, it is assumed that all the components
including the switches, diodes, capacitors, and inductors are ideal. The capacitances of all capacitors are considered
large enough so that the voltages across the capacitors are remaining constant during the entire switching interval. The
operating principles and steady-state analysis are presented in detail as follows.
3.1 | Operating states analysis
Based on the conduction state of the switches (S1 and S2) and the diodes (D1 ! D3), the operation of the proposed con-
verter can be divided into three operating modes as presented in Table 1. The PT-2 shows the switching state I and II
during CCM operation. However, it shows three switching states during DCM operation. The equivalent circuits of the
PT-2 for switching states I, II, and III are depicted in Figure 3A,B,C, respectively. The steady-state analysis of the PT-2
is presented here for CCM operation using switching state I and II. Similar analysis has been extended for the DCM
operation also using the equivalent circuit of switching state III as shown in Figure 3C, where all the semiconductor
devices are in OFF state. Figure 4 shows the key steady-state waveforms during CCM and DCM operations. Analyses of
the dc-dc power converter during the switching states are mainly based on the inductor voltages and capacitor currents.
Hare, the inductor voltages are denoted as VL1 and VL2 for L1 and L2, respectively and the capacitors (C1 ! C3) currents
are denoted as iC1_ch ! iC3_ch during charging mode and iC1_dis ! iC3_dis during discharging mode.
3.1.1 | Operating state I
In this state, the switches are in ON-state, the diodes D1 and D2 are reverse biased, and D3 is forward biased. The equiv-
alent circuit of this operating state is depicted in Figure 3A. During this state, both inductors charge, capacitors C1 and
C2 discharge, and capacitor C3 charges. By using Kirchhoff's voltage law (KVL) and Kirchhoff's current law (KCL) on
the equivalent circuit shown in Figure 3A, the following voltage and current expressions are obtained.
V L1 ¼ V L2 ¼ V in ð1Þ
iC1_dis ¼ iC2_dis ¼ ðI 0 þ iC3_ch Þ ð2Þ
During this state, the steady-state output voltage expression can easily be written in terms of input and capacitor volt-
ages as follows.
V 0 ¼ ðV in þ V C1 þ V C2 Þ ð3Þ
3.1.2 | Operating state II
In this state, the switches are in OFF-state, the diodes D1 and D2 are forward biased, and D3 is reverse biased. The
equivalent circuit of this operating state is shown in Figure 3B. In this state, the inductors discharge to charge the
capacitors C1 and C2, and the output capacitor C3 discharges through load-R. By using KVL and KCL on the state II
equivalent circuit presented in Figure 3B, the following expressions are obtained.
TABLE 1 Operating states of the proposed Topology-2
Switching state S1 S2 D1 D2 D3
I ON ON OFF OFF ON
II OFF OFF ON ON OFF
III OFF OFF OFF OFF OFF
ð4Þ
ð5Þ
ð6Þ
SHAW ET AL.
Equivalent circuits of the PT-2. (A) Operating state-I. (B) Operating state-II. (C) Operating state-III

I L2
2
ðV in V C1 Þ
¼
2
iC3_dis ¼ I 0
I L1
2
V L1 ¼ V L2 ¼
iC1_ch ¼ iC2_ch ¼
FIGURE 3
1270
SHAW ET AL. 1271
FIGURE 4 Key steady-state waveforms of the PT-2. (A) During CCM operation. (B) During DCM operation
3.1.3 | Operating state III
In this state, the switches are in OFF-state and all the diodes D1 ! D3 are reverse biased. The equivalent circuit of this
operating state is depicted in Figure 3C. This operating state is for the PT-2 when it operates only in DCM. In this oper-
ating state, the voltages across L1 and L2 equal zero and the current through all capacitors are zero.
V L1 ¼ V L2 ¼ 0 ð7Þ
iC1_dis ¼ iC2_dis ¼ 0 ð8Þ
iC3_dis ¼ 0 ð9Þ
3.2 | Analysis for CCM operation
In CCM operation, the PT-2 has two operating states, namely: state I and state II. The key steady-state waveforms of the
CCM operation are shown in Figure 4A. The voltage gain, the voltage and current stresses on components, design equa-
tion for passive components, and the efficiency analysis of the PT-2 are presented in the upcoming subsections.
3.2.1 | Voltage gain expression
During steady-state, the average voltages across inductors are zero within one switching time period and mathemati-
cally defined as (10).
1272 SHAW ET AL.
Z DT s Z Ts
1
V L1 dt þ V L1 dt ¼ 0 ð10Þ
Ts 0 DT s
Using the inductor voltages expressions during operating stage-1 and stage-2 in (10) results in (11).

ðV in V C1 Þ
ðV in ÞðDÞ þ ð 1 DÞ ¼ 0 ð11Þ
2
Simplification of (11) results in the voltages across intermediate capacitors C1 and C2 as given by (12).

1þD
V C1 ¼ V C2 ¼ V in ð12Þ
1D
Now utilizing the capacitor voltages expressions in (3), the output voltage expression is obtained in terms of the
input voltage Vin and its further simplification results in the following voltage gain expression for CCM operation.

V0 3þD
M¼ ¼ ð13Þ
V in 1D
3.2.2 | Voltage stresses on semiconductor devices
The voltage stresses on switches (S1 and S2) are equal and are given by (14).

V in þ V C1 V in
V S1 ¼ V S2 ¼ ¼ ð14Þ
2 ð 1 DÞ
Now by using (13) and (14), the switch voltage stresses can be represented in terms of output voltage as (15).
V0
V S1 ¼ V S2 ¼ ð15Þ
ð3 þ D Þ
Similarly, the voltage stresses across all diodes (D1, D2, and D3) are equal and is obtained as:
2V in
V D1 ¼ V D2 ¼ V D3 ¼ ðV 0 V C1 Þ ¼ ð16Þ
ð 1 DÞ
Now by using (13) and (16), the diode voltage stresses can be denoted in terms of output voltage as (17).
2V 0
V D1 ¼ V D2 ¼ V D3 ¼ ð17Þ
ð3 þ DÞ
3.2.3 | Current stresses on semiconductor devices
The source current (Iin) is decided by the magnitude of load (I0) and the operating duty cycle (D). Assuming the power
converter has very negligible losses and by utilizing the power balance equation ðV in I in ¼ V 0 I 0 Þ along with voltage
gain expression (13) results in the average source current (Iin) expression given by (18).
SHAW ET AL. 1273
I in ¼ ð3 þ DÞI 0 =ð1 DÞ ð18Þ
By applying the charge balance rule for capacitors C1 and C3, as given by (19), using (2), (5), and (6), the average
inductor currents, and the charging and discharging currents of all capacitors are obtained as given in (20) to (22).

ðiC1_dis ÞðDÞ ¼ ðiC1_ch Þð1 DÞ
ð19Þ
ðiC3_ch ÞðDÞ ¼ ðiC1_dis Þð1 DÞ
2I 0
I L1 ¼ I L2 ¼ ¼ IL ð20Þ
ð1 DÞ

iC1_ch ¼ iC2_ch ¼ I 0 =ð1 DÞ
ð21Þ
iC1_dis ¼ iC2_dis ¼ ðI 0 =DÞ

iC3_ch ¼ ð1 DÞI 0 =D
ð22Þ
iC3_dis ¼ I 0
By using Equations (20) to (22), the current stresses on the switches (iS1 and iS2) and the current stresses on the
diodes (iD1 ! iD3) can be obtained as given in (23) to (25).
ð1 þ DÞI 0
iS1 ¼ iS2 ¼ ðI L1 þ iC1_dis Þ ¼ ð23Þ
ð1 DÞD
I0
iD1 ¼ iD2 ¼ ðI L1 iC1_ch Þ ¼ ð24Þ
ð1 D Þ
iD3 ¼ iC1_dis ¼ ðI 0 =DÞ ð25Þ
3.2.4 | Passive components design
The voltage across inductors during operating stage-1, defined by (1), is utilized to obtain the expression for inductance
L in terms of ΔiL . When the maximum allowable ripple current is known, the minimum inductance value for L1 and L2
can easily be obtained using (26).

V in D
L ¼ L1 ¼ L2 ≥ ð26Þ
ΔiL f s
The discharging current expressions for capacitor C1 and C2, defined by (21), are utilized to obtain the expression
for capacitance C in terms of ΔvC . Similarly, from the discharging current expression of capacitor C3, defined by (22), its
design equation is obtained in terms of ΔvC3 . Thus, when the maximum allowable ripple voltages are known, the mini-
mum capacitance values for C1, C2, and C3 can be easily obtained using (27) and (28).

V0
C ¼ C1 ¼ C2 ≥ ð27Þ
RΔvC f s

V 0 ð1 D Þ
C3 ≥ ð28Þ
RΔvC3 f s
1274 SHAW ET AL.
3.3 | Boundary condition analysis
In boundary conduction mode (BCM), the current flowing through L1 and L2 just touches the zero line in each
switching cycle. More specifically, this operating condition implies that the lowest value of inductor current becomes
zero. The lowest value of the inductor current for the PT-2 can be computed by using average inductor current (20) and
the ripple current ðΔiL Þ as follows:

ΔiL 2I 0 V in D
I LðlowestÞ ¼ I L ¼ ð29Þ
2 1D 2Lf s
Now by equating the lowest inductor current expression to zero, the following condition is obtained for BCM operation.
" #
4L D ð1 DÞ2
¼ ð30Þ
RT s ð3 þ DÞ

By defining k ¼ 4L=ðRT s Þ and k crit ðDÞ ¼ Dð1 DÞ2 =ð3 þ DÞ, the PT-2 ensures CCM operation when k > k crit ðDÞ,
whereas it will operate in DCM when k < kcrit ðDÞ.
3.4 | Analysis for DCM operation
During DCM operation, the PT-2 shows all three operating states, namely: state I, state II, and state III. The equivalent
circuits for all three operating states are shown in Figure 3. The first two operating states are same as in CCM, while
the state III is only for the DCM operation. The time-period of the state I is DTs, time-period of the state II is DxTs, and
the time-period of the state III is (1-D-Dx)Ts. The key steady-state waveforms of the DCM operation are shown in
Figure 4B. Similar to CCM operation, by using volt-sec balance to inductor L1, the voltages across capacitors are
obtained as:

2D þ Dx
V C1_DCM ¼ V C2_DCM ¼ V in ð31Þ
Dx
Now, by substituting (31) in (3), the voltage gain expression during DCM operation can be obtain as given by (32).

V0 4D þ 3Dx
¼ ð32Þ
V in DCM Dx
In DCM operation, the peak inductor current through L1 and L2 is given by:

V in D
iLðpeakÞ_DCM ¼ ð33Þ
Lf s
Similarly, the switch and diode voltage stresses during DCM operation are obtained as follows:
V0
V S1_DCM ¼ V S2_DCM ¼ ð34Þ
ð3 þ DÞ
2V 0
V D1_DCM ¼ V D2_DCM ¼ V D3_DCM ¼ ð35Þ
ð 3 þ DÞ
SHAW ET AL. 1275
4 | POWER L OS S A ND EFFIC IENCY ANALYSIS
The efficiency of any switched-mode power converter depends on the power losses taking place in all the passive com-
ponents (L and C) and the semiconductor devices. Here, the efficiency analysis is presented for PT-2, but it can be easily
extended to other three topologies (PT-4, PT-1, and PT-3). The power losses taking place in the PT-2 are mainly:
(i) power losses in inductors (PL1 and PL2), (ii) power loss in capacitors (PC1, PC2, and PC3), (iii) power loss in the
switches: (a) conduction losses (PS1 and PS2), (b) switching losses (PS1_sw and PS2_sw), and (iv) power loss in diodes (PD1,
PD2, and PD3). The losses in inductors (L1 and L2) and capacitors (C1, C2, and C3) are mainly due to the parasitic resis-
tances. The detailed expressions for power loss computation in the inductors, capacitors, switches, and diodes of the
PT-2 are listed in Table 2. Using the power loss expressions of individual elements listed in Table 2, the total power loss
ðPLoss Þ in the PT-2 will be:
PLoss ¼ PL1 þ PL2 þ PC1 þ PC2 þ PC3 þ PS1 þ PS1_sw þ PS2 þ PS2_sw þ PD1 þ PD2 þ PD3 ð36Þ
If P0 is the power transferred to load-R, then the efficiency (ɳ) of the PT-2 can be obtained by using (37).

P0
η ð %Þ ¼ 100 ð37Þ
P0 þ PLoss
5 | COMPA RI S ON WI T H OT H E R ST E P - UP DC - DC C O NV E R T E R
TOPOLOGIES
A comprehensive comparison of the proposed topologies and other reported high gain boost converters is presented in
Table 3. This comparison study clearly shows that the proposed topologies have higher voltage gain as compared to
other listed converters with only a total component count (TCC) of 10. However, topologies proposed in8,13,19,20 have
same or higher TCC than the proposed converters with lower voltage conversion ratio as presented in Table 3. The very
high voltage gain characteristic of these proposed converters (PT-2 and PT-4) can also be seen from the voltage gain
range column of Table 3, where the ideal voltage gain varies from 4 to 19 under the duty cycle variation from 0.2 to 0.8.
From this comparison study it can also be concluded that despite of having very high voltage gain, the switch voltage
TABLE 2 Expressions for Power Loss Computation in PT-2
Elements Power loss expressions

Inductor-L1 PL1 ¼ I 2L1_RMS r L1 (where I L1_RMS ¼ 2I 0 =ð1 DÞ)
Inductor-L2 PL2 ¼ I 2L2_RMS r L2 (where I L2_RMS ¼ 2I 0 =ð1 DÞ)
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
Capacitor-C1 PC1 ¼ I 2C1_RMS r C1 (where I C1_RMS ¼ I 0 ½ð1=DÞ þ ð1=ð1 DÞÞ)
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
Capacitor-C2 PC2 ¼ I 2C2_RMS r C2 (where I C2_RMS ¼ I 0 ½ð1=DÞ þ ð1=ð1 DÞÞ)
r
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

Capacitor-C3 ð1DÞ2
PC3 ¼ I 2C3_RMS r C3 (where I C3_RMS ¼ I 0 D þ ð1 DÞ )
pffiffiffiffi
Switch-S1 PS1 ¼ I 2S1_RMS r DS1 (where I S1_RMS ¼ ð1 þ DÞI 0 = ð1 DÞ D )
PS1_sw ¼ 12 I S1 V S1 ðt ON þ tOFF Þ f s
pffiffiffiffi
Switch-S2 PS2 ¼ I 2S2_RMS r DS2 (where I S2_RMS ¼ ð1 þ DÞI 0 = ð1 DÞ D )
PS2_sw ¼ 12 I S2 V S2 ðt ON þ tOFF Þ f s
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
Diode-D1 PD1 ¼ V f 1 I D1_AVG þ I 2D1_RMS r D1 (where I D1_AVG ¼ I 0 , I D1_RMS ¼ I 0 = ð1 DÞ)
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
Diode-D2 PD2 ¼ V f 2 I D2_AVG þ I 2D2_RMS r D2 (where I D2_AVG ¼ I 0 , I D2_RMS ¼ I 0 = ð1 DÞ)
pffiffiffiffi
Diode-D3 PD3 ¼ V f 3 I D3_AVG þ þI 2D3_RMS r D3 (where I D3_AVG ¼ I 0 , I D3_RMS ¼ I 0 = D)
1276
TABLE 3 Comparison of high step-up boost topologies with the proposed DC-DC converters
Maximum
Total Voltage Switch Maximum intermediate Nature of Voltage gain
L C S D components gain voltage diode voltage capacitor voltage source range for
Topologies count count count count counts (TCC) (M) stress stress stress current D = 0.2 ! 0.8
SL Boost6 2 1 1 4 8 ð1þDÞ V0 V0 -- Non-pulsating 1.5 ! 9
ð1DÞ
Topology in11 2 3 1 2 8 ð1þDÞ V0 V0 V0 Non-pulsating 1.5 ! 9

ð1DÞ ð1þDÞ ð1þDÞ ð1þDÞ
23 ð1þDÞ V0 V0 V0
Topology in 2 3 1 2 8 ð1þDÞ ð1þDÞ ð1þDÞ
Smooth 1.5 ! 9
ð1DÞ
Topology in22 2 3 1 3 9 ð1þDÞ V0 V0 DV 0 Non-pulsating 1.5 ! 9

Topology in7 2 2 1 6 11 ð1þDÞ V0 V0 DV 0 Non-pulsating 1.5 ! 9

ð1DÞ ð1þDÞ ð1þDÞ
KY Boost12 2 3 2 1 8 ð2DÞ V0 V0 V0 Smooth 2.25 ! 6

ð1DÞ ð2DÞ ð2DÞ ð2DÞ
Topology in17 3 3 2 2 10 ð1þ3DÞ V0 2V 0 ð1þDÞV 0 Non-pulsating 2 ! 17

ð1DÞ ð1þ3DÞ ð1þ3DÞ ð1þ3DÞ
Topology in14 4 1 2 7 14 ð1þ3DÞ ð1þDÞV 0 2ð1þDÞV 0 -- Non-pulsating 2 ! 17

ð1DÞ ð1þ3DÞ ð1þ3DÞ
Topology in19 2 3 2 3 10 2 V0 V0 V0 Non-pulsating 2.5 ! 10

ð1DÞ 2 2 2
13 ð3DÞ V0 2V 0 ð1DÞV 0
Topology in 2 3 2 3 10 ð3DÞ ð3DÞ
Non-pulsating 3.5 ! 16
ð1DÞ ð3DÞ


Topology in21 2 4 2 4 12 ð3þDÞ V0 2V 0 ð1þDÞV 0 Non-pulsating 4 ! 19

Proposed 3 3 2 2 10 ð1þ3DÞ V0 2V 0 ð1þDÞV 0 Non-pulsating 2 ! 17

ð1DÞ ð1þ3DÞ ð1þ3DÞ ð1þ3DÞ
Topologies
(PT-1, PT-3)
Proposed 2 3 2 3 10 ð3þDÞ V0 2V 0 ð1þDÞV 0 Non-pulsating 4 ! 19
Topologies
(PT-2, PT-4)
SHAW ET AL.
SHAW ET AL. 1277
and current stress of the proposed topologies are on the lower side as compared to most of the existing boost converters.
In order to achieve higher voltage gain, many topologies utilize a large number of diodes and inductors as in.7,8,14,20
However, the PT-2 utilizes only 3 diodes and 2 inductors to provide a very high voltage gain which makes the system
efficient and less bulky. In Table 3, the topology in21 has the same voltage gain as the PT-2 and PT-4 topologies, but it
utilizes a higher number of components with a TCC of 12. The PT-1 and PT-3 topologies have identical voltage gain as
converter reported in14 with lower component counts. The topology in14 has a higher number of inductors and diodes
with a TCC of 14, but the PT-1 and PT-3 have a TCC of 10. Additionally, the PT-1 and PT-3 exhibit reduced switch and
diode voltage stresses as compared to the topology in.14
The very high voltage gain feature of the proposed topologies is also verified through the comparison plot as shown
in Figure 5A. Figure 5A presents the ideal voltage gain variation of all the topologies listed in Table 3 with the increase
in duty ratio from 0 to 0.8, which implies that the voltage gain of the proposed topologies is higher as compared to all
other listed topologies for all range of duty cycle. Similarly, the low switch voltage stress feature of the proposed con-
verters is presented in Figure 5B. It shows the normalized switch voltage stress variation of all topologies of Table 3
with the rise in duty ratio from 0 to 0.8. Figure 5B clearly shows that the voltage stresses across the switches are lower
for the PT-2 and PT-4 as compared to the rest of the topologies for the entire range of duty ratio variation. The maxi-
mum voltage stress on diodes, normalized by load voltage, is also plotted for all topologies with the variation in duty
F I G U R E 5 Voltage gain, switch, and diode voltage stress comparison with existing high-gain topologies. (A) Voltage gain variation with
duty ratio. (B) Normalized switch voltage stress variation with duty ratio. (C) Normalized diode voltage stress variation with duty ratio
1278 SHAW ET AL.
ratio, and the comparison plot is depicted in Figure 5C. Here, Figure 5C clearly shows that the voltage stresses across
the diodes of PT-2 and PT-4 are lower as compared to many of the topologies except the topologies in.8,19,20 Hence, for
all ranges of duty ratio variation, the proposed topologies with very high voltage boosting ability exhibit low switch and
diode voltage stresses.
In order to have a quantitative comparative analysis between the proposed topologies and existing boost converter
topologies, the voltage gain and normalized voltage stresses are presented in the bar-chart form at the nominal duty
ratio (i.e., D = 0.6). The voltage gain at D = 0.6 is computed for all the topologies using the gain expressions listed in
Table 3 and plotted in the bar chart as shown in Figure 6A, which shows that the PT-2 and PT-4 have the highest volt-
age gain among all. From Figure 6A, it is also evident that proposed PT-1 and PT-3 have the second-highest voltage gain
among all topologies at the nominal operating point. Similarly, the normalized switch and diode voltage stresses are
obtained at D = 0.6 from their respective expressions listed in Table 3 and compared in the bar chart as shown in
Figure 6B,C, respectively. From Figure 6B, it is clear that at the nominal operating point the PT-2 and PT-4 have the
lowest switch voltage stress. The normalized diode voltage stresses of proposed topologies are also on the lower side as
compared to all the topologies as displayed in Figure 6C. Hence, this comparison study implies the proposed boost con-
verter topologies provide very high voltage gain with reduced switch and diode voltage stresses.
6 | R ES U L T S A N D D I S C U S S I O N
In order to demonstrate the performance features of the PT-2, a 250 W, 50 kHz prototype is built in the laboratory.
The set-up picture of the experimental prototype is shown in Figure 7, which includes the following: (a) PT-2,
(b) gate diver board, (c) FPGA controller board, (d) load, and (e) digital oscilloscope. For the proposed converter,
the input voltage has been selected as 48 V with an operating switching frequency of 50 kHz. The switches S1 and
F I G U R E 6 Bar chart comparison of voltage gain and voltage stresses with other topologies at D = 0.6. (A) Voltage gain. (B) Normalized
switch voltage stress variation. (C) Normalized diode voltage stress
SHAW ET AL. 1279
FIGURE 7 Experimental set-up picture for the PT-2
TABLE 4 Specifications and components of the PT-2
Description Values
Input voltage (Vin) 48 V
Output voltage (V0) 408 V
Rated power (P0) ≈ 250 W
Duty cycle (D) ≈ 0.6
Switching frequency (fs) 50 kHz
Inductors (L1 = L2) 600 μH
Capacitors (C1 = C2) 100 μF
Output capacitor (C3) 220 μF
Switches (S1 and S2) C2M0160120D
Diodes (D1, D2 and D3) STTH6012
S2 are C2M0160120D power MOSFET and diodes (D1, D2, and D3) STTH6012 have been used for the development
of the PT-2 prototype. By following the design equations discussed in Section 3, the inductors (L1 and L2) and capac-
itors (C1, C2, and C3) are respectively designed to limit the current and voltage ripples within the allowable limit
(ΔiL ≤ 30% and ΔvC ≤ 5%). The experimental specifications and final passive components values of the PT-2 proto-
type are listed in Table 4.
The high voltage gain features offered by the PT-2 are experimentally verified and the measured observations are
presented in Figure 8. Here, Figure 8A shows the measured voltage gain variation of PT-2 with the duty ratio deviation
from 0.2 to 0.75 along with its analytical characteristics. The analytical gain characteristics is drawn by using the ideal
voltage gain expression given by (13) in Section 3. The measured voltage gain increases with an increase in duty ratio
(D) of the converter and the variation is in close agreement with the analytical expression defined by (13). At higher
duty cycles, the experimental gain reduces from that theoretical gain due to the loading impact. Similarly, the experi-
mental and analytical efficiency of PT-2 is presented in Figure 8B for the supply voltages of 48 V. The analytical
SHAW ET AL.
Experimental voltage gain and efficiency of the PT-2. (A) Voltage gain variation with duty ratio. (B) Efficiency variation with
Power loss distribution of the PT-2 at P0 ≈ 246 W

FIGURE 8
FIGURE 9
load power
1280
SHAW ET AL. 1281
efficiency of the proposed topology is obtained by using the loss analysis method described in Section IV with the
parameter specifications detailed in Table 4. It is seen that the efficiency plots drop with the increase in load power (P0)
due to loading impact. The peak efficiency of the PT-2 prototype is 95.4% for P0 = 120 W and it shows a minimum effi-
ciency of 91.5% for P0 = 430 W. Thus, it is clearly evident that the PT-2 exhibits more than 90% efficiency under wide
range of load variations. The analytical power loss distribution among the components of PT-2 is presented in Figure 9.
F I G U R E 1 0 Steady-state experimental results of the PT-2 for D = 0.6. (A) Input voltage, input current, output voltage, and load
current. (B) Capacitor voltages and output voltage. (C) Inductor currents. (D) Switch voltages. (E) Diode voltages
1282 SHAW ET AL.
The minimum loss is taking place in the capacitors that is equal to 11% of the total loss at P0 ≈ 246 W. The percentage
of loss in the switches is 30%, the loss in the diodes is 29%, and loss occurring in the inductors is equal to 30% of the
total losses as depicted in Figure 9.
In order to confirm the converter operation and its high voltage gain feature, Figure 10A shows the experimental
waveform of input/output voltage and current at a duty value of 0.6. With the value of D = 0.6, the voltage gain of
the PT-2 becomes 8.5. Thus, with the input voltage of 48 V, the output voltage has a magnitude of 408 V. The input
current has a peak of 11.5 A. The higher peak current is due to the charging current of the capacitor during mode-I
of operation. At the duty value of 0.6, the average input current and output current attained a value of ≈ 5.6 A and
≈ 0.6 A, respectively. Therefore the efficiency of the proposed converter-2 becomes 92.5% at an output power of
245.5 W.
The presence of voltage multiplier at the downstream of the FTPHGS cell enhances the output voltage of the
PT-2, which is further extended by the addition of input side inductor-switch network. Figure 10B shows the
waveforms of voltages across capacitors C1 and C2 along with the output voltage waveform of the PT-2 at a duty
value of 0.6. At the load voltage of 408 V, the capacitor voltage is half of the output voltage with a voltage of
204 V. Furthermore, Figure 10C shows the current of inductors L1 and L2. As the value of inductors (L1 and L2)
has been selected as 600 μH based on the design Equation (26), the inductor currents are continuous and the
PT-2 works in CCM.
One of the major advantages of the proposed converter is the reduction of the voltage stress of the switches with
higher output voltage magnitude. Figure 10D shows the waveform of gate pulses for the switches along with the voltage
stress of both switches S1 and S2. The magnitude of the gate pulse is from 5 V to 15 V which results in the peak volt-
age stress of the switches as 150 V. The voltage stresses of the diodes are also illustrated in Figure 10E at the duty value
of 0.6, which are also on the lower side as they are less than that of the load voltage.
The operation principle, analytical studies, and experimental results presented in the above paragraphs are during
L1 = L2 of the PT-2. However, during unequal values of inductances (i.e., L1 ≠ L2), the charging slope of the inductor
currents (IL1 and IL2) will be different when they are in parallel and but they follow equal current during discharging
when the inductors are in series. Hence there will be an abrupt change in current during the transition state between
DTs and (1-D)Ts. Here, during experimentation, the inductor values are chosen almost the same (i.e., 600 μH) and this
non-ideal behavior can be easily neglected as the difference between L1 and L2 is very small, which is within 5 μH.
To verify the behavior of the TP-2 during unequal L1 and L2, the simulation results are presented using Matlab
Simulink.34 The operating point and converter specifications are chosen as listed in Table 4 except for the L1 value.
Here the L1 value is selected as 700 μH whereas the L2 value is the same as before, that is, 600 μH to verify the work-
ing of the PT-2 during unequal inductor values. The simulation results are presented in Figure 11 at a duty value of
0.6 with the input voltage of 48 V as shown in Figure 11A along with the output voltage and capacitor voltage wave-
forms of the PT-2. Similarly, the inductor currents and load current waveforms are shown in Figure 11B, which
F I G U R E 1 1 Steady-state simulation results the PT-2 for D = 0.6 during unequal L1 and L2. (A) Input voltage, capacitor C1 voltage, and
load voltage waveforms. (B) Inductor L1 current, inductor L2 current, and load current waveforms
SHAW ET AL. 1283
FIGURE 12 Experimental verification of high voltage gain feature at moderate duty cycles of the PT-2. (A) For D = 0.5. (B) For D = 0.7
clearly depicts the different slopes of the inductor currents during charging interval DTs. It can be seen that the
inductor current IL2 has a higher slope than IL2 as L2 has a lower inductance value than L1. The simulation results
shown in Figure 11 demonstrate the behavior of inductor currents during unequal values of the inductances of the
proposed topologies.
The PT-2 is also tested with the two other values of duty cycles to demonstrate its wide operating range and very
high voltage gain feature. Here, Figure 12A,B depicts the input and output parameters of voltage and current at the
duty value of 0.5 and 0.7, respectively. With the duty value of 0.5, the voltage gain is around 6.70 (V0 ≈ 322 V) and with
the duty value of 0.7, the archived voltage gain becomes 11.35 (V0 ≈ 545 V), which confirms the high voltage gain fea-
ture of the PT-2 at moderate duty ratios. This ascertains that the proposed topology provides a very high voltage gain
over wide range of duty cycle variations, which is an essential quality for the step-up dc-dc converters employed for
renewable energy sources such as solar energy.
7 | C ON C L U S I ON
A new family of transformerless step-up dc-dc converters with very high voltage gain is proposed in this paper by utiliz-
ing distinct four-terminal PWM high-gain switch cells and inductor-switch network. The first two topologies exhibit
identical voltage gain with opposite load voltage polarity. Similarly, the other two structures have the same voltage con-
version ratio with opposite load voltage polarity, which can be applied as per the application requirements. The attrac-
tive features of these non-isolated topologies are that these converters are able to provide a voltage gain of more than
10 at a moderate duty cycle by utilizing a reduced number of passive components and diodes as compared to recently
reported topologies. The voltage and current stresses on switches of the proposed topologies are also on the lower side
in comparison to the existing high-gain boost dc-dc converters.
The detailed operating principle and steady-state analysis are presented for the proposed positive output high step-
up dc-dc converter (PT-2). The theoretical analysis and high voltage boosting capability at reduced switch voltage stress
of this topology is demonstrated through experimental results using a 250 W, 50 kHz laboratory prototype. At nominal
specifications (Vin = 48 V, V0 = 408 V, and P0 ≈ 250 W), an efficiency of about 94.27% is achieved. The proposed dc-dc
boost converters offer a very high voltage gain with additional advantages such as low switch voltage/current stresses
and improved efficiency. These attractive features of the proposed boost topologies make them the apposite choice for
PV/battery grid-tie applications.
DATA AVAILABILITY STATEMENT

Data sharing not applicable to this article as no datasets were generated or analysed during the current study.
ORCID
Priyabrata Shaw https://orcid.org/0000-0001-7880-2386
Atif Iqbal https://orcid.org/0000-0002-6932-4367
1284 SHAW ET AL.
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How to cite this article: Shaw P, Siddique MD, Mekhilef S, Iqbal A. A new family of high gain boost DC-DC
converters with reduced switch voltage stress for renewable energy sources. Int J Circ Theor Appl. 2023;51(3):
1265‐1285. doi:10.1002/cta.3464

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Received: 23 June 2022 Revised: 6 September 2022 Accepted: 21 September 2022

A new family of high gain boost DC-DC converters with

Priyabrata Shaw 1 | Marif Daula Siddique 2 | Saad Mekhilef 3 | Atif Iqbal 2

a. Very high voltage gain at low and moderate duty ratio.

3 | PROPOS ED HIGH-G AIN STEP-U P C ONVERTERS: OPERATION

3.1 | Operating states analysis

3.1.1 | Operating state I

iC1_dis ¼ iC2_dis ¼ ðI 0 þ iC3_ch Þ ð2Þ

3.1.2 | Operating state II

TABLE 1 Operating states of the proposed Topology-2

3.1.3 | Operating state III

iC1_dis ¼ iC2_dis ¼ 0 ð8Þ

3.2 | Analysis for CCM operation

3.2.1 | Voltage gain expression

3.2.2 | Voltage stresses on semiconductor devices

3.2.3 | Current stresses on semiconductor devices

I in ¼ ð3 þ DÞI 0 =ð1 DÞ ð18Þ

iD3 ¼ iC1_dis ¼ ðI 0 =DÞ ð25Þ

3.2.4 | Passive components design

3.3 | Boundary condition analysis

3.4 | Analysis for DCM operation

4 | POWER L OS S A ND EFFIC IENCY ANALYSIS

TABLE 2 Expressions for Power Loss Computation in PT-2

Elements Power loss expressions

Topology in11 2 3 1 2 8 ð1þDÞ V0 V0 V0 Non-pulsating 1.5 ! 9

Topology in22 2 3 1 3 9 ð1þDÞ V0 V0 DV 0 Non-pulsating 1.5 ! 9

Topology in7 2 2 1 6 11 ð1þDÞ V0 V0 DV 0 Non-pulsating 1.5 ! 9

KY Boost12 2 3 2 1 8 ð2DÞ V0 V0 V0 Smooth 2.25 ! 6

Topology in17 3 3 2 2 10 ð1þ3DÞ V0 2V 0 ð1þDÞV 0 Non-pulsating 2 ! 17

Topology in14 4 1 2 7 14 ð1þ3DÞ ð1þDÞV 0 2ð1þDÞV 0 -- Non-pulsating 2 ! 17

Topology in19 2 3 2 3 10 2 V0 V0 V0 Non-pulsating 2.5 ! 10

Topology in8 2 5 1 4 12 ð2þDÞ V0 V0 V0 Non-pulsating 2.75 ! 14

Topology in20 2 5 1 4 12 ð2þDÞ V0 V0 V0 Non-pulsating 2.75 ! 14

Topology in21 2 4 2 4 12 ð3þDÞ V0 2V 0 ð1þDÞV 0 Non-pulsating 4 ! 19

Proposed 3 3 2 2 10 ð1þ3DÞ V0 2V 0 ð1þDÞV 0 Non-pulsating 2 ! 17

FIGURE 7 Experimental set-up picture for the PT-2

TABLE 4 Specifications and components of the PT-2

Power loss distribution of the PT-2 at P0 ≈ 246 W

DATA AVAILABILITY STATEMENT

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