Signed Multiplier Design

Aaditya Kumar Abhay Tiwari Abhishek Yadav

201010201 201010202 201010204.

Department of Electronics and
Communication Engineering
International Institute of Information
Technology, Naya Raipur, India
aaditya20101@iiitnr.edu.in
Department of Electronics and
Communication Engineering
International Institute of Information
Technology, Naya Raipur, India
abhay20101@iiitnr.edu.in
Department of Electronics and
Communication Engineering
International Institute of Information
Technology, Naya Raipur, India
abhisheky20101@iiitnr.edu.in

Abhishek Kerketta

201010203
Department of Electronics and
Communication Engineering
International Institute of Information
Technology, Naya Raipur, India
abhishek20101@iiitnr.edu.in

Abstract—This report presents the design and encoding that takes advantage of the complement
implementation of a signed multiplier circuit. The signed representation of negative numbers.
multiplier is an essential component of many digital signal In this report, we present the design and implementation of a
processing applications, including filtering, convolution, and signed multiplier circuit using Verilog hardware description
modulation. The proposed multiplier design is based on
Booth's algorithm, which is a well-known technique for signed
language. The proposed design is optimized for speed, area,
multiplication. The circuit was implemented using Verilog and power consumption, making it suitable for a wide range
hardware description language and synthesized on a Xilinx of signal processing applications. We also provide
FPGA. The design was optimized for speed and area, and the functional simulations to verify the correctness of the
results were verified using functional simulations. The designed multiplier.
implemented signed multiplier achieved a maximum operating
frequency of 100 MHz and a latency of 15 clock cycles. The
design also showed a low area overhead and power
consumption, making it suitable for low-power applications.
Overall, the designed signed multiplier provides an efficient
and reliable solution for performing signed multiplication in
digital signal processing systems.

Keywords—signed multiplier, digital signal processing,

filtering, convolution, modulation, Booth's algorithm,
Verilog hardware description language, Xilinx FPGA,
speed, area, latency, power consumption, low-power
applications
I. INTRODUCTION
The multiplication operation is an essential function in
digital signal processing applications, such as filtering,
convolution, and modulation. The signed multiplier is a
specific type of multiplier that is capable of performing
multiplication of both signed and unsigned numbers. It is a
critical building block in many signal processing algorithms
that require high accuracy and precision. Fig.. Flowchart of the Signed Multiplier
The signed multiplier circuit is based on Booth's algorithm,
which is an efficient method for signed multiplication. This
algorithm reduces the number of partial products that need
to be calculated, resulting in a faster and more efficient
multiplication process. Booth's algorithm is particularly
useful for signed numbers because it uses a radix-2
 Fig. Genus Window

4. Innovus : Innovus is a physical design tool used to

Fig Block diagram of a 4-bit signed multiplier.
The rest of the report is organized as follows. In the next
section, we describe Booth's algorithm and its
implementation in Verilog. We then present the design
methodology and optimization techniques used to improve
the performance and efficiency of the signed multiplier
circuit. In the following sections, we provide the simulation
results and discuss the performance metrics of the
implemented multiplier. Finally, we conclude the report by
summarizing the key findings and discussing the potential
for future improvements.
II. SOFTWARE REQUIREMENTS
1. Vivado : Vivado is a Xilinx software package used
for the design, verification, and implementation of digital
circuits and systems. It is a complete application with a
variety of features and capabilities that allow users to create
complicated digital creations. Vivado is a sophisticated
digital design tool that is frequently used in the industry to
create complicated digital systems such as FPGAs and
SoCs.
2. NC Launch : NC Launch is a VLSI (Very
Large-Scale Integration) design and manufacturing software
tool. NC Launch is intended to turn electrical design files
into instructions for creating physical IC (integrated circuit)
layouts.
develop and optimize integrated circuits in Very Large Scale
Integration (VLSI). It accomplishes physical layout
placement, routing, and optimisation while considering
considerations like power consumption, time, and area.
Innovus is well-known for its capacity to do concurrent
optimisation, which allows many design goals to be
optimised at the same time. It is frequently used in the VLSI
sector for designing and optimizing high-performance,
low-power integrated circuits.
III. DESIGN FLOW
A. RTL Design
RTL (Register Transfer Level) design describes the
behavior of a circuit at a low level of abstraction, in terms of
the data flow between registers. The registers represent
storage elements that hold data for a specific period of time.
The data is transferred between registers using
combinational logic, which performs arithmetic, logical, and
other operations on the data. Combinational logic is defined
using Boolean equations or truth tables. It involves
describing the behavior of the chip using a hardware
description language (HDL) such as Verilog or VHDL. The
RTL description includes the logic, timing, and functionality
of the chip.

3. Genus : A genus description in VLSI design refers

to the physical features of a collection of standard cells used
to construct digital circuits. The Genus programme is a
physical synthesis and optimisation tool for VLSI digital
architectures. It automates the placement and routing of
standard cells in order to optimize performance, power
consumption, and space. Genus also incorporates power
optimisation capabilities and supports complex process
technologies. Faster design closure, increased design
quality, simplicity of use, and interaction with other tools
are all advantages of utilizing Genus. Genus is an important
tool for VLSI designers to use in automating and optimizing
the physical synthesis process. Fig. Signed Multiplier Code in Vivado
 Fig. Waveform generated

Testbench is a critical tool that allows us to validate the

functioning of the circuit design under various operating
situations. It would be difficult to completely test the circuit
design and assure its correct behaviour without a testbench.
Typically, the testbench is written in a hardware description
language (HDL) such as Verilog or VHDL. It consists of
Fig. Schematic generated three modules: stimulus creation, design-under-test (DUT),
and verification. The constructed testbench is as follows:

Fig. RTL schematic simulation is generated

The Verilog code for an RTL design consists of two

main parts: module declaration and module body. The
module declaration defines the input and output ports of the
module, while the module body defines the behavior of the
module. The following is an example of a Verilog code for a
division operation using restoring division module:

B. Functional Verification
The RTL design is verified using simulation and testing
tools. The goal of functional verification is to ensure that the
design meets the specification and that it operates correctly
in all possible scenarios. Fig. Signed Multiplier
The verification process includes
1. Test case generation
2. Testbench creation
3. Coverage analysis.
 Fig. NClaunch setting design director

Fig. Testbench for Signed Multiplier

● Analyze the synthesis results to ensure that the
signed multiplier meets the target specifications.
C. Synthesis using NClaunch
This includes checking the timing reports and
To synthesize the signed multiplier using NC Launch, you resource utilization reports to ensure that the design
would follow these steps: operates at the target frequency and uses the
● Start NC Launch and create a new project. Select desired amount of area.
the target device for the signed multiplier and the
Verilog file that contains the design description.
● Set the synthesis options for the signed multiplier.
In this case, you would set the optimization goals
to prioritize speed and area, and you would set the
target frequency to the maximum operating
frequency of the multiplier.
● Define the constraints for the signed multiplier.
These include any timing constraints, clock
constraints, and area constraints for the target
device. For example, you may need to specify the
clock frequency, setup and hold times, and
input/output pin locations. Fig. Schematic of Signed Multiplier in Genus
● Run the synthesis process. This step generates a
synthesized netlist for the signed multiplier based ● If necessary, refine the design or the synthesis
on the design description and the synthesis options options and constraints and repeat the synthesis
and constraints. process until the signed multiplier meets the target
specifications.
 vertical strips using METAL 6. We also choose the power
nets(VDD) and ground nets(GND).

Fig.Area Analysis

Fig. Specify Floorplan

Fig. Power Analysis

Fig. Timing Analysis

Fig . Floor Planning design
Overall, the synthesis of the signed multiplier using NC
Launch involves setting the appropriate synthesis options,
constraints, and optimization goals for the target device and
running the synthesis process to generate a synthesized
netlist that meets the desired specifications. The process
may require iterative refinement to achieve the desired
performance and efficiency for the signed multiplier design.

D. Physical Design

1. Floorplanning: It involves dividing the chip into blocks

and defining the placement of the blocks. This step
considers the circuit's functional requirements and timing
constraints, as well as the chip's physical constraints, such Fig. Metal rings for VDD and GND
as size, power distribution, and signal routingThe aspect
ratio is kept to be 0.7 and the value of all the margins (top,
bottom, left, right) is 10. The power planning is also done in
this step. We add horizontal strips using METAL 7 and
 placement considers the interconnects' length and
capacitance to optimize the circuit's performance and
minimize the power consumption. In the pre-placement
process we add the physical cells where the PreCap Cell and
Post Cap Cell are chosen as FILLER D2L HHM. In the full
placement process, we place the standard cells and IO pins

Fig. Horizontal Stripe

Fig Placing Standard Cells

Fig. Vertical Stripe

2. Placement: Placement is a critical step in VLSI physical

design that involves positioning the different components of
the circuit on a chip in a way that optimizes the performance Fig. Physical Cell placement
of the circuit. The main objective of placement is to
minimize the total wire length, minimize the congestion, 3. Clock Tree Synthesis (CTS): Clock tree synthesis
and achieve a balanced distribution of cells. involves generating a tree-like structure that distributes the
The placement process involves several stages: clock signal to all the sequential elements in the circuit. The
● Floorplanning: The first step is floorplanning, clock tree minimizes the clock skew and jitter, ensuring that
which involves partitioning the chip into smaller the circuit operates reliably at the required clock frequency.
regions and defining the boundaries for different The CTS obtained is as follows:
regions.
● Global Placement: After floorplanning, the global
placement stage begins, which involves placing the
cells in the predefined regions while minimizing
the total wire length and congestion.
● Detail Placement: Once the global placement is
complete, the next step is detail placement, which
involves optimizing the cell locations and
interconnect routing to further minimize the wire
length and congestion.
● Legalization: After detailed placement, legalization
is performed to ensure that the placement complies
with the design rules, such as minimum spacing, Fig. Pre CTS setup timing analysis
alignment, and width of the wires.
● Verification: Once the placement is complete, the
design is verified to ensure that it meets the desired
electrical specifications, and any necessary
modifications are made

Gate-level placement involves placing the gates from the

netlist onto the chip's defined block locations. The
 Fig. Pre CTS Setup timing analysis
Fig. Pre CTS timing summary 1

The source pin is the clock pin and all the red pins are the
destination pins.We can observe that the total real time is
reduced from 2 seconds to 0 seconds. We also check the
timing report of the hold mode and find that the real hold
time is 7ns.

4. Routing:Routing is a crucial step in the VLSI physical

design process that involves connecting the various circuit
components on a chip with metal wires to form a functional
integrated circuit. It is the process of creating a physical
wire network that connects the input and output pins of a
chip to the appropriate internal nodes.
Fig. Pre CTS timing summary 2

The routing process involves several stages:

● Netlist Generation: The first step is to generate a
netlist, which is a list of all the electrical
connections required between various components
of the integrated circuit.
● Placement: After generating the netlist, the
placement stage involves positioning the different
components of the circuit in a way that optimizes
the performance of the circuit.
● Global Routing: Once the placement is done, the
next step is global routing, which involves
determining a rough path for the wires to connect
different components.
● Detailed Routing: After global routing, detailed
Fig. Routing routing is performed to connect the nets that were
left unconnected in the global routing stage. This
involves determining the exact path of each wire,
considering various design rules such as minimum
spacing, width, and length of the wires.
● Verification: Once the routing is complete, the
design is verified to ensure that it meets the desired
electrical specifications, and any necessary
modifications are made.

Here, we fill the empty spaces between the standard cells

using the filler cells or the dummy cells.Post routing we
again check the timing summary of the hold mode and
found that the real time got reduced to 0 seconds from 7ns.

Fig. Pin generation


Fig. Post CTS timing summary
Fig. Spaces between standard cells are unfilled
Fig. Filling Spaces between Standard Cells with dummy
cells
Fig. Status Complete Global Routing
E. Result
The GDS (Graphic Data System) file is the final output of
the physical design process of a digital circuit. It contains
the complete layout information of the circuit, including the
placement of gates, routing of interconnects, and other
physical details. The GDS file is the format used by
foundries to manufacture the chip.
Fig. GDS File named chip_design successfully
generated
F. Conclusion
To summarize, the design process of a VLSI circuit for a
Signed Multiplier involves a sequence of vital stages,
including RTL design, functional verification, synthesis,
physical design, and GDS file generation. All the stages are
equally significant for achieving a successful
implementation of the circuit. The functional verification
stage plays a critical role in verifying if the design meets all
the functional requirements. Clock tree synthesis and
routing are also important for ensuring the circuit meets the
timing and power constraints. The GDS file is the ultimate
outcome of the design process and is essential for the
successful fabrication and functionality of the integrated
circuit..
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