ECE 

442
Solid‐State Devices & Circuits

15. Advanced Techniques

Jose E. Schutt-Aine
Electrical & Computer Engineering
University of Illinois
jschutt@emlab.uiuc.edu

Jose E. Schutt‐Aine ‐ ECE 442 1
 Cascode Current Mirror
In addition to diode-
connected transistor Q1,
Q4 is used to provide
suitable bias gate voltage
for Q3

Ro ≅ g m 3 ro 3 ro 2

The cascode mirror

current has a very high
output impedance

Jose E. Schutt‐Aine ‐ ECE 442 2
MOS Folded Cascode Amp

Jose E. Schutt‐Aine ‐ ECE 442 3
 MOS Folded Cascode
1. CS transistor with CG transistor of opposite
polarity
2. Q1 and Q2 for the differential input pair and act
as CS amplifiers
3. Q3 and Q4 are the cascode transistors with
their gates tied to incremental ground
4. Output resistance of current source needed to
be high Î use cascode current mirror
5. Transistors Q5-Q8 make up cascode current
mirror
6. Selecting IB=I forces all transistors to operate
at current I/2
Jose E. Schutt‐Aine ‐ ECE 442 4
MOS Folded Cascode Amp

Jose E. Schutt‐Aine ‐ ECE 442 5
 Input Common-Mode Range
Connect both input together to a source VICM. Q1 and
Q2 operate in saturation at all timesÎVICMmax should
be Vtn above voltage at drains of Q1-Q2
VICM max = VDD − VOV 9 + Vtn
This value can be larger than VDDÎsignificant
improvement over the case of the 2-stage circuit.
Minimum value of VICM is

VICM min = −VSS + VOV 11 + VOV 1 + Vtn

Jose E. Schutt‐Aine ‐ ECE 442 6
 Input Common-Mode Range
Value of VICMmin is not sufficiently low. VBIAS3 should
be selected to provide required current I while
operating Q11 at low overdrive voltage

−VSS + VOV 11 + VOV 1 + Vtn ≤ VICM ≤ VDD − VOV 9 + Vtn

To maximize the allowable positive swing of vo (and
VICMmax), select the value of VBIAS1 so that Q10
operates at the edge of saturation

VBIAS 1 = VDD − V0V 10 − VSG 4

Jose E. Schutt‐Aine ‐ ECE 442 7
 Output Voltage Swing
The upper limit of vo will be
vo max = VDD − VOV 10 − VOV 4

This is two overdrive voltages below VDD Î not

good. However, lowest possible vo is when Q6
reaches the edge of saturation
vo min = −VSS + VOV 7 + VOV 5 + Vtn

This is two overdrive voltages plus a threshold

voltage above –VSS. Can be alleviated by using
modified mirror circuit.
Jose E. Schutt‐Aine ‐ ECE 442 8
 MOS Folded Cascode Amp

Small-Signal Incremental Circuit

Jose E. Schutt‐Aine ‐ ECE 442 9
 Voltage Gain
Amp is a transconductance amplifier with an infinite
input resistance a transconductance Gm and an
output resistance Ro
2( I / 2) I
Gm = g m1 = g m 2 = =
VOV 1 VOV 1
Output resistance is
Ro = Ro 4 & Ro 6
Ro4 is the output resistance of the CG transistor Q4
Ro 4 ≅ ( g m 4 ro 4 )( ro 2 & ro10 )
Jose E. Schutt‐Aine ‐ ECE 442 10
 Voltage Gain

Ro6 is given by Ro 6 ≅ g m 6 ro 6 ro8

From which

Ro = ⎡⎣ g m 4 ro 4 ( ro 2 & ro10 ) ⎤⎦ & ( g m 6 ro 6 ro8 )

The DC open-loop gain is Av = GmRo

{ }
Av = g m1 ⎡⎣ g m 4 ro 4 ( ro 2 & ro10 ) ⎤⎦ & ( g m 6 ro 6 ro8 )

Jose E. Schutt‐Aine ‐ ECE 442 11
 Output Impedance

Output impedance of folded cascode amp is in

the order of
Ro ∝ g rm o
2

This is high. However, with negative feedback

using voltage sampling, it becomes

Rof = 1/ g m1
which is much lower

Jose E. Schutt‐Aine ‐ ECE 442 12
 Frequency Dependence
1. Cascode configuration has excellent high-
frequency response
2. The first two poles are at very high
frequencies
3. Primary purpose of op amp is to feed highly
capacitive loads Î pole at the output
becomes dominant.

Vo Gm Ro
=
Vid 1 + sCL Ro

Jose E. Schutt‐Aine ‐ ECE 442 13
 Frequency Dependence

The dominant pole has a frequency fP given by

1
fP =
2π CL Ro

And the unity-gain frequency ft is given by

Gm
f t = Gm Ro f P =
2π CL

Jose E. Schutt‐Aine ‐ ECE 442 14
 Folded Cascode Design
Design a folded with I = 200 µA, IB= 250 µA, and
|Vov| = 0.25 V for all devices. Use kn’=100 µA/V2,
kp’=40 µA/V2, |VA’| = 20 V/µm, VDD = VSS = 2.5 V, and
|Vt|=0.75 V. All devices have L=1 µm. use CL= 5 pF.
Find ID, gm, ro and W/L for all transistors

From I and IB, we can determine ID for each

transistor.The transconductance is given by:

2I D 2I D
gm = =
Vov 0.25

Jose E. Schutt‐Aine ‐ ECE 442 15
 Folded-Cascode Amp Design

and the output resistance from

VA 20
ro = =
ID ID
The W/L ratio for the devices is given by:

⎛W ⎞ 2 I Di
⎜ ⎟ =
⎝ L ⎠i k 'Vov
2

Jose E. Schutt‐Aine ‐ ECE 442 16
 Folded-Cascode Amp Design Table

Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11
ID 100 100 150 150 150 150 150 150 250 250 200
(µA)

gm 0.8 0.8 1.2 1.2 1.2 1.2 1.2 1.2 2.0 2.0 1.6
(mA/V)

ro 200 200 133 133 133 133 133 133 80 80 100

(kΩ)

W/L 32 32 120 120 48 48 48 48 200 200 64

Jose E. Schutt‐Aine ‐ ECE 442 17
 Folded-Cascode Amp Design
Note that for all transistors,

g m ro = 160 V / V
VGS = 1.0 V
Input common-mode range is

−1.25 V ≤ VICM ≤ 3 V
Output voltage swing is

−1.25 V ≤ vo ≤ 2 V
Jose E. Schutt‐Aine ‐ ECE 442 18
 Folded-Cascode Amp Design
Calculate Ro4

Ro 4 = 160 ( 200 & 80 ) = 9.14 M Ω

Calculate Ro6

Ro 6 ≅ g m 6 ro 6 ro8 = 21.28 M Ω

The output resistance Ro can then be found as

Ro = Ro 4 & Ro 6 = 6.4 M Ω

Jose E. Schutt‐Aine ‐ ECE 442 19
 Folded-Cascode Amp Design
Voltage gain is
Av = Gm Ro = 0.8 × 10−3 × 6.4 × 106 = 5120 V / V
Unity gain bandwidth
−3
Gm 0.8 × 10
ft = = = 25.5 MHz
2π CL 2π × 5 × 10 −12

Dominant-pole frequency is

f t 25.5 MHz
fP = = = 5 Hz
Av 5120
Jose E. Schutt‐Aine ‐ ECE 442 20
 Widlar Current Source

A resistor RE is included in
the emitter lead of Q2

⎛ I REF ⎞
I O RE = VT ln ⎜ ⎟
⎝ IO ⎠
The Widlar circuit provides
small constant current using
relatively small resistors
Îsavings in chip area

Jose E. Schutt‐Aine ‐ ECE 442 21
 Design of Op Amps

1. Designer starts with building blocks whose

performance can be analyzed to a first order
approximation by hand

2. This step provides insight to the designer as

the design of the circuit develops

3. At some point designer must turn to computer

analysis programs such as SPICE. This will
provide speed and accuracy to the design
process

Jose E. Schutt‐Aine ‐ ECE 442 22
 The 741 Op Amp
1. Three-stage amplifier: differential input,
single-ended high-gain stage and output
buffering stage

2. Several transistors, few resistors and only

one capacitor

3. General-purpose op amp that requires two

power supplies

Jose E. Schutt‐Aine ‐ ECE 442 23
741 Op Amp

Jose E. Schutt‐Aine ‐ ECE 442 24
General Strategy for Analyzing the 741
1. Identify the individual stages with their
respective transistors. For each stage
determine the role of the transistors

2. Perform a stage by stage DC analysis of the

circuit. Determine the bias points and mode
of operation for each transistor.

3. Perform the small-signal analysis of each

stage. Develop an incremental model model
and find the parameters of the model

Jose E. Schutt‐Aine ‐ ECE 442 25
General Strategy for Analyzing the 741 (cont’)

1. For each equivalent circuit, calculate gain,

input and output resistances.

2. Determine overall gain of circuit as well as

input and output impedance

3. Perform high-frequency analysis of circuit to

get an estimate for the poles.

4. Use SPICE to fine tune analysis

Jose E. Schutt‐Aine ‐ ECE 442 26
741 Op Amp

Jose E. Schutt‐Aine ‐ ECE 442 27
 741 Op Amp

• Bias Strategy
– IREF is generated by mirror Q11-Q12 and R5
– Q8-Q9 current mirror
– Q13 double-collector lateral pnp device; Q12 and Q13
form a two-output current mirror
– Q13B provides bias current Q17
– Q13A provides bias current for the output stage
– Q18 and Q19 provide VBE drops to Q14 and Q20

Jose E. Schutt‐Aine ‐ ECE 442 28
 741 Op Amp – Input Stage

• Input Stage
– Transistors Q1 through Q7 make up the input stage
– Bias is performed by transistors Q8, Q9 and Q10
– Q1 and Q2 form a differential emitter-follower pair
– Q3 and Q4 form a differential common-base pair
– Q5, Q6 and Q7 form the load/current mirror to the
input stage
– Q3 and Q4 also perform dc level shifting to allow
both positive and negative swings

Jose E. Schutt‐Aine ‐ ECE 442 29
 741 Op Amp – Second Stage

• Second Stage
– Transistors Q16, Q17 and Q13B make up the
intermediate stage
– Q16 acts as an emitter follower
– Q17 is a common emitter amplifier
– Output of second stage is at collector of Q17
– Capacitor CC provides Miller compensation
– Capacitor CC occupies large area in chip

Jose E. Schutt‐Aine ‐ ECE 442 30
 Amplifier - Class B Operation
• Class B Amp
– Arrangement saves power
– Transistors turn on only
when signal is applied
– npn sources current and pnp
sinks current
– Both transistors are cutoff
when vI = 0Îcrossover
distortion

Jose E. Schutt‐Aine ‐ ECE 442 31
 741 Op Amp – Output Stage

• Output Stage
– Class AB operation that
reduces crossover distortion
– Transistors Q14 and Q20 make
up output stage
– Q18 and Q19 provide bias to Q14
and Q20

Jose E. Schutt‐Aine ‐ ECE 442 32
 741 Op Amp – Input Stage DC Analysis

• Input Stage
– Q11 & Q10 are a Widlar
current source

Transistors Q1 through Q4,

Q8 and Q9 form a negative
feedback loop that
stabilizes the value of I

Jose E. Schutt‐Aine ‐ ECE 442 33
 741 Op Amp – Input Stage DC Analysis

IC 6  I

IC 5  I

2I VBE 6 + IR2
IC 7  I E 7 = +
βN R3
I
VBE 6 = VT ln
IS

Jose E. Schutt‐Aine ‐ ECE 442 34
 741 Op Amp – Output Stage DC Bias

• Output Stage
– Q13 delivers a
current of 0.25 IREF
– Class AB operation

Jose E. Schutt‐Aine ‐ ECE 442 35
 Small-Signal Analysis – Input Stage
vi
ie =
4re
re is the emitter
resistance of Q1-Q4

VT 25 mV
re = = = 2.63 k Ω
I 9.5 µ A

Rid = 4 ( β N + 1) re

For βN = 200, we obtain Rid = 2.1 MΩ

Jose E. Schutt‐Aine ‐ ECE 442 36
 Small-Signal Analysis – Input Stage
io = 2α ie
io α
Gm1 ≡ =
vi 2re
re = 2.63 k Ω

α 1

Gm1 = 1/ 5.26 mA / V

Jose E. Schutt‐Aine ‐ ECE 442 37
 Small-Signal Analysis – Input Stage
Output resistance of input stage. Seen from collector of Q6

Ro = ro ⎡⎣1 + g m ( RE & rπ ) ⎤⎦

RE=re=2.63 kΩ and ro=VA/I

where VA=50 V and I=9.5
µAÎro=5.26 MΩ

Jose E. Schutt‐Aine ‐ ECE 442 38
 Input Stage – Incremental Model

Develop equivalent circuit for input stage

Jose E. Schutt‐Aine ‐ ECE 442 39
Small-Signal Analysis – Second Stage

Jose E. Schutt‐Aine ‐ ECE 442 40
 Second Stage – Incremental Model

Develop equivalent circuit for second stage

Jose E. Schutt‐Aine ‐ ECE 442 41
Small-Signal Analysis – Second Stage
Input Resistance
Ri2 is found by inspection:

Ri 2 = ( β16 + 1) ⎡⎣ re16 + R9 & ( β17 + 1)( re17 + R8 ) ⎤⎦

Ri 2 = 4 M Ω
Jose E. Schutt‐Aine ‐ ECE 442 42
Small-Signal Analysis – Second Stage
Transconductance
The transconductance Gm2 is the output current to
input voltage
( R9 & Ri17 )
α vb 7 vb17 = v12
ic17 =
re17 + R8
( R9 & Ri17 ) + re16

Ri17 = ( β17 + 1)( re17 + R8 )

ic17
Gm 2 ≡ = 6.5 mA / V
vi 2
Jose E. Schutt‐Aine ‐ ECE 442 43
 Small-Signal Analysis – Second Stage
Output Resistance
Find resistance looking into into output terminal

Ro 2 = ( Ro13 B // Ro17 )

First component

Ro13 B = ro13 B = 90.9 k Ω

Second component is found
looking into collector of Q17

Ro17 = 787 k Ω Ro 2 = 81 k Ω
Jose E. Schutt‐Aine ‐ ECE 442 44
 Small-Signal Analysis – Output Stage

• Characteristics
– AB class circuit
– Driven by Q17
– Q23 is follower
– Q18 & Q19
providing bias
– Q14 & Q20 are
output transistors

Jose E. Schutt‐Aine ‐ ECE 442 45
 Output Stage
Output Voltage Limits
Maximum positive voltage limited by saturation of Q13

vo max = VCC − VCEsat − VBE14

About 1V below VCC

Minimum output voltage limited by saturation of Q17

vo min = −VEE + VCEsat + VEB 23 + VEB 20

About 1.5 V above -VEE

Jose E. Schutt‐Aine ‐ ECE 442 46
 Output Stage – Incremental Circuit

Construct model

vo 2 = −Gm 2 Ro 2vi 2
Gm2=6.5 mA/V and Ro2=81 kΩ

Jose E. Schutt‐Aine ‐ ECE 442 47
 Output Stage – Incremental Model
• Finding Rin3
– Assume Q20 to have 5 mA
– Resistance looking into base of Q20 is about β20RL
– Assume β20=50 and RL=2 kΩÎresistance into
Q20=100 kΩ Q18 & Q19 providing bias
– Place above resistance in parallel with resistance
of Q13A (about 280 kΩ) [resistance of Q18-Q19
network small and can be neglected]

Assuming β23=50

Rin 3  β 23 (100 k Ω // 280 k Ω ) = 50 × 74 = 3.7 M Ω

Jose E. Schutt‐Aine ‐ ECE 442 48
 Output Stage – Incremental Model
Looking into emitter of Q23

Ro 2
Ro 23 = + re 23
β 23 + 1
Using Ro2=81 kΩ, β23=50,
re23=25/0.18 = 139 Ω gives
Ro23=1.73 kΩ
Ro 23
Rout = + re 20
β 20 + 1
For β = 50, Rout=34 Ω

Jose E. Schutt‐Aine ‐ ECE 442 49
 Overall Gain
vo vi 2 vo 2 vo
=
vi vi vi 2 vo 2
vo RL
= −Gm1 ( Ro1 // R12 )( −Gm 2 Ro 2 ) Gvo 3
vi RL + Rout
vo
Ao ≡ = −476.1× ( −526.5 ) × 0.97 = 243,147 V / V
vi vo
Ao ≡ = 107.7 dB
vi

Jose E. Schutt‐Aine ‐ ECE 442 50
 741 Op Amp - Frequency Response
Miller capacitance due to CC between the base of Q16 and

Cin = CC (1 + A2 )
ground is

Resistance between the base of Q16 and ground is

Rt = ( Ro1 // Ri 2 ) = ( 6.7 M Ω // 4 M Ω )
Dominant pole is at
1
fP = = 4.1 Hz
2π Cin Rt
Unity gain-bandwith is

f t = A0 f3dB = 243,147 × 4.1  1 MHz

Jose E. Schutt‐Aine ‐ ECE 442 51
 Conclusion - Design of Op Amps
1. Designer starts with building blocks whose
performance can be analyzed to a first order
approximation by hand

2. This step provides insight to the designer as

the design of the circuit develops

3. At some point designer must turn to computer

analysis programs such as SPICE. This will
provide speed and accuracy to the design
process

Jose E. Schutt‐Aine ‐ ECE 442 52