ECE 442 Differential Amplifiers

ECE
442
Solid‐State Devices & Circuits
13. Differential Amplifiers
Jose E. Schutt-Aine
Electrical & Computer Engineering
University of Illinois
jschutt@emlab.uiuc.edu
Jose E. Schutt‐Aine ‐ ECE 442 1
Background
• Differential Amplifiers
– The input stage of every op amp is a differential
amplifier
– Immunity to temperature effects
– Ability to amplify dc signals
– Well-suited for IC fabrication because
– (a) they depend on matching of elements
– (b) they use more components
– Less sensitive to noise and interference
– Enable to bias amplifier and connect to other
stage without the use of coupling capacitors
Differential Amplifiers
• Practical Considerations
– Both inputs to a differential amplifier may have
different voltages applied to them
– In the ideal situation with perfectly symmetric
stages, the common-mode input would lead to
zero output
– Temperature drifts in each stage are often
common-mode signals
– Power supply noise is a common-mode signal
and has little effect on the output signal
MOS Differential Pair
Assume current source is ideal

vID=vgs1-vgs2
Output is collected as vD2-vD1
MOS Differential Pair
- If vID is positive, vD2-vD1 is

positive
vID>0 Î vgs1>vgs2 ÎID1 > ID2
vD1 lower voltage point than vD2
For proper operation,

MOSFETS should not
enter triode region
DC Analysis
IRD IRD
VD1 = VDD − VD 2 = VDD −
2 2
I
µCoxW ID =
ID = (VGS − VT )
2
2
2L
LI ⎡ LI ⎤
VGS = VT + VSQ = − ⎢VT + ⎥
µCoxW ⎣ µCoxW ⎦
Incremental Analysis
1 1
vg1 = vcm + vid vg 2 = vcm − vid
2 2
Neglecting the body effect
vin vin
vo1 = − g m R
'
D vo 2 = g m R
'
D
2 2
vo 2 − vo1
R = RD & rout
'
D AD = = g m RD'
vin
Frequency Response
When driven by a low-impedance signal source, the

upper corner frequency is determined by the output
circuit
1
f high =
2π Cout RD'
Common-Mode Rejection Ratio
vo1 vo 2 RD
= =
vicm vicm 1
+ 2 RSS
gm
Assume RSS >> 1/gm
(a) For single-ended output:
vo1 vo 2 RD
=
vicm vicm 2 RSS
RD 1
Acm = , Ad = g m RD
2 RSS 2
Ad
CMRR = = g m RSS
Acm
(b) For differential output:
vo 2 − vo1
Acm = =0
vicm
vo 2 − vo1
Ad = = g m RD
vid
CMRR = ∞
BJT Differential Pair
Assume perfect match

between the devices and
symmetry in the circuit
BJT Differential Pair
Rin = 2rπ vin R = rout1 & Rc1 = rout 2 & Rc 2
'
iin = C
2rπ Rc1 = Rc 2 = RC
vin −vin
Base currents: ib1 = ib 2 =
2rπ 2rπ
BJT Differential Pair – Incremental Model
'
v r g R
vo1 = − g m vπ 1RC' = − g m RC' in π = − m C vin
rπ 2
'
v r g R
vo 2 = g m vπ 2 RC' = g m RC' in π = m C vin
rπ 2
Single-ended gain of first stage: AS 1 = − g m RC
'
Double-ended differential gain (with vout=vo2-vo1):
AD =
gm R '
C
−
( −g mR
'
C )=g R =
' βR '
C
m C
2 2 rπ
BJT Differential Pair – General
RB1 = RB 2 = RB
RC1 = RC 2 = RC
Rin = 2 RB + 2 RE ( β + 1) + 2rπ
β RC'
AD =
RE ( β + 1) + rπ + RB
Differential Amplifiers - Observations
• Observations
– The differential pair attenuates the input signal of
each stage by a factor of one-half cutting the gain
of each stage by one-half
– The double-ended output causes the two single-
ended gains to be additive
– Thus, the voltage gain of a perfectly matched
differential stage is equal to that of a single stage
Remarks on Differential Amplifiers
1. In many applications, the differential amplifier is not

fed in a complementary fashion
2. Rather, the input signal may be applied to one of
the input terminals while the other terminal is
grounded
3. In this case, the signal voltage at the emitters will
not be zero and thus the resistor REE will have an
effect on the operation
4. However, if REE is large (REE >> re) as is usually the
case, vid will still divide equally between the 2
junctions
5. The operation of the differential amplifier will still be
almost identical to that of the symmetrical feed and
the CE equivalence can still be employed
Common Mode
RC 2 = RC + ∆RC
RC1 = RC
Can show that
α RC
vc1 = −vicm
2 REE + re
α ( RC + ∆RC )
vc 2 = −vicm
2 REE + re
BJT Diff Pair - Common Mode
α∆RC
vo = vc1 − vc 2 = vicm
2 REE + re
α∆RC α∆RC
Acm =
2 REE + re 2 REE
α RC ∆RC
Acm = ⋅
2 REE RC
Example - I
β=100
Collector resistance
accurate within 1%
Early voltage = 100V
Example – I (cont’)
Emitter current in both transistors is: 0.5 mA
VT 25 mV
re = = = 50 Ω
I E 0.5 mA
Rid = 2 ( β + 1) ( re + RE ) = 2 × 101× ( 50 + 150 ) 40 k Ω
vid Rid 40
= = = 0.8
vsig Rsig + Rid 5 + 5 + 40
vo Total resistance in the collectors

=
vid Total resistance in the emitters
Example - I (cont’)
vo 2 RC 2 × 10
= = = 50
vid 2 ( re + RE ) 2 ( 50 + 150 ) × 10 −3
Overall differential gain:

vo vid vo
Ad = = ⋅ = 0.8 × 50 = 40
vsig vsig vid
RC ∆RC Where ∆RC is the worst

Acm = case variation in
N 2 REE RC
common-mode
gain
collector resistance
10
Acm = × 0.02 = 5 × 10−4
2 × 200
Common-Mode Rejection ratio CMRR
Ad
CMRR = 20 log
Acm
40
CMRR = 20 log −4
= 98 dB
5 × 10
Input common-mode resistance: Ricm
VA 100
ro = = = 200 k Ω
I / 2 0.5
⎛ ro ⎞
Ricm = ( β + 1) ⎜ REE & ⎟ = 101( 200 k Ω & 100k Ω ) = 6.7 M Ω
⎝ 2⎠
Example - II
In the circuit shown, the dc bias current is 4 mA. If α =

0.993, RB1 = RB2 = RB3 = 1,000 Ω, RE = 30 Ω, RC = 1.6
kΩ, VCC = 10 V, and VBE(on) = 0.7 V,
(a) Calculate the dc collector currents
(b) Calculate the dc or quiescent collector voltages
(c) Calculate the maximum peak value of vout before
serious distortion results
(d) Calculate the incremental differential voltage gain of
the circuit
(e) If the base resistor of Q2 is changed to RB2= 400 Ω,
calculate the dc collector current through each device
Example - II
Example - II
(a) Assuming perfect match between Q1 and
Q2, DC bias current will split equally IE1 = IE2
= 2mA. IC=αIE=1.986 mA
(b) The quiescent collector voltages will equal

VCC − I C RC = 10 − 1.986 × 1.6 = 6.82 V
(c) Maximum collector voltage is 10 V (at cutoff)

minimum is 0 V (at saturation).Therefore,
positive peak voltage is 10-6.82 = 3.18 V, and
negative peak is 6.82 V Îp-p voltage = 6.36 V
Example - II
(d) The incremental differential voltage gain
of the circuit is defined as:
vout vo 2 − vo1
AD = =
Calculate re and β vin vin
26 26
re = = = 13 Ω
IE 2
α 0.993
β= = = 142
1 − α 0.007
Example - II
Applying the gain equation and assuming rout
>> 1.6 kΩ gives
142 × 1600
AD = = 31.8 V / V
143 × (13 + 30 ) + 1000
(e) The voltage at the node above the dc

current source can be found from
V1 = − ⎡⎣ I B1RB1 + VBE ( on ) + ( β + 1) I B1RE ⎤⎦
V2 = − ⎡⎣ I B 2 RB 2 + VBE ( on ) + ( β + 1) I B 2 RE ⎤⎦
Example - II
Effects of non-balance
Example - II
( β + 1) I B1 + ( β + 1) I B 2 = 4 mA
I B1 = 13.1 µ A I B 2 = 14.8 µ A
The corresponding emitter and collector currents are
I E1 = 1.88 mA I E 2 = 2.12 mA
I C1 = 1.86 mA I C 2 = 2.10 mA
The two quiescent collector voltages are no longer
equal, resulting in a nonzero quiescent output voltage
VCQ 2 = 10 − 1.6 × 2.1 = 6.64 V
VCQ1 = 10 − 1.6 × 1.86 = 7.02 V
Example - II
VoutQ = VCQ 2 − VCQ1 = 6.64 − 7.02 = −0.38 V
Nonzero quiescent voltage Îserious consequences

when this stage is followed by additional gain stages,
creating an output offset voltage when the inputs are
shorted together
Nonideal Characteristics
Input offset voltage of
MOS differential pair
Mismatch can result in a

dc output voltage Vo
(output dc offset voltage)
Vos=Vo/Ad is input offset

voltage
Nonideal Characteristics
If Vos is applied (differentially) at the input, a zero
voltage difference should result at the output
• Factors contributing to dc offset voltage

1. Mismatch in load resistance
2. Mismatch in W/L
3. Mismatch in VT
⎛ Vov ∆RD ⎞ ⎛ Vov ∆ (W / L ) ⎞

2 2
Vos = ⎜ ⋅ ⎟ +⎜ ⋅ ⎟ + ( ∆VT )
2
⎝ 2 2 ⎠ ⎝ 2 W /L ⎠
Input Offset Voltage for BJT Diff Pair
• Offset results from

1. Mismatch in RC’s
2. Mismatch in β
3. Mismatch in junction area
2 2
⎛ ∆RC ⎞ ⎛ ∆I S ⎞
Vos = VT ⎜ ⎟ +⎜ ⎟
⎝ RC ⎠ ⎝ I S ⎠
Offset Current for BJT Diff Amp
In a perfectly symmetric differential pair, the 2 input
terminals carry equal dc current to support bias
I /2
I B1 = I B 2 =
β +1
Mismatches (primarily from β) make the 2 input
dc currents unequal
I os = I B1 − I B 2
⎛ ∆β ⎞
I os = I B ⎜ ⎟
⎝ β ⎠
Differential-to-Single-Ended Conversion
- Beyond first
stage, signal can
be converted
from differential
to single-ended
- Simply ignore the

drain current in
Q1 and eliminate
its drain resistor
Differential-to-Single-Ended Conversion
• Limitations
– Factor of 2 (6 dB) is lost in the gain if drain
current of Q1 is not used
– Much better approach consists of using drain

current of Q1
– Active load approach allows to perform

conversion without loss of gain by making use of
drain current in Q1
MOS Differential Amp with Active Load
Replacing drain
resistances with current
sources, results in
much higher voltage
gain and savings in chip
area in diff amp
Current mirror action makes it possible to convert
the signal to single-ended form without loss of gain.
The differential gain is:

vo
Ad ≡ = g m ( ro 2 & ro 4 )
vid
If ro 2 = ro 4 = ro
1
Ad = g m ro
2
The active-loaded MOS differential amplifier has a
low common-mode gain Î high CMRR
The common-mode gain is:
vo 1 ro 4
Acm ≡ =− RSS is internal
vicm 2 RSS 1 + g m 3ro 3 impedance
of current source
Usually, g m 3ro 3 1 and ro 3 = ro 4
1
Acm = −
2 g m 3 RSS
Since RSS is large, Acm will be small
Ad
CMRR ≡ = ⎡⎣ g m ( ro 2 & ro 4 ) ⎤⎦ [ 2 g m 3 RSS ]
Acm
If ro 2 = ro 4 = ro and g m 3 = g m
CMRR = ( g m ro )( g m RSS )
BJT Differential Amp with Active Load
Current mirror & active

load
Differential stage
Active Loaded BJT Pair – Incremental Model
Virtual ground develops at common-emitter terminal
Output resistance is parallel equivalent of the output
resistance of the differential pair and the output
resistance of the current mirror
The differential gain is:

vo
Ad ≡ = g m ( ro 2 & ro 4 )
vid
If ro 2 = ro 4 = ro The differential input
impedance is:
1
Ad = g m ro Rid = 2rπ
2
The active-loaded BJT differential amplifier has a low
common-mode gain Î high CMRR
The common-mode gain is:
vo ro 4
Acm ≡ − REE is internal
vicm β 3 REE impedance
of current source
It is assumed that , g m 3 = g m 4
and rπ 4 = rπ 3 and ro 3 rπ 3 , rπ 4
Ad ⎛ β 3 REE ⎞
CMRR ≡ = ⎡⎣ g m ( ro 2 & ro 4 ) ⎤⎦ ⎜ ⎟
Acm ⎝ ro 4 ⎠
If ro 2 = ro 4 = ro
1
CMRR = β 3 g m REE
2
For large CMRR, bias current source should
have large output resistance REE
Frequency Response of MOS Diff Amp
• Resistively Loaded
1. Resistance RSS is
between node S and
ground
2. Capacitance CSS is
between node S and
ground
3. CSS includes Cdb, Cgd,

and Csb
Frequency Response – Differential Half
Gain function of differential half

will be identical to that of
common-source amplifier
Frequency Response – Common-Mode
Zero associated with CSS will

dominate the circuit response
Common-mode gain is found

by analyzing the effect of a
mismatch ∆RD in RD
Frequency Response – Common-Mode
RD ⎛ ∆RD ⎞
Acm ( s ) = − ⎜ ⎟ (1 + sCSS RSS )
2 RSS ⎝ RD ⎠
Acm picks up a zero on the negative real axis of

the complex s-plane. The frequency is ωZ
1
ωZ =
CSS RSS
1
fZ =
2π CSS RSS
Frequency Response – Common-Mode Gain
Frequency Response – Differential Gain
Frequency Response – CMRR
Frequency Response – Actively Loaded MOS
Cm = C gd 1 + Cdb1 + Cdb 3 + C gs 3 + C gs 4
CL = C gd 2 + Cdb 2 + C gd 4 + Cdb 4 + Cload
Frequency Response – Actively Loaded MOS
⎛ Cm ⎞
⎜ 1+ s ⎟
vo ⎛ 1 ⎞ 2 g m3
Ad ( s ) ≡ = ( g m Ro ) ⎜ ⎟⎜ ⎟
vid ⎝ 1 + sCL Ro ⎠ ⎜ 1 + s Cm ⎟
⎜ ⎟
⎝ g m3 ⎠
1
First pole: f P1 =
2π CL Ro
g m3 g m3
Second pole: f P 2 =
2π Cm 2π ( 2C gs 3 )
2 g m3
Zero at: fZ =
2π Cm
Actively Loaded MOS - Transconductance
Darlington Configuration
- Popular BJT combination

- Composite transistor with
β=β1β2
- Can be used as the
cascade of two CC
Darlington Voltage Follower
Rin = ( β + 1) ⎡⎣ re1 + ( β 2 + 1) ( re 2 + RE ) ⎤⎦
⎡ re1 + Rsig / ( β1 + 1) ⎤
Rout = RE & ⎢ re 2 + ⎥
⎣ β2 + 1 ⎦
vout RE
=
vsig re1 + Rsig / ( β1 + 1)
RE + re 2 +
β2 + 1
CMOS OP Amp Example
In the differential amplifier shown, Q1 and Q2 form the differential
pair while the current source transistors Q4 and Q5 form the active
loads for Q1 and Q2 respectively. The dc bias circuit that establishes
an appropriate dc voltage at the drains of Q1 and Q2 is not shown.
The following specifications are desired: differential gain Ad =
80V/V, IREF = 100 µA, the dc voltage at the gates of Q6 and Q3 is
+1.5V; the dc voltage at the gates of Q7, Q4 and Q5 is –1.5V.
The technology available is specified as follows: µnCox=3µpCox =

90µA/V2; Vtn=|Vtp|=0.7V, VAn=|VAp| = 20V. Specify the required
value of R and the W/L ratios for all transistors. Also, specify ID
and VGS at which each transistor is operating. For dc bias
calculations, you may neglect channel-length modulation. Fill in
the entries in the table provided to show your results.
CMOS OP Amp Example
CMOS OP Amp Example
1.5 − (−1.5) 3V
I REF = 100 µ A = ⇒R= = 30k Ω
R 0.1mA
Drain currents are determined by symmetry and inspection
VGS values are also determined by inspection for all
transistors except Q1 and Q2. To determine VGS for Q1 and
Q2, we do the following: the equivalent load resistance will
consist of ro1 in parallel with ro4 for Q1 and ro2 in parallel
with ro5 for Q5. Since the ro’s are equal, this corresponds to
ro/2.
We have:
ro 2 Ad 2 × 80
g m = Ad ⇒ g m = = = 0.4mA / V
2 ro 400k Ω
CMOS OP Amp Example
2I D 2 I D 2 × 0.05
gm = ⇒ Vov = = = 0.25
Vov gm 0.4
Take polarity into account for PMOS
VGS 1,2 = −0.25 − VT = −0.95
To find W/L ratios, use

W W 2I D
I D = µ Cox (VGS − VT ) ⇒
2
=
2L L µ Cox (VGS − VT ) 2
taking into account PMOS and NMOS devices separately
CMOS OP-AMP DESIGN TABLE
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Units
µCox 30 30 30 90 90 30 90 µA/V2
ID 50 50 100 50 50 100 100 µA
VGS -.95 -.95 -1 +1 +1 -1 +1 V
W/L 57.3 57.3 74 1. 12.3 12.3 73.1 24.7
2-Stage CMOS Op Amp
2-Stage CMOS Op Amp
Two-stage configuration with two power supplies
which can range from +/- 2.5 V for 0.5 µm
technology to +/- 0.9 V for 0.18 µm technology. IREF
is generated either externally or using on-chip
CKT.
Current mirror formed by Q5-Q8 supplies differential

pair Q1-Q2 with bias current. The W/L of Q5 is
selected to control I. The diff pair is actively loaded
by current mirror Q3-Q4
2-Stage CMOS Op Amp
Second stage is Q6 which is a CS amplifier for
which Q7 is the current source. A capacitor Cc is
included for negative feedback to enhance the
Miller effect through Q6 Î compensation
This op amp does not have a low output

impedance and is thus not suited for driving a low-
impedance load
Let I REF = 90 µ A, Vtn = 0.7 V , Vtp = −0.8 V
µ nCox = 160 µ A / V 2 , µ p Cox = 40 µ A / V 2

2-Stage CMOS Op Amp
| VA | for all devices = 10 V , VDD = VSS = 2.5 V
• Voltage Gain
First stage: A1 = − g m1 ( ro 2 & ro 4 )
Since Q8 and Q5 are matched, I = IREF, Q1, Q2,

Q3 and Q4 will have I/2 = 45 µA.
IQ7=IREF = 90 µA = IQ6
Let VGS-VT = Vov (overdrive voltage)

2-Stage CMOS Op Amp
1
From I D = ( µ Cox )(W / L ) Vov
2
We find Vov for each transistor.
2I D
Transconductance is: g m =
Vov
VA
ro =
ID
2-Stage CMOS Op Amp – Voltage Gain
Gain for first stage: A1 = − g m1 ( ro 2 & ro 4 )
A1 = −0.3 ( 222 & 222 ) = −33.3 V / V
Gain for second stage: A2 = − g m 6 ( ro 6 & ro 7 )
A2 = −0.6 (111 & 111) = −33.3 V / V
Overall dc open loop gain is (-33.3)(-33.3) = 1109 V/V
20 log1109 = 61 dB
2-Stage Op Amp Design Table
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
20/0.8 20/0.8 5/0.8 5/0.8 40/0.8 10/0.8 40/0.8 40/0.8
W/L
ID(µA) 45 45 45 45 90 90 90 90
|Vov| (v) 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3
|VGS| (v) 1.1 1.1 1.0 1.0 1.1 1.0 1.1 1.1
gm(mA/V)
0.3 0.3 0.3 0.4 0.6 0.6 0.6 0.6
ro(kΩ) 222 222 222 222 111 111 111 111
2-Stage Op Amp – Frequency Response
Incremental Circuit
Gm1 = g m1 = g m 2
R1 = ro 2 & ro 4 , C1 = C gd 4 + Cdb 4 + C gd 2 + Cdb 2 + C gs 6
Gm 2 = g m 6
R2 = ro 6 & ro 7 , C2 = Cdb 6 + Cdb 7 + C gd 7 + CL
CL is the load capacitance (usually large) ⇒ C2 C1
Vo Gm1 ( Gm 2 − sCC ) R1 R2
=
Vid 1 + sA + s 2 B
A = C1 R1 + C2 R2 + CC ( Gm 2 R1 R2 + R1 + R2 )
B = ⎡⎣C1C2 + CC ( C1 + C2 ) ⎤⎦ R1 R2
Transmission zero at s = sZ with

Gm 2
ωZ =
CC
Two poles that are the root of the denominator
1
ω p1 ≅ ω p2 ≅
Gm 2
R1CC Gm 2 R2 C2

ECE 442 Differential Amplifiers

Uploaded by

Document Information

Original Description:

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

ECE 442 Differential Amplifiers

Uploaded by

Copyright:

Available Formats

ECE

Assume current source is ideal

- If vID is positive, vD2-vD1 is

For proper operation,

When driven by a low-impedance signal source, the

Assume RSS >> 1/gm

(b) For differential output:

Assume perfect match

Double-ended differential gain (with vout=vo2-vo1):

1. In many applications, the differential amplifier is not

Can show that

vo Total resistance in the collectors

Overall differential gain:

RC ∆RC Where ∆RC is the worst

Common-Mode Rejection ratio CMRR

In the circuit shown, the dc bias current is 4 mA. If α =

(b) The quiescent collector voltages will equal

(c) Maximum collector voltage is 10 V (at cutoff)

(e) The voltage at the node above the dc

V1 = − ⎡⎣ I B1RB1 + VBE ( on ) + ( β + 1) I B1RE ⎤⎦

VoutQ = VCQ 2 − VCQ1 = 6.64 − 7.02 = −0.38 V

Nonzero quiescent voltage Îserious consequences

Mismatch can result in a

Vos=Vo/Ad is input offset

• Factors contributing to dc offset voltage

⎛ Vov ∆RD ⎞ ⎛ Vov ∆ (W / L ) ⎞

• Offset results from

- Simply ignore the

– Much better approach consists of using drain

– Active load approach allows to perform

The differential gain is:

Since RSS is large, Acm will be small

Current mirror & active

Virtual ground develops at common-emitter terminal

The differential gain is:

3. CSS includes Cdb, Cgd,

Gain function of differential half

Zero associated with CSS will

Common-mode gain is found

Acm picks up a zero on the negative real axis of

- Popular BJT combination

The technology available is specified as follows: µnCox=3µpCox =

VGS 1,2 = −0.25 − VT = −0.95

To find W/L ratios, use

taking into account PMOS and NMOS devices separately

ID 50 50 100 50 50 100 100 µA

VGS -.95 -.95 -1 +1 +1 -1 +1 V

W/L 57.3 57.3 74 1. 12.3 12.3 73.1 24.7

Current mirror formed by Q5-Q8 supplies differential

This op amp does not have a low output

µ nCox = 160 µ A / V 2 , µ p Cox = 40 µ A / V 2

First stage: A1 = − g m1 ( ro 2 & ro 4 )

Since Q8 and Q5 are matched, I = IREF, Q1, Q2,

Let VGS-VT = Vov (overdrive voltage)

We find Vov for each transistor.

A1 = −0.3 ( 222 & 222 ) = −33.3 V / V

Gain for second stage: A2 = − g m 6 ( ro 6 & ro 7 )

A2 = −0.6 (111 & 111) = −33.3 V / V

Overall dc open loop gain is (-33.3)(-33.3) = 1109 V/V

R2 = ro 6 & ro 7 , C2 = Cdb 6 + Cdb 7 + C gd 7 + CL

CL is the load capacitance (usually large) ⇒ C2  C1

Transmission zero at s = sZ with

You might also like

CL is the load capacitance (usually large) ⇒ C2 C1