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    Cs Naga Niranjan Reddy
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    This document provides details about a major project to implement a 16-bit Vedic multiplier using an FPGA. The project is being undertaken by 4 students for their 7th semester Electronics and Communication Engineering course at G.PULLA REDDY ENGINEERING COLLEGE in Kurnool, India. It aims to use the ancient Vedic mathematics technique of UrdhvaTiryakbhyam Sutra to perform multiplication faster and with lower power consumption compared to conventional methods. The students will use Xilinx Vivado and Cadence Incisive software on a Zynq 7000 FPGA board to demonstrate the 16-bit Vedic multiplier.

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    This document provides details about a major project to implement a 16-bit Vedic multiplier using an FPGA. The project is being undertaken by 4 students for their 7th semester Electronics and Communication Engineering course at G.PULLA REDDY ENGINEERING COLLEGE in Kurnool, India. It aims to use the ancient Vedic mathematics technique of UrdhvaTiryakbhyam Sutra to perform multiplication faster and with lower power consumption compared to conventional methods. The students will use Xilinx Vivado and Cadence Incisive software on a Zynq 7000 FPGA board to demonstrate the 16-bit Vedic multiplier.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    11 views3 pages

    Abstract NIR

    Uploaded by

    Cs Naga Niranjan Reddy
    This document provides details about a major project to implement a 16-bit Vedic multiplier using an FPGA. The project is being undertaken by 4 students for their 7th semester Electronics and Communication Engineering course at G.PULLA REDDY ENGINEERING COLLEGE in Kurnool, India. It aims to use the ancient Vedic mathematics technique of UrdhvaTiryakbhyam Sutra to perform multiplication faster and with lower power consumption compared to conventional methods. The students will use Xilinx Vivado and Cadence Incisive software on a Zynq 7000 FPGA board to demonstrate the 16-bit Vedic multiplier.

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    of 3

    G.

    PULLA REDDY ENGINEERING COLLEGE (Autonomous),Kurnool


    Affiliated to JNTUA, Ananthapuramu

    DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

    BATCH NO: 11 SEMESTER: VII SECTION: A

    MAJOR PROJECT TITLE:


    FPGA IMPLEMENTATION OF 16-BIT VEDIC MULTIPLIER.

    Name: Roll No:

    Naga Niranjan ReddyChinnaSalipela 209X1A0438

    Kammari Manohar Achari 209X1A0458

    YeddulaAkankska 209X1A0456

    Mulla Manzoor Ahmed 199X1A04B2

    PROJECT GUIDE: HEAD OF THE DEPARTMENT:

    Dr.S.Vyshali,M.Tech,Ph.D. Dr.S.Nagaraja Rao,M.Tech,Ph.D


    Associate Professor, Professor and Head of the Department,
    Department of ECE, Department of ECE,
    GPREC, Kurnool. GPREC, Kurnool.
    ABSTRACT
    We know that time plays a key role in our life and also in technology. An inch of nanoseconds
    matters a lot in many applications. So, we need quick responsive integral parts to enhance the
    devices in time domain. Any Device in VLSI or Digital Signal Processing (DSP) it should have
    low delay and low power consumption, then we can say that technology has improved.

    Our project is on “16-bit Vedic Multiplier”. The term “Vedic


    Mathematics” represents a collection of Methods or Sutras to solve numerical computations
    quick and fast. The technique we are going to use in this project is “UrdhvaTiryakbhyam
    Sutra”. The sutras collectively were later named as Vedic Maths. These sutras were derived
    from “The Ganit Sutras” also known as ‘Sulabh Sutras’ or the simple system of mathematics.
    The term “Sutra” is meant for “formula”. Using this we are going to do a 16-bit Vedic
    Multiplier. Using this method, we can make multiplication faster than the normal convention
    method and also, we can reduce propagation delay & power consumption. We make use of
    FPGA board, to give our presentation on Vedic multiplier. Multiplier can be used in various
    domains like Highspeed Arithmetic operations, MAC unit, Image Processing, Digital Signal
    Processing (DSP)…e.tc. We should make use of our Indian Ancient knowledge to make
    technology for better tomorrow.

    Software :
     Xilinx Vivado 2018.3 Windows/ Cadence Incisive (NCsim) 13.10 Red Hat.

    Hardware :
     FPGA Zynq 7000 Board.
    BLOCK DIAGRAM:

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