Q. No. cs - 820 / O66 B. Tech/Even 2016-17/Reg 2016-17 VLSI TESTING AND VERIFICATION CS - 820 Full Marks : 70 Time : Three Hours The figures in the margin indicate full marks. Answer any five questions. Answers to all parts of a question should strictly be grouped together under the properly mentioned question no. 1. (a) What is event driven logic simulation? Illustrate event driven logic simulation on the following circuit assuming the gate delays for AND gate as 3 and OR gate as 2 and an input event for the input B 1>0. B D e 6 A (b) Explain how a Linear Feedback Shift Register is used for pseudo-random pattern generation. What is the primitive polynomial of an LFSR? Te. 2. (a) Describe the D-algorithm for test generation in combinational circuits. P.T.O. ¥/14/62- 100(2°) (b) Generate a test with the PODEM ATPG algorithm for the fault g s-a-1 in the following circuit. Explicitly show each step of execution. Gaal 3. (a) Define Transition faults in memory devices. Explain what would happen if there were a transition fault on the CS signal of a DRAM? (b) What is state coupling fault? Define the necessary condition(s) for detecting state coupling fault. Does the following MARCH C-test catches state coupling faults? Justify your claim with proper explanation. {M0:2(w0); M1:T}(r0, wl); M2:f1(r1, w0); M3:\)(r0, wl); M4:(r1, w0); M5:0(70)} TT 4. (a) What is the role of testing in VLSI? What do you mean by at-speed testing? (3) (b) Determine the total number of stuck-at (single and multiple) faults for the logic circuit of a 2-input XOR gate implemented with NAND gates only. (c) Show that in the following circuit, faults c s-a-0 and f s-a-1 are equivalent. 4+4+6 5. For the circuit shown below : (a) What is the number of all potential fault sites? (b) Derive the equivalence collapsed set. Obtain the collapse ratio. (c) Derive the dominance collapsed set. What is the corresponding collapse ratio? P.T.O. Y/14/62- 100G4) (d) What is fault masking? Explain with an example. 14+5+5+3 6. (a) Define stuck open and stuck short type of faults. (b) State Check Point Theorem. For the circuit described below enumerate the minimal set of single stuck-at faults that must be tested according to the Checkpoint Theorem. a,b d and e nand b,c He nand g or h and (c) What is the importance of testability analysis? Compute the combinational SCOAP testability measure for the circuit in (b). 2+4+8 7. Write short notes on the following (any two) : 7x2=14 (a) Single stuck fault model (b) Coupling faults in Memory Devices (c) Compiled code simulation (d) Verification Test process for VLSI chips.