IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO.
4, JULY 1998
Conduction Power Loss in MOSFET
Synchronous Rectifier with
Parallel-Connected Schottky Barrier Diode
Nobuhiko Yamashita, Member, IEEE, Naoki Murakami, Member, IEEE, and Toshiaki Yachi, Member, IEEE
Abstract— The conduction power loss in an MOSFET syn-
chronous rectifier with a parallel-connected Schottky barrier
diode (SBD) was investigated. It was found that the parasitic
inductance between the MOSFET and SBD has a large effect on
the conduction power loss. This parasitic inductance creates a
current that is shared by the two devices for a certain period and
increases the conduction power loss. If conventional devices are
used for under 1-MHz switching, the advantage of the low on-
resistance MOSFET will almost be lost. To reduce the conduction
loss for 10-MHz switching, the parasitic inductance must be a
subnanohenley.
Index Terms—Conduction power loss, dc–dc converter, MOS-
FET, Schottky barrier diode, synchronous rectifier.
I. INTRODUCTION
T HE POWER loss in dc–dc converters for telecommunica-
tion equipment must be as small as possible to minimize
power use and device size. The conduction power loss in a
rectifier circuit is a large part of the converter power loss.
Synchronous rectification using MOSFET’s has significant
advantages in reducing this loss, so a variety of circuits and
analyses were studied [1]–[11], and MOSFET’s suitable for
synchronous rectification were presented [12]–[16].
MOSFET’s must be driven to achieve a rectifying action,
but it is difficult to achieve good drive timing with a driver, and
it needs many driver parts. Using transformer secondary volt-
age for driving MOSFET’s, on the other hand, is simple and
effective [2], [6], [11]. In a converter with forward topology,
the forward action can drive a rectifying MOSFET while the
reset action can drive a freewheeling MOSFET. Focusing on
the transition period between actions, that is, during current
exchange between a rectifying and a freewheeling device,
both devices conduct, so the MOSFET’s are in the off state
because they cannot be driven, and the current flows through
the body diodes of the MOSFET’s. Furthermore, when there
is excess output current, the on-duty cycle of the main switch
is reduced, and once again the MOSFET’s cannot be driven.
Driving an MOSFET with perfect timing is impossible even
if an exclusive driver is used. Current flow through the body
Manuscript received February 19, 1996; revised December 4, 1997. Rec-
ommended by Associate Editor, W. Portnoy.
The authors are with NTT Integrated Information and Energy Systems
Laboratories, Nippon Telegraph and Telephone Corporation, Tokyo 180,
Japan.
Publisher Item Identifier S 0885-8993(98)04850-9.
0885–8993/98$10.00  1998 IEEE
667
diode has the disadvantages of a large forward voltage drop
and reverse recovery time because the body diode is a p-n
junction diode. To prevent current flow through the body diode
during these conditions, a parallel-connected Schottky barrier
diode (SBD) is used to rectify the current during the MOSFET
off-state period [4], [6].
An MOSFET rectifier with an SBD, however, has a larger
power loss than that expected with only MOSFET on-
resistance dissipation. This is caused by parasitic inductance
between the MOSFET and the SBD, which is about 10 nH
for a conventional package of devices. While this may seem
small enough to neglect, the applied voltage, i.e., the voltage
difference between the MOSFET and SBD, is also small, so
the current changes slowly. This means that shared current
will flow between the MOSFET and SBD for a rather long
time as long as several hundred nanoseconds. As a result,
the advantage of a lower conduction loss with an MOSFET
synchronous rectifier is lost when the switching frequency
reaches the megahertz level.
Studies of an analysis when the SBD is not connected [5],
[11] and an analysis of the condition when the current flows
though the parallel-connected SBD only during the MOSFET
off state [4] have been reported although there is no analysis
of current sharing during the MOSFET on state.
In this paper, we will describe the effect of parasitic
inductance between an MOSFET and parallel-connected SBD
in a synchronous rectifier circuit for the first time. We will
show both analytically and experimentally that the inductance
creates current sharing between the MOSFET and SBD. We
will also show that the conduction power loss is higher at
higher switching frequencies because of the SBD current.
II. MOSFET SYNCHRONOUS RECTIFIER
The circuit scheme for a single-ended forward dc–dc con-
verter is shown in Fig. 1 [6]. This converter has one switch
(main switch), and output voltage is controlled by the on-
state duty of the main switch. Hard switching was selected to
simplify the circuit. This converter uses a rectifying MOSFET
and a freewheeling MOSFET as synchronous rectifiers. An
SBD is connected to the freewheeling MOSFET—it is parallel
to the freewheeling current flow during the MOSFET off
state. A transformer secondary voltage waveform was used
to drive the MOSFET because this avoids use of a driver
circuit which must be controlled. The forward action can fully
668 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO. 4, JULY 1998

(a)

Fig. 1. A dc–dc converter using synchronous rectifier circuit.

(b)
drive the rectifying MOSFET, but the reset action that drives
the freewheeling MOSFET may finish while the freewheeling Fig. 2. (a) Current waveforms and (b) equivalent circuits of freewheeling
MOSFET and SBD.
current is flowing. Thus, the parallel-connected SBD allows
the freewheeling MOSFET current to flow even while the
MOSFET is not being driven.
The current waveforms of the rectifier circuit are also shown
in Fig. 1. Output current flows alternately through the
rectifying MOSFET and the freewheeling MOSFET, which
are switched by a main switch. In the following analysis,
we consider rectifying current and freewheeling current
to be constant values of during current flow. The
MOSFET and SBD currents are and , respectively.
Freewheeling current includes and .

III. EFFECT OF PARASITIC INDUCTANCE

Current waveforms of the freewheeling device and equiv-
alent circuits are shown in Fig. 2. The parasitic inductance
on the MOSFET side is and that on the SBD side is
. The freewheeling current first flows through the SBD.
The MOSFET should be off at the current start time to avoid
creating a short circuit between the freewheeling and rectifying
MOSFET’s. The current flows through the SBD once, but
cannot exchange immediately from the SBD to the MOSFET
after MOSFET turn on because of a parasitic inductance
between the MOSFET and SBD. A larger parasitic inductance
causes a longer exchange time. The current exchange action
may not be completed during the MOSFET on-state period if
the inductance is too large.
The current exchange period is shown in Fig. 2 as Period I.
During Period II, the current flows only through the MOSFET.
If we can drive MOSFET’s with ideal timing, no current flows
through the SBD, but this is impossible. The MOSFET turn-
on timing should be later rather than earlier to avoid any short
circuits between MOSFET rectifiers.
There is a parasitic inductance of about 10 nH in con-
ventional packages of MOSFET’s and SBD’s. Because this
inductance is significantly smaller then other circuit inductive
elements (e.g., the magnetic inductance of transformers and
choke inductors), it has been neglected when considering
Fig. 3. Experimental circuit.
conduction power loss, although parasitic resonant action has
not. The applied voltage of the parasitic inductance, which
is the difference between the MOSFET and SBD voltages,
is also very small. For example, it is 0.4 V for a 0.4-V
SBD and a 0-V MOSFET, whose current is initially zero. It
will take hundreds of nanoseconds to exchange a current of
10 A for a 10-nH applied voltage of 0.4 V. Recent dc–dc
converters use switching frequencies from several hundred
kilohertz to 1 MHz, so this current exchange time can no
longer be neglected.
During the current exchanging period, the shared current
flowing through the SBD dissipates more conduction power
than the current flowing through only the MOSFET, thus,
the advantage of the MOSFET synchronous rectifier in low
conduction power loss is lost.
IV. ANALYSIS
A. Modeling and Analysis
1) Equivalent Circuit: Models of the MOSFET and SBD
are shown in Fig. 2. The freewheeling current flowing
YAMASHITA et al.: CONDUCTION POWER LOSS IN MOSFET RECTIFIER 669

(a) (b)

(c)

Fig. 4. Experimental current waveforms (switching frequency: 100 kHz). (a) Lp = 2 H (Lm = Ls = 1 H). (b) Lp = 6:6 H (Lm = Ls = 3:3 H).
p
(c) L = 20 H (L m s
= L = 10 H).

time is in a cycle, and during this period, it is considered 2) Current Exchange Time: The MOSFET and SBD cur-
to be a constant value of the output current . At the start rents and during Period I are
of , all current flows through the SBD as . After the
MOSFET is turned on, will exchange from the SBD to
(1)
the MOSFET for the time . Through this Period I, the
current is shared by the MOSFET and the SBD, and the (2)
equivalent circuit is shown in Fig. 2(b). After current exchange
has finished, Period II begins. The MOSFET is represented where is the sum of and .
as resistor and the SBD as voltage source . The When reaches , Period I finishes, and this time is
parasitic capacitances of the devices are neglected because the
variations in voltage between nodes of the devices are small
during the period when the freewheeling circuit conducts. A (3)
body diode of the MOSFET is also neglected because it does or
not conduct.
(3 )
The length of Period I depends on the parasitic inductance
—a small can be neglected, but a larger cannot. The
circuit will be analyzed using equivalent circuits for Periods I where is the MOSFET voltage when all current flows
and II, as shown in Fig. 2. through the MOSFET .
670 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO. 4, JULY 1998

The current exchange time is in proportion to the output

current and the parasitic inductance. Although a larger output
current from converters requires bigger devices (and therefore
larger parasitic inductance), the parasitic inductance itself must
be reduced to allow control of the current exchange time.
3) Conduction Power Loss: Next, we derive equations to
calculate the conduction power losses of the MOSFET and
SBD. Dissipated energy by conduction current on the MOS-
FET and SBD are and , respectively,

(4)

Fig. 5. Measured current exchange time.

(5)

Dissipated energy during period is the sum of these, i.e.,

(6)

From (1) and (4)–(6), is

Fig. 6. Measured conduction power loss.

(7)

Equation (7) shows energy per cycle, so the power loss of

Period I is energy magnified by the switching frequency

(8)

During period , the current flows only through the MOSFET,

so dissipated energy is

(9) Fig. 7. Calculated parasitic inductance dependence of current exchange

time.

The power loss of Period II is found similarly since

is replaced with

(10)

The total conduction power loss is classified into two cases.

1) :
Here, is represented by the sum of (8) and (10) (12)

(11) Then, is
(13)
2) :
Current exchange does not complete, so there is no These equations show that zero parasitic inductance makes
Period II. Dissipated energy is shown as in (7), only the power loss the same as the loss which only the MOSFET
YAMASHITA et al.: CONDUCTION POWER LOSS IN MOSFET RECTIFIER 671

(a) (b)

(c)
Fig. 8. Calculated parasitic inductance dependence of conduction power loss. (a) Io = 10 A and R on = 10 m
. (b) Io =1 A and R on = 100
m
. (c) Io = 0:1 A and Ron = 1
.

conducts. On the other hand, in the case of infinite inductance,
the power loss is equal to the loss which only the SBD
conducts.
B. Experiment
1) Experimental Circuit: The current-sharing model was
tested using an experimental circuit shown in Fig. 3. In the
experiment, the transformer is omitted to test only the rectifi-
cation circuit. The MOSFET and the SBD are used for
the rectifying action because the MOSFET can be driven easily
by the switch . The freewheeling action is done simply by
the SBD . The currents and are measured by current
probes. To measure the input current, a resistor is inserted
between a power source and the experimental circuit. The
output current is calculated from an output voltage and a load
resistance. The power loss is obtained from the input/output
current and voltage.
The experimental conditions must be selected carefully.
The resistance of rectifiers is very small for dc–dc converters
that handle output currents of several amperes, for example,
many MOSFET’s with on-state resistance in the 10-m class
have been introduced and used. Current probe impedance is
about 0.1 (depending on the frequency). This impedance
is significantly larger than the MOSFET on resistance. The
impedance of the current probe should be smaller than the on
resistance, so we used an MOSFET with larger on resistance
in the experiment. The parasitic inductance is also rather large
when an inductor is used, and a small rectifying current is
selected to control the MOSFET voltage drop. The MOSFET
on resistance is 1.86 , and the output current is set to 50 mA
(Fig. 3), so we can ignore the impedance of the current probe.
The experimental SBD forward voltage is 0.32 V.
2) Result:
a) Current sharing characteristics: The experimental
current waveforms are shown in Fig. 4. The current sharing
and switching are clear in the waveforms. In the experiment,
the switching time is not a large fraction of a cycle when the
switching frequency is 100 kHz, and the inductor is 2 H,
however, it becomes a significant part when the inductor is
20 H.
b) Current exchange time: The measured current ex-
change time is shown in Fig. 5 compared with the analyzed
time. Both times agree well, so the analysis is probably
appropriate.
c) Conduction power loss: Inductance dependence on
experimental power loss is described next. From measured
total power loss, the expected conduction power loss is
calculated by deducting the measured loss with no inductor
and adding a value that incorporated loss associated with
MOSFET on resistance. The calculated data ( ) and analysis
results (- - -) are shown in Fig. 6. For an inductor of up to
3.3 H, the measurement and analysis show good agreement.
However, the measured loss at 10 H does not match the
analysis. This is because the inductor of 10 H makes a
rather large parasitic oscillation [shown in Fig. 4(c)], which
672
is neglected to simplify analysis, but does affect the power
loss. Thus, although there is a little inaccuracy under some
conditions, the analysis gives an approximate estimation.
V. DISCUSSION
A. Parasitic Inductance Dependence
of Current Exchange Time
The calculated current exchange time using (3) shows the
parasitic inductance dependence of the current exchange time
(Fig. 7). Rectifying current has three levels (0.1, 1, and
10 A) as a parameter. In this calculation, the SBD forward
voltage drop is a constant 0.4 V, and the MOSFET
forward voltage drop is a constant 0.1 V. The constant
means that MOSFET on resistance will change
depending on the current . This shows that
with the exchange time of 10 ns, the parasitic inductance
is up to 50 nH for the output current of 0.1 A, but it is
below 1 nH for 10 A. Conventional MOSFET and SBD device
packages have a parasitic inductance of around 10 nH. This
10-nH inductance creates an exchange time of several hundred
nanoseconds for a 10-A rectifying current. This exchange time
has a remarkably large ratio, about half a cycle for a 1-MHz
switching frequency, where the cycle time is only 1 s.
B. Expected Problem of Conduction Loss
at Higher Switching Frequency
During the current exchange period, the conduction power
loss becomes larger than that of only the MOSFET conduction
condition because the shared current flows through the SBD,
which has a large voltage drop. The calculated conduction
power loss for the MOSFET and SBD is shown in Fig. 8. The
switching frequency is a parameter with five levels. The lower
dashed line in these graphs shows the ideal conduction loss,
which occurs when only the MOSFET conducts. The upper
dashed line shows the conduction loss when only the SBD
conducts. The parallel-connected MOSFET and SBD have a
conduction loss between these two levels. For a sufficiently
small parasitic inductance, the combined conduction loss must
be close to the loss for only the MOSFET. On the other
hand, for a rather large parasitic inductance, the conduction
loss must approach that of the SBD-only condition. As a
result, a larger parasitic inductance spoils the advantage of low
conduction loss in MOSFET synchronous rectification. For
example, a parasitic inductance of 10 nH creates a conduction
loss about twice as high under 1-MHz switching and 10-A
output current conditions. If the switching frequency is 10
MHz, the conduction loss is nearly the loss of the SBD-only
conduction. To lower the loss of MOSFET synchronous rectifi-
cation for 10-MHz switching, the parasitic inductance between
the MOSFET and SBD must be below the subnanohenley
range. However, inductance cannot be achieved at this low
level using conventional packaging and assembling techniques.
Even a multichip module will not work because the bonding
wire has inductance on the nanohenley order. To increase
switching frequency up to the 10-MHz range, an MOSFET
integrated with an SBD on one chip [13] should be used. This
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO. 4, JULY 1998
device still shows a parasitic inductance between the separated
MOSFET and SBD areas. So a complex device, such as a new
MOSFET cell structure with an SBD, is needed to achieve
higher switching frequencies of several ten megahertz.
VI. CONCLUSION
We have investigated the conduction power loss in an MOS-
FET synchronous rectifier with a parallel-connected SBD. The
parasitic inductance between the MOSFET and SBD has a
large effect on the conduction power loss, and this inductance
creates a current shared by the two devices for a certain period.
The SBD current increases the conduction power loss. If
conventional devices are used for under 1-MHz switching, the
advantage of the low on-resistance MOSFET will be almost
lost. To reduce the conduction loss for 10-MHz switching, the
parasitic inductance must be a subnanohenley.
REFERENCES
[1] R. S. Kagan, M. Chi, and C. Hu, “Improving power supply efficiency
with MOSFET synchronous rectifiers,” in Proc. POWERCON9, 1982,
p. D-4.
[2] S. Ikeda, Y. Usunaga, and H. Yoshida, “Power MOSFET for switch-
ing regulator,” in Proc. IEEE Int. Telecommunications Energy Conf.
(INTELEC), 1982, pp. 212–215.
[3] R. A. Blanchard and P. E. Thibodeau, “Use of depletion mode MOSFET
devices in synchronous rectification,” in Proc. IEEE Power Electronics
Specialists Conf. (PESC), 1986, pp. 81–86.
[4] W. A. Tabisz, F. C. Lee, and D. Y. Chen, “A MOSFET resonant
synchronous rectifier for high-frequency dc/dc converters,” in Proc.
IEEE Power Electronics Specialists Conf. (PESC), 1990, pp. 769–779.
[5] E. Sakai and K. Harada, “Switching loss analysis of MOSFET syn-
chronous rectifier,” in Proc. Chinese-Japanese Power Electronics Conf.
(CJPEC), Sept. 1992, pp. 109–114.
[6] N. Murakami, H. Namiki, K. Sakakibara, and T. Yachi, “A simple and
efficient synchronous rectifier for forward dc–dc converters,” in Proc.
IEEE Applied Power Electronics Conf. (APEC), 1993, pp. 463–468.
[7] I. D. Jitaru and G. Cocina, “High efficiency dc–dc converter,” in Proc.
IEEE Applied Power Electronics Conf. (APEC), 1994, pp. 638–644.
[8] J. A. Cobos, O. Garcı́a, J. Sebastián, and J. Uceda, “Resonant reset
forward topologies for low output voltage on board converters,” in Proc.
IEEE Applied Power Electronics Conf. (APEC), 1994, pp. 703–708.
[9] J. A. Cobos, O. Garcı́a, J. Uceda, J. Sebastián, and E. de la Cruz,
“Comparison of high efficiency low output voltage forward topologies,”
in Proc. IEEE Power Electronics Specialists Conf. (PESC), 1994, pp.
887–894.
[10] H. K. Ji and H. J. Kim, “Active clamp forward converter with MOSFET
synchronous rectification,” in Proc. IEEE Power Electronics Specialists
Conf. (PESC), 1994, pp. 895–901.
[11] M. M. Jovanovic, M. T. Zhang, and F. C. Lee, “Evaluation of
synchronous-rectification efficiency improvement limits in forward
converters,” IEEE Trans. Ind. Electron., vol. 42, no. 4, pp. 387–395,
1995.
[12] Y. Shimada, K. Kato, and T. Sakai, “High efficiency MOS-FET rectifier
device,” in Proc. IEEE Power Electronics Specialists Conf. (PESC),
1983, pp. 129–136.
[13] C. S. Korman, H. R. Chang, K. Shenai, and J. P. Walden, “High
performance power DMOSFET with integrated Schottky diode,” in
Proc. IEEE Power Electronics Specialists Conf. (PESC), 1989, pp.
176–179.
[14] R. Kollman, G. Sills, and J. Yuan, “A comparison of silicon UMOS-
FET’s versus GaAs vertical FET’s for low voltage, synchronous rectifi-
cation at 2.5 MHz,” in Proc. High Frequency Power Conversion Conf.
(HFPC), May 1992, pp. 112–123.
[15] C. Blake, D. Kinzer, and P. Wood, “Synchronous rectifiers versus
Schottky diodes,” in Proc. IEEE Applied Power Electronics Conf.
(APEC), 1994, pp. 17–23.
[16] Y. Fukumochi, I. Suga, and T. Ono, “Synchronous Rectifiers using new
structure MOSFET,” in Proc. Int. Symp. Power Semiconductor Devices
& IC’s (ISPSD), May 1995, pp. 252–255.
YAMASHITA et al.: CONDUCTION POWER LOSS IN MOSFET RECTIFIER 673

Nobuhiko Yamashita (M’92) was born in Saga,
Japan, on April 29, 1964. He received the B.S.
degree in electronics engineering from the Kyushu
Institute of Technology, Fukuoka, Japan, in 1987.
He joined Nippon Telegraph and Telephone Cor-
poration (NTT) Electrical Communications Lab-
oratories, Tokyo, Japan, in 1987, where he has
been researching high-speed power semiconductor
devices and circuits for dc–dc converters. He is
currently engaged in research on power supplies for
telecommunication systems.
Mr. Yamashita is a Member of the Japan Society of Applied Physics and
the Institute of Electronics, Information and Communication Engineers.
Toshiaki Yachi (M’83) was born in Ishikawa,
Japan, on August 26, 1950. He received the
B.S., M.S., and Dr.Eng. degrees in electronics
engineering from Shizuoka University, Shizuoka,
Japan, in 1973, 1975, and 1986, respectively.
He joined Nippon Telegraph and Telephone
Corporation (NTT) Electrical Communications
Laboratories, Tokyo, Japan, in 1975, where he has
been researching MOS device technology. He is
currently engaged in research on power electronics
technology.
Dr. Yachi is a Member of the Japan Society of Applied Physics, the Institute
of Electronics, Information and Communication Engineers, and the Institute
of Electrical Engineers of Japan.

Naoki Murakami (M’87) was born in Shimane,

Japan, on March 28, 1948. He received the B.S.
and M.S. degrees in electronics engineering from
Kyushu University, Fukuoka, Japan, in 1971 and
1973, respectively.
He joined Nippon Telegraph and Telephone Cor-
poration (NTT) Electrical Communications Labora-
tories, Tokyo, Japan, in 1973, where he has been
researching switching power supplies for switching
systems. He is currently engaged in research on
compact and highly efficient power supply modules.
Mr. Murakami is a Member of the Institute of Electronics, Information and
Communication Engineers and the Institute of Electrical Engineers of Japan.