onsider the gate-level circuit shown in Figure 2.1(a).

(a) Draw its “intersection graph” (see Figure 7 of

ACTICAL PROBLEMS IN VLSI PHYSICAL DESIGN AUTOMATION

More Practice Problems
1. Perform a single pass of Kernighan and Lin algorithm on the circuit in
Figure 2.1(a) using {aceg, bdf h} as the initial solution. Break ties in lexi-
cographical order.
2. Consider the gate-level circuit in Figure 2.16. Perform a single pass of
Kernighan and Lin algorithm using {acegi, bdf hj} as the initial solution.
Fix cells a and b in their initial partition, and do not move them.
3. Consider the clustered netlist shown in Table 1.9 and Table 1.10 based on
Modified Hyperedge Coarsening algorithm. The area constraint for biparti-
tioning is set to [2, 6].
(a) Perform a single pass of Fiduccia and Mattheyses algorithm on the
clustered netlist. The initial solution is ({C 1 , C 4 , C 5 }, {C 2 , C 3 }).
(b) Perform a single pass of Fiduccia and Mattheyses algorithm on the
original netlist using the best solution obtained in part (a) as the initial
solution.
4. Perform a single pass of Fiduccia and Mattheyses algorithm on the circuit
shown in Figure 2.5(a) using {bcde, af gh} as the initial solution. Break
ties in alphabetical order. The area constraint is set to [3, 5].
5. Perform EIG Algorithm on the circuit in Figure 2.5(a) and obtain biparti-
tioning solutions that minimize the following metrics:
(a) Ratio cut under area constraint [3, 5].
(b) Cutsize under area constraint [3, 5].
6. Consider the gate-level circuit shown in Figure 2.1(a).
(a) Draw its “intersection graph” (see Figure 7 of [Hagen and Kahng,
1992]). Use the following correct definition of A ab :
A ab
=
q

l=1
1
d l − 1

1
1
+
|s a | |s b |

(b) Obtain the second smallest eigenvalue and its eigenvector of the inter-
section graph.
(c) Perform the module assignment heuristic shown in Figure 8 of [Hagen
and Kahng, 1992] to obtain the best ratio-cut partition. What is the best
ratio-cut value and its partitioning solution?Partitioning
57
7. Perform FBB algorithm on the circuit in Figure 2.23 using (c, f ) as the
source/sink pair. The area constraint is set to [4, 5]. The node merging
should be done in alphabetical order.
8. Perform FBB algorithm on the circuit in Figure 2.5(a) using (a, h) as the
source/sink pair. The area constraint is set to [3, 5]. The node merging
should be done in alphabetical order
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