A 90 nm Active Inductor Feedback Transimpedance

Ampli er For Fiber Optics Applications

Muhammed Subhi Hameed Alsheikhjader  (  mohammedsubhi@uomosul.edu.iq )
University of Mosul

Research Article

Keywords: Transimpedance, TIA, Front-End Ampli er, Optical Preampli er

Posted Date: October 27th, 2022

DOI: https://doi.org/10.21203/rs.3.rs-2193638/v1

License:   This work is licensed under a Creative Commons Attribution 4.0 International License.  
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 A 90 nm Active Inductor Feedback Transimpedance Amplifier For
Fiber Optics Applications
Muhammed Subhi Hameed Alsheikhjader

Department of Physics ,College of Science, University of Mosul, Mosul-Iraq

Email: mohammedsubhi@uomosul.edu.iq
ORCID: https://orcid.org/0000-0002-5804-3164

Abstract. A simulated 90 nm active inductor feedback transimpedance amplifier is reported. A 1V configuration of

regulated cascode followed by a shunt-shunt feedback stage is considered with a local active inductor feedback
configuration. A transimpedance gain of 62.9 dBΩ is achieved with a bandwidth of 2.7 GHz, power consumption of
1.22 mW and an input referred noise current spectral density of 21 𝑝𝐴⁄√𝐻𝑧 . The key advantage of using local
active inductor feedback is to solve a major problem regarding integrated circuit design constraint in which it
replaces an ordinary spiral inductor and therefore, real advantages of less volume on board a chip, low power
consumption and input referred noise are obtained. Important transient analysis and Fourier transform analysis were
performed to examine active inductor feedback system response. There was no apparent inductive peaking associated
with transimpedance gain despite of the fact that the frequency response of active inductor impedance behavior was
to a greater extent similar to that of an ordinary spiral inductor.

Keywords: Transimpedance, TIA, Front-End Amplifier, Optical Preamplifier

1. Introduction

The call for high performance optical receiver front-ends for fiber optics applications have become highly crucial in
recent years. High data rates communications demand an efficient compromise that involves gain, bandwidth and
noise optimization with low power consumption and cost. In past history, following the stated purpose, many
techniques and fabrication technologies were employed. An inductorless modified regulated cascode [1], shunt-shunt
feedback [2–4] and active feedback transimpedance amplifier (TIA) [5][6] were introduced. As for active inductor
incorporation within various topologies, an active inductor peaking was realized [7], a current-reuse TIA [8], a TIA
using active inductor in shunt and series techniques [9] and a common source TIA with active inductive peaking
[10] .

In this work, real problem regarding a major integrated circuit design constraint is overcome. An active inductor
replaces an ordinary inductor and therefore avoiding an occupation of volume and area aboard the chip. At the same
time, the active inductor is embedded within a feedback system, hence, maintaining classical features such as
desensitization of considerable TIA gain, extension of bandwidth and noise reduction.

1.1 Conventional Regulated Cascode Structure

The common gate (CG) TIA is a widely used topology that has the feature of low input resistance governed by the
transconductance 𝑔𝑚 of MOSFET transistor as in Fig. 1a. The input resistance formula is represented as follows
[11]:

1
 𝑅𝑆
𝑅𝑖𝑛 = (1)
1 + 𝑅𝑆 𝑔𝑚1

The conventional regulated cascode (RGC) TIA may take different forms [12–15]. The most common one is to have
it combined with a CG main amplifier as well as a common source (CS) auxiliary amplifier as shown in Fig. 1b.
Bandwidth extension is possible given that the input resistance of RGC is smaller than that of the CG amplifier in
which the input resistance is defined as:

𝑅1
𝑅𝑖𝑛 = (2)
1 + 𝑔𝑚2 𝑅1 (𝑔𝑚1 𝑅3 + 1)

where 𝑔𝑚1 and 𝑔𝑚2 are the transconductance values of transistors M1 and M2 respectively.

Fig. 7 Basic TIA structures (a) Common gate topology (b) RGC configuration.

1.2 Shunt-Shunt Feedback Structure

In this feedback topology, input resistance is lowered allowing input pole rise in magnitude, hence, it leads to better
absorption of photodiode current as in Fig. 2.

Fig. 2 Feedback transimpedance amplifier structure [16].

2
The basic transimpedance gain formula can be represented by the following expression [16]:

𝑉𝑜𝑢𝑡 𝐴 𝑅𝐹
=− (3)
𝐼𝑖𝑛 𝐴 + 1 1 + 𝑅𝐹 𝐶𝐷 𝑆
𝐴+1

Following a transfer function assumption of a closed loop frequency domain gain as:

𝐴𝑜
𝐴(𝑆) = (4)
𝑆
1+
𝜔𝑜

For which 𝐴𝑜 is the open loop gain. A second order TIA gain formula is achieved:

𝑉𝑜𝑢𝑡 𝐴𝑜 𝑅𝐹
= (5)
𝐼𝑖𝑛 𝑅𝐹 𝐶𝐷 2 1
𝑆 + (𝑅𝐹 𝐶𝐷 + ) 𝑆 + 𝐴𝑜 + 1
𝜔𝑜 𝜔𝑜

In addition to maintaining a reasonably good TIA gain as in Eq. 5, a better noise optimization can be secured in
which the feedback resistor 𝑅𝐹 does not carry bias current when it is large enough. The input referred noise of the
feedback amplifier is given as:

4𝐾𝑇 𝑉̅̅̅̅̅
2
𝑛,𝑖𝑛
𝑖̅̅̅̅̅
2
𝑛,𝑖𝑛 = + 2 (6)
𝑅𝐹 𝑅𝐹

A large 𝑅𝐹 makes the choice of shunt-shunt feedback more reliable in noise reduction especially when 𝑅𝐹 is replaced
by a frequency dependent active inductor as it will be demonstrated in the proposed TIA design.

2. Proposed Transimpedance Amplifier Topology

The 90 nm TIA design consists of two stages as in Fig. 3, the first stage is the g m-boosted RGC followed by a shunt-
shunt feedback stage that have an active inductor formation instead of ordinary feedback resistor. The frequency
dependent active inductor consists of two P-MOSFET transistors, M4 and M5 previously used as a current source
[11]. This TIA specifications and design topology are considered to be considerable development of earlier 0.35 µm
technology research work [17].

One of the major challenges comes from the fact that an ordinary inductor is transformed into an open circuit at high
frequencies while it is a simple short circuit at low frequencies. In the case of an active inductor, this challenge is
virtually overcome especially within a specific frequency response domain in which it needs not reaching an open
circuit state.

3
Fig. 3 The proposed TIA circuit schematic representation.

It is considered that 𝐶𝐴 = 𝐶𝑔𝑏2 + 𝐶𝑑𝑏1 + 𝐶𝑑𝑏𝑝7 is the total capacitance to ground at node A, while 𝐶𝐵 = 𝐶𝑔𝑠1 +
𝐶𝑠𝑏2 + 𝐶𝑃𝐷 is the total capacitance to ground at node B. In addition, 𝐶𝐴𝐵 = 𝐶𝑔𝑠2 + 𝐶𝑔𝑑1 is the sum of Gate-Source
capacitance of transistor M2 and Gate-Drain capacitance of transistor M1. Output node capacitance will be considered
at the input of the next stage (shunt-shunt feedback). All parasitic capacitances 𝐶𝐴 , 𝐶𝐵 and 𝐶𝐴𝐵 were taken into
account without approximations. DC biasing was at ground for V B6 and VB7 (PMOS), while VB6 = 0.36 V (NMOS).

Following small signal analysis on the sum of currents at node A, the input and the output nodes, the following
transfer function is obtained according to the small signal RGC model of Fig. 4.

Fig. 4 Small signal model of RGC topology.

𝐼𝑜𝑢𝑡 𝑔𝑚2 (𝑔𝑑𝑠7 + 𝑔𝑚1 ) + 𝑔𝑚2 𝐶𝐴 𝑆

= (7)
𝐼𝑖𝑛 𝑎𝑆 2 + 𝑏𝑆 + 𝑐
As it is considered that:

𝑎 = (𝐶𝐴𝐵 𝐶𝐴 + 𝐶𝐴 𝐶𝐵 + 𝐶𝐴𝐵 𝐶𝐵 ) (8𝑎)

4
𝑏 = (𝐶𝐴𝐵 (𝑔𝑑𝑠7 + 𝑔𝑚1 ) + 𝑔𝑚2 𝐶𝐴 + 𝑔𝑑𝑠7 𝐶𝐵 ) (8𝑏)

𝑐 = 𝑔𝑚2 (𝑔𝑑𝑠7 + 𝑔𝑚1 ) (8𝑐)

Pole zero location is 𝑧1 = (𝑔𝑑𝑠7 + 𝑔𝑚1 )⁄𝐶𝐴 and that is an initial pole which is the inverse time constant of node A.
The resistance of the input RGC stage is:

1
𝑅𝑖𝑛−𝑅𝐺𝐶 = (9)
𝑔𝑚2 (1 + 𝑔𝑚1 𝑟𝑑𝑠7 )

When the frequency of operation is increased, the current gain falls as a result of parasitic capacitances associated
with node A that shunt signal to ground. In addition, the Miller capacitance 𝐶𝐴𝐵 lowers the local feedback gain
(1 + 𝑔𝑚1 𝑟𝑑𝑠7 ) at high frequency that contribute to the cancellation of the virtual ground effect at input node. Despite
of these RGC drawbacks, a compensating second stage can reverse gain deterioration to a considerable extent.

Fig. 5 Small signal model of the shunt-shunt feedback structure.

Following the small signal model of the shunt-shunt feedback structure in Fig. 5, the total capacitance 𝐶𝐷 = 𝐶𝑑𝑏2 +
𝐶𝑔𝑠3 + 𝐶𝑠𝑏𝑝4 + 𝐶𝑠𝑏𝑝5 is at the drain of transistor M2 while the total capacitance at the drain of transistor M3 is 𝐶3 =
𝐶𝑑𝑏3 + 𝐶𝑑𝑏8 + 𝐶𝑑𝑏𝑝4 + 𝐶𝐿 in which the sum of currents at the input and output nodes leads to the following transfer
function of the shunt-shunt feedback amplifier.

𝑉𝑜𝑢𝑡
𝐼𝑖𝑛

1 − 𝑍𝑓 𝑔𝑚3
= (10)
𝑔𝑑𝑠8 𝐶3 1
( + (𝑔𝑑𝑠8 𝐶𝐷 + ) 𝑆 + 𝐶3 𝐶𝐷 𝑆 2 ) 𝑍𝑓 + (𝐶3 + 𝐶𝐷 )𝑆 + 𝑔𝑑𝑠8 + 𝑔𝑚3 +
𝑅𝐷 𝑅𝐷 𝑅𝐷

𝐶3 1
where 𝛼 = (𝑔𝑑𝑠8 𝐶𝐷 + ) and 𝛽 = 𝑔𝑑𝑠8 + 𝑔𝑚3 + for simplicity.
𝑅𝐷 𝑅𝐷

The active inductor feedback impedance at the drain node of transistor M 4 is defined as [11]:

𝑟𝑜5 𝐶𝑔𝑠4 𝑆 + 1
𝑍𝑓 = (11)
𝑔𝑚4 + 𝐶𝑔𝑠4 𝑆

5
As far as Eq. (11) is concerned, no design constraints were involved given the fact that approximation such as
𝑟𝑜5 𝐶𝑔𝑠4 𝑆 ≪ 1 may not necessarily hold. The final state of the shunt-shunt feedback TIA gain representation is given
in Eq. (12):

𝑉𝑜𝑢𝑡 𝑅𝐷 [(𝑔𝑚4 − 𝑔𝑚3 ) + 𝐶𝑔𝑠4 (1 − 𝑔𝑚3 𝑟𝑜5 )𝑆]

= (12)
𝐼𝑖𝑛 𝑎3 𝑆 3 + 𝑎2 𝑆 2 + 𝑎1 𝑆 + 𝑎0

Taking into account that:

𝑎3 = 𝐶3 𝐶𝐷 𝑅𝐷 𝑟𝑜5 𝐶𝑔𝑠4 (13𝑎)

𝑎2 = 𝑅𝐷 𝐶𝑔𝑠4 (𝑔𝑑𝑠8 𝐶𝐷 𝑟𝑜5 + 𝐶3 + 𝐶𝐷 ) + 𝐶3 (𝑟𝑜5 𝐶𝑔𝑠4 + 𝐶𝐷 𝑅𝐷 ) (13𝑏)

𝑎1 = 𝑅𝐷 (𝑔𝑑𝑠8 (𝐶𝐷 + 𝐶𝑔𝑠4 ) + 𝑔𝑚4 (𝐶3 + 𝐶𝐷 )) + 𝐶𝑔𝑠4 (𝑔𝑑𝑠8 𝑟𝑜5 + 𝑔𝑚3 𝑅𝐷 ) + 𝐶3 (13𝑐)

𝑎0 = (𝑔𝑑𝑠8 + 𝑔𝑚4 (𝑔𝑑𝑠8 + 𝑔𝑚3 ) + 1) (13𝑑)

The TIA DC gain of the shunt-shunt feedback amplifier is [𝑅𝐷 (𝑔𝑚4 − 𝑔𝑚3 )]⁄𝑎0 . The input impedance of the shunt-
shunt feedback is worked out from the small signal model of Fig. 5 as it is:

𝑅𝐷 (𝑟𝑜5 𝐶𝑔𝑠4 𝑆 + 1)
𝑍𝑖𝑛−𝑠ℎ𝑢𝑛𝑡 (𝑆) = (14)
𝑟𝑜5 𝐶𝑔𝑠4 𝐶𝐷 𝑅𝐷 𝑆 2 + (𝑟𝑜5 𝐶𝑔𝑠4 + 𝑅𝐷 (𝐶𝐷 + 𝐶𝑔𝑠4 )) 𝑆 + (1 + 𝑅𝐷 𝑔𝑚4 )

where 𝐴′ = 𝑟𝑜5 𝐶𝑔𝑠4 𝐶𝐷 𝑅𝐷 , 𝐵′ = (𝑟𝑜5 𝐶𝑔𝑠4 + 𝑅𝐷 (𝐶𝐷 + 𝐶𝑔𝑠4 )) and

𝐶 ′ = (1 + 𝑅𝐷 𝑔𝑚4 ) .

Having an input resistance:

𝑅𝐷
𝑅𝑖𝑛−𝑠ℎ𝑢𝑛𝑡 = (15)
1 + 𝑅𝐷 𝑔𝑚4

Multiplying the transfer function of both RGC (Eq. (7)) and shunt-shunt feedback (Eq. (12)) stages, a fifth order
polynomial denominator is embedded within the TIA gain of Eq. (16) as follows:

𝑉𝑜𝑢𝑡 𝑅𝐷 (𝐴 + 𝐵𝑆 + 𝐶𝑆 2 )
=
𝐼𝑖𝑛 𝑎𝑎3 𝑆 + (𝑎𝑎2 + 𝑏𝑎3 )𝑆 + (𝑎𝑎1 + 𝑏𝑎2 + 𝑐𝑎3 )𝑆 3 + (𝑎𝑎0 + 𝑏𝑎1 + 𝑐𝑎2 )𝑆 2 + (𝑏𝑎0 + 𝑐𝑎1 )𝑆 + 𝑐𝑎𝑜
5 4

𝐴 = 𝑔𝑚2 (𝑔𝑑𝑠7 + 𝑔𝑚1 )(𝑔𝑚4 − 𝑔𝑚3 ) (17𝑎)

𝐵 = 𝑔𝑚2 𝐶𝑔𝑠4 (𝑔𝑑𝑠7 + 𝑔𝑚1 )(1 − 𝑔𝑚3 𝑟𝑜5 ) + 𝐶𝐴 (𝑔𝑚4 − 𝑔𝑚3 ) (17𝑏)

𝐶 = 𝑔𝑚2 𝐶𝐴 𝐶𝑔𝑠4 (1 − 𝑔𝑚3 𝑟𝑜5 ) (17𝑐)

6
where
, 𝐵′′ = (𝑎𝑎2 + 𝑏𝑎3 ) , 𝐶 ′′ = (𝑎𝑎1 + 𝑏𝑎2 + 𝑐𝑎3 ) , 𝐷 = (𝑎𝑎0 + 𝑏𝑎1 + 𝑐𝑎2 ) , 𝐸 = (𝑏𝑎0 + 𝑐𝑎1 ) and 𝐹 =𝐴′′ = 𝑎𝑎3
𝑐𝑎𝑜 .

The TIA DC gain is 𝑅𝐷 𝐴⁄𝑐𝑎0 while the two pole zero locations can be easily worked out by numerically solving
numerator quadratic formation in Eq. (16). Given the fact that the total input capacitance is 𝐶𝐵 , while Eq. (9)
represents the input resistance of the input stage, hence, the 𝑓−3𝑑𝐵 bandwidth Eq. is given as:

𝑔𝑚2 (1 + 𝑔𝑚1 𝑟𝑑𝑠7 )

𝑓−3𝑑𝐵 = (18)
2𝜋𝐶𝐵

The purpose of using RGC stage followed by a shunt-shunt feedback stage will be realized in the next section. As far
as the RGC stage is concerned and according to Eq.s (9) and (18), minimized input resistance and parasitic
capacitance leads to wider bandwidth, while the benefit of using a subsequent shunt-shunt feedback stage is to
provide an output voltage through TIA gain according to Eq. (12) given that the TIA DC gain is
[𝑅𝐷 (𝑔𝑚4 − 𝑔𝑚3 )]⁄𝑎0 .

2.1 Amplifier Gain And Impedance Results

Simulated transimpedance amplifier analysis for the proposed circuit shown in Fig. 6 indicated that the amplifier
gain is 62.9 dBΩ with 𝑓−3𝑑𝐵 bandwidth of 2.7 GHz (logarithmic scale). The transition frequency 𝑓𝑇 =
(1⁄2𝜋)(𝑔𝑚 ⁄(𝐶𝑔𝑠 + 𝐶𝑔𝑑 )) was applied as to the 90 nm CMOS technology and was found to be 25.4 GHz for output
node at the drain of transistor M3. Bandwidth simulation is in total agreement with Eq. (18), in which 𝑔𝑚1 =
1.62 𝑚𝑆, 𝑔𝑚2 = 1.9 𝑚𝑆, 𝑟𝑑𝑠7 = 160 Ω and 𝐶𝐵 = 249 𝑓𝐹. This simulation result is intended for 2.5 Gb/s Non-
Return-To-Zero fiber optic transmission.

Fig. 6 Simulated transimpedance gain of the proposed circuit.

A mathematical representation following Eq. (16) is visualized in which parasitic capacitances and
transconductances values were extracted from simulation and were applied to Eq. (16) alongside feedback
impedance components according to Eq. (11). A TIA gain of 345 Ω was worked out as indicated in Fig. 7 at the
specified 2.7 GHz bandwidth already achieved in simulation.

7
Fig. 7 A Calculated transimpedance gain for the proposed circuit.

The simulated input impedance is around 11.7 Ω at 2.7 GHz as a result of the g m-boosted RGC topology as in Fig. 8.
Behavioral frequency response of the active inductor feedback impedance 𝑍𝑓 is demonstrated in Fig. 9 according to
active inductor behavior, there was no actual observation of inductive peaking despite wide range of feedback system
parameter sweep concerning transistors M4 and M5. Extremely low signal drain current of transistor M 5 provides an
explanation for the high valued feedback impedance 𝑍𝑓 following Eq. (11) given that 𝑟𝑜5 is extremely high.

Fig. 8 Input impedance for the TIA topology.

8
Fig. 9 The frequency response of the active inductor feedback impedance for three cases of transistor M4; (a)
𝑔𝑚 = 3.56𝑚𝑆 , 𝑉𝑡ℎ = −0.2𝑉 (b) 𝑔𝑚 = 9.79𝑚𝑆 , 𝑉𝑡ℎ = −0.55𝑉 (c) 𝑔𝑚 = 12.5𝑚𝑆 , 𝑉𝑡ℎ = −0.7𝑉.

Fig. 10 TIA gain through parameter sweep for transistor M 8: (a) (𝑊 ⁄𝐿) = 20 , (b) (𝑊 ⁄𝐿) = 2.

A TIA gain through major parameter sweep was carried out as to the width of transistor M 8 (current source). A width
ranging from 2 up to 20 times channel length was considered as in Fig. 10. The optimal results remained as
illustrated earlier in Fig. 6 regarding gain and bandwidth and so was the case for the optimal condition of the input
referred noise current as it will be demonstrated later.

9
2.2 Transient Analysis Results

Simulated signal drain current of transistor M4 is considered for transient analysis and is assumed to have a unit step
response ID4(t). In Fig. 11, at t > 0, there is a positive value for the unit step function although not entirely constant,
but with a change of less than 20 µA. However, a derivative of the unit step function with respect to time
demonstrates the unit impulse function δ(t) as in Fig. 12. This function is in total agreement with the fact that a unit
impulse function is undefined at t = 0, hence, while it is 0 at t > 0, the undefined sharp rise is taken as 1 as t = 0.
Impulse durations at t < 0 (unit impulse function = 0) may be beyond the scope of this work with regard to signal
drain current ID4(t). The strength of the impulse function demonstrated in Fig. 12 corresponds to the function pulse
area although with very short time duration.

Fig. 11 Transistor M4 drain current ID4 in unit step function representation.

Fig. 12 Transistor M4 drain current ID4 in impulse function response.

10
Assuming that the unit step function ID4(t) is integrated with unit impulse function δ(t-t0) at an initial time condition
(t0 = 0), then a unit ramp function is obtained as in Fig. 13. The Fourier transform of the unit impulse function δ(t-t0)
for ID4(t) in comparison with input current signal is represented in Fig. 14 with nine harmonics based upon a
fundamental frequency resolution of 2.7 GHz. Sampling or Sifting property can always be initiated at initial time
condition 0 < t0 < t through which the point of impulse takes place. Transient analysis of I D4(t) is a measure of TIA
gain sensitivity given that ID4(t) is the most dominant drain current within the TIA shunt-shunt feedback system.

Fig. 13 Ramp response for transistor M4 drain current ID4.

Fig. 14 Fourier transform of the input current signal (dotted line) in relation to transistor M 4 signal drain current
(bold line).

2.3 Noise Analysis With Simulation Results

A generic noise model of the proposed TIA circuit is illustrated in Fig. 15.

11
Fig. 15 Noise model superposition.

The input equivalent noise current for the proposed TIA circuit 𝑖̅̅̅𝑖𝑛 is strictly evaluated for the RGC input stage
given the fact that output noise current is referred back to the input. The main cause for the output noise current
𝑖𝑜1 is the thermal noise generated by the current source ̅̅̅̅̅̅
fraction ̅̅̅̅ 𝑖𝑑𝑀6 [18].

[𝑔𝑚2 (𝑔𝑑𝑠7 + 𝑔𝑚1 ) + 𝑔𝑚2 𝐶𝐴 𝑆] × 𝑖̅̅̅̅̅̅

𝑑𝑀6
𝑖̅̅̅̅
𝑜1 = (19)
𝑎𝑆 2 + 𝑏𝑆 + 𝑐

The thermal noise current ̅̅̅̅

𝑖𝑑2 (from drain of transistor M2) is the main cause for the fractional output noise current
𝑖̅̅̅̅
𝑜2 which is expressed as follows:

[𝑀(𝑆) 𝐶𝐴𝐵 𝑆 + 𝑁(𝑆)𝐶𝐵 𝑆] × ̅̅̅̅

𝑖𝑑2
̅̅̅̅
𝑖𝑜2 = (20)
𝑎𝑆 2 + 𝑏𝑆 + 𝑐

where for simplicity,

𝑀(𝑆) = (𝑔𝑑𝑠7 + 𝐶𝐴 𝑆 + 𝑔𝑚1 )

𝑁(𝑆) = (𝑔𝑑𝑠7 + (𝐶𝐴 + 𝐶𝐴𝐵 )𝑆)

The fractional output noise current 𝑖̅̅̅̅

𝑜3 is due to the thermal noise current 𝑖̅
𝐻 from drains of transistors M 1 and M7 (
𝑖̅𝐻 = 𝑖̅̅̅̅
𝑑1 + 𝑖̅̅̅̅̅̅
𝑑𝑀7 ).

−𝐶𝐵 𝑔𝑚2 𝑆 𝑥 𝑖̅𝐻

𝑖̅̅̅̅
𝑜3 = (21)
𝑎𝑆 2 + 𝑏𝑆 + 𝑐

The equivalent noise current within the feedback system 𝑖̅̅̅̅̅̅

𝑖𝑛𝑓𝑏 is the main cause for the output noise current ̅̅̅̅
𝑖𝑜4 , in
which 𝑖̅̅̅̅
𝑜4 = ̅̅̅̅̅̅
𝑖𝑖𝑛𝑓𝑏 . The total output noise current 𝑖̅̅̅̅̅̅̅
𝑜−𝑡𝑜𝑡 is referred back to the input node for the proposed TIA
circuit using the transfer function of Eq. (7).

𝑖̅̅̅̅̅̅̅
2 ̅̅̅̅
2 ̅̅̅̅
2 ̅̅̅̅
2 ̅̅̅̅
2
𝑜−𝑡𝑜𝑡 = 𝑖𝑜1 + 𝑖𝑜2 + 𝑖𝑜3 + 𝑖𝑜4 (22)

In equivalence, it is:

12
 2
𝑔𝑚2 (𝑔𝑑𝑠7 + 𝑔𝑚1 ) + 𝑔𝑚2 𝐶𝐴 𝑆
𝑖̅̅̅̅̅̅̅
2
𝑜−𝑡𝑜𝑡 = | | × ̅̅̅
𝑖2𝑖𝑛 (23)
𝑎𝑆 2 + 𝑏𝑆 + 𝑐

The input referred noise current spectral density is improvised as follows:

2 2
(𝑔𝑑𝑠7 + 𝐶𝐴 𝑆 + 𝑔𝑚1 )𝐶𝐴𝐵 𝑆 + (𝑔𝑑𝑠7 + (𝐶𝐴 + 𝐶𝐴𝐵 )𝑆)𝐶𝐵 𝑆 −𝐶𝐵 𝑆
2 = ̅̅̅̅̅̅
𝑖̅̅̅ 𝑖2𝑑𝑀6 + | | × 𝑖̅̅̅̅
2
| 𝑥 𝑖̅2𝐻
𝑖𝑛 𝑑2 + |
𝑔𝑚2 (𝑔𝑑𝑠7 + 𝑔𝑚1 ) + 𝑔𝑚2 𝐶𝐴 𝑆 (𝑔𝑑𝑠7 + 𝑔𝑚1 ) + 𝐶𝐴 𝑆
2
𝑎𝑆 2 + 𝑏𝑆 + 𝑐
+| | × ̅̅̅̅̅̅
𝑖2𝑖𝑛𝑓𝑏 (24)
𝑔𝑚2 (𝑔𝑑𝑠7 + 𝑔𝑚1 ) + 𝑔𝑚2 𝐶𝐴 𝑆

Although it is reasonable to consider that 𝑔𝑑𝑠7 and 𝐶𝐴 𝑆 are much smaller than 𝑔𝑚1 , it may not be possible to ignore
them since operation frequency of the proposed TIA is not far below 𝑓𝑇 . Defining the fractional input referred noise
current ̅̅̅̅̅̅
𝑖2 within the active inductor feedback system as follows:
𝑖𝑛𝑓𝑏

2
𝐶𝐷 𝑆 ̅̅̅̅
𝑖̅̅̅̅̅̅
2
𝑖𝑛𝑓𝑏 = [| | (𝑖2𝑑3 + 𝑖̅̅̅̅
2 ̅̅̅̅
2 ̅̅̅̅
2
𝑑8 )] + 𝑖𝑅𝐷 + 𝑖𝑍𝑓 (25)
𝑔𝑚3

That can lead to:

𝜔2 𝐶𝐷2 1 1 1
𝑖̅̅̅̅̅̅
2
𝑖𝑛𝑓𝑏 = 2 × 𝛾4𝐾𝑇 (𝑔𝑚3 + + + ) (26)
𝑔𝑚3 𝑟𝑑𝑠8 𝑅𝐷 |𝑍𝑓 |

A simulated data for the input referred noise current is manifested in Fig. 16 in which 21 𝑝𝐴⁄√𝐻𝑧 is achieved at 2.7
GHz.

Fig. 16 Simulation of the input-referred noise current spectral density.

13
In Table 1, many TIA design performances are indicated in comparison to this competitive work. A power
consumption of 1.22 mW indicates that the drain current of transistors M 4 and M5 (part of the active inductor region)
was low enough which enabled the decline in power consumption compared to other research literature given in
Table1. Higher TIA gain, lower supply voltage and lower power consumption were the main emphasis of the
proposed 90 nm CMOS TIA topology.

Table 1: Proposed TIA design performance in relation to other research works.

Ref. [19] [20] [21] [22] [23] [24] [4] [11] [25] This Work

Year 2014 2017 2016 2016 2018 2018 2017 2018 2020 2022

CMOS Technology 0.18 0.18 0.18 0.18 0.13 0.18 0.13 90 55 90

µm µm µm µm µm µm µm nm nm nm
Gain (dBΩ) 60 50.8 62.2 54.3 50 45 51 41 69 62.9

Bandwidth (GHz) 2.9 7.9 4.3 7 15 21.2 10.5 3.4 10.7 2.7

Input referred noise 13.14 7.4 - 5.9 20 63.1 6.8 13.1 15 21

(𝒑𝑨⁄√𝑯𝒛 )
Supply Voltage (V) 1.8 1.8 1.8 1.8 1.2 1.8 1.2 1 1.2 1

Power Consumption 25.4 7.2 7.72 29 5.34 10.2 30 1.4 15.7 1.22
(mW)
No. of passive 0 1 0 0 0 0 2 0 0 0
inductors

3. Conclusion

A transimpedance amplifier with regulated cascode followed by active inductor-based shunt-shunt feedback stage
was envisaged. The active inductor feedback contributes to better integrated circuit design advantage in terms of
volume and chip area as it was the main idea behind the proposed inductorless circuit. In addition, it conforms to the
demands for high TIA gain, low supply voltage and low power consumption.

Declarations

Competing Interests
There are no competing interests and that includes financial or personal nature
Author’s Contributions
Not Applicable / Single Author
Funding
No funding received
Availability of Data and Materials
By simple docx format as in Table 1. Figures are in TIFF format.

14
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