SCHEM, MLB, PB17": Bom Options

8 7 6 5 4 3 2 1
CK ENG
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD APPD
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. REV ZONE ECN DESCRIPTION OF CHANGE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. DATE DATE
A 285476 PRODUCTION RELEASED 07/28/03 ?
D PAGE CONTENTS PAGE CONTENTS D
1
2
TITLE PAGE AND CONTENTS
SYSTEM BLOCK DIAGRAM

22
23
LMU, LIGHT SENSOR, BOOTBANGER, SLEEP LED
SPIDEY - KBD,TPAD,HALL EFFECT,PWR BUTTON
INTERNAL CONNECTORS - DVD,
CARDSLOT, HARD DRIVE, LEFT USB/BLUETOOTH
SCHEM,MLB,PB17"
3 POWER BLOCK DIAGRAM 24 FAN CONTROLLER, MODEM, SOUND
SERIAL DEBUG (JOLLY ROGER, PWR/NMI/RESET)
07/28/2003
4 PCB NOTES AND HOLES 25 USB 2.0 BOM OPTIONS STUFF NO STUFF
D3_HOT
5 MPC7450 MAXBUS INTERFACE 26 MARVELL GIGABIT ETHERNET PHY
D3_COLD
6 MPC7450 DATA 27 FIREWIRE A/B PHY GPU_SS

GPU_SWITCH
7 CPU PLL AND CONFIGURATION STRAPS 28 FIREWIRE A/B CONNECTORS, PORT POWER LIMITER
SERIAL_DEBUG
C 8 INTREPID MAXBUS AND BOOT STRAPS 29 PMU (POWER MANAGEMENT UNIT) VCORE_OFFSET C
1_8V_MAXBUS
9 INTREPID MEMORY INTERFACE / BOOT ROM 30 BATTERY CHARGER AND CONNECTOR
1_5V_MAXBUS
10 DDR MEMORY MUXES 31 12.8V SYSTEM POWER SUPPLY / PMU POWER SUPPLY NEC_USB
INTREPID_USB
11 200PIN DDR MEMORY SODIMM CONNECTORS 32 3.3V / 5V SYSTEM POWER SUPPLIES
BBANG
12 INTREPID AGP 4X/PCI 33 CPU CORE VOLTAGE POWER SUPPLY
NO_BBANG
13 INTREPID ENET/FW/UATA/EIDE INTERFACES 34 1.5V/ 1.8V / 2.5V SYSTEM POWER SUPPLIES ATI_MEMIO_HI
ATI_MEMIO_LO
14 INTREPID GPIOS/SERIAL/USB INTERFACES/SSCG 35 SIGNAL CONSTRAINTS (1 OF 3) - DIGITAL/CLK
SSCG
15 INTREPID POWER RAILS 36 SIGNAL CONSTRAINTS (2 OF 3) - DIGITAL/DIFF NO_SSCG
5V_HD_LOGIC
B 16 INTREPID DECOUPLING 37 SIGNAL CONSTRAINTS (3 OF 3) - POWER NETS B
3V_HD_LOGIC
17 CARDBUS CONTROLLER (PCI1510) 38 FUNCTIONAL TEST POINTS EXT_TMDS
INT_TMDS
18 M10 AGP & CLOCKS 39 REVISION HISTORY (1 OF 1)
19 M10 LVDS/TMDS/VGA/GPIO & GPU VCORE 40-41 SIGNAL NAMES
20 M10 ANALOG, POWER, GND 42-43 COMPONENT LOCATIONS
VIDEO CONNECTORS - INVERTER, DVI, S-VIDEO

21 DUAL-CHANNEL LVDS
DIMENSIONS ARE IN MILLIMETERS
METRIC Apple Computer Inc.

XX
A X.XX
DRAFTER DESIGN CK NOTICE OF PROPRIETARY PROPERTY A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
X.XXX PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
ENG APPD MFG APPD
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
ANGLES II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
TABLE_5_HEAD QA APPD DESIGNER TITLE
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION DO NOT SCALE DRAWING
TABLE_5_ITEM
051-6459
820-1524
1
1
SCHEM,MLB,PB17 INCH
PCBF,MLB,PB17 INCH
SCH1
PCB1
TABLE_5_ITEM
RELEASE SCALE
NONE
SCHEM,MLB,PB17 INCH
SIZE DRAWING NUMBER REV.
MATERIAL/FINISH
NOTED AS D 051-6459 A
THIRD ANGLE PROJECTION APPLICABLE SHT 1 OF 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
J18 J24 J22
Ethernet FW - A FW - B
Connector Connector Connector SLEEP
P.29 P.29 LED LMU
P.27 J25 J19
P.25
2 DATA PAIRS
2 DATA PAIRS Battery Power Supply SUTRO (PWR)
4 DATA PAIRS @ 200MHz Connector & Charger
@ 400MHZ Connector
U28 D
D U49 J11 P.31 P.31-35 P.31
FireWire OPTICAL DRIVE
Ethernet PHY J14
PHY Connector U36
P.28 TUBA (SOUND) SMBUS
P.27 P.24
G/MII J13
Connector
P.25
3.3V LMU I2C
3.3V 1394 OHCI ULTRA ATA/100 U39
10/100/1000 3.3V Connector P.23
8BIT TX 8BIT TX/RX
100MHZ P.24
EIDE
I2S I2C
U48/J2/J4
Fan
PMU
8BIT RX
125MHZ I2C Circuit P.30 J10
UIDE P.25 CARDBUS
SERIAL
NOT USED Connector
J3 (SHARE WITH BLUETOOTH) 5V
ETHERNET FIREWIRE P.18
LEFT USB UATA 100 EIDE CARDSLOT I2S I2C J15
10/100/1000 800 MB/S P.14
P.14 P.14 P.14 P.15 J5
P.24 USB 2.0 P.14 P.14 P.15 TRACKPAD Keyboard 33MHZ
C USB PORT A SCCA
Serial Debug
Connector Connector 16/32 BITS C
J12 Connector 3.3V/5V
P.15 P.15 KB LED U26
RIGHT USB NOT USED USB PORT B P.25
LIGHT SENSOR
BACKUP BATTERY
P.32
USB 2.0
P.15
USB PORT C
U44 VIA/PMU
P.15 U17
P.23 TI PCI1510
CardBus
P.15 U52
J3 (SHARE WITH LEFT USB)
BlueTooth NOT USED USB PORT D
INTREPID BOOTROM
P.14
BOOT ROM
1M X 8 USB 2.0
CONTROLLER
Controller
P.18
P.15 P.10
P.24 P.26
USB PORT E PCI
J9 P.15 32BITS PCI BUS
33MHZ 32BITS
Modem Board USB PORT F 33MHZ
P.15 P.13
Connector AGP BUS 3.3V
1.5V/3.3V U43
P.25
32BITS MEMORY MEMORY
MAXBUS J21
66MHZ CH. A CH. C
4X AGP
B INTRPEID
I2C MAXBUS
P.9
DDR MEMORY P.13 ATI M10 (INTERNAL MEM) (INTERNAL MEM) AIRPOPT
Connector
B
1.8V P.10 MEMORY MEMORY
167MHZ
32BIT ADDRESS MEMORY BUS
64MB CH. B CH. D
P.24
64BIT DATA 2.5V P.18-20 (INTERNAL MEM) (INTERNAL MEM)
167MHZ J8
U42 U11/U12/U13/U14 64BITS
EDID (I2C)
COMPOSITE
Inverter
S-VIDEO
CPU PLL 2:1 DDR MUXES Connector
APOLLO
(DDC TOO)
Config P.21
LVDS
TMDS
RGB
P.11
CPU P.7
J7 J17 J16
(MPC7457) PMU
P.5-6 LCD Panel S-Video DVI-I
J20/J23 Connector Connector Connector
DDR SDRAM DIMM 0 P.21 P.21 P.21 SYSTEM BLOCK DIAGRAM
A NOTICE OF PROPRIETARY PROPERTY
A
DDR SDRAM DIMM 1 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
SO-DIMM Connector I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT
P.12 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE COMPUTER INC.

D 051-6459 A
SCALE SHT OF
NONE 2 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
POWER SYSTEM ARCHITECTURE

+5V_MAIN
1V20_REF -
>~13.44V TURNS-ON
U21
PG 31
+
BACKLIGHT VCC MAP31 DDR I/O DCDC_EN
<~13.44V SHUTS-OFF
INVERTER MAP31 DDR CORE SLEEP
MAIN 2.5V/1.5V DDR POWER
+PBUS
D AC RUN/SS D
DC/DC +2.5V_MAIN
ADAPTER INRUSH BUCK MAXBUS
LIMITER +24V_PBUS REGULATOR (MAX1715) SEQUENCING
VCC
IN PG 30
+PBUS (12.8V) PG 35 PGOOD 1_5V_2_5V_OK
(LTC1625)
PG 31 PG 32 SHUTDOWN: STOPPED
14V_PBUS +5V_MAIN SLEEP: RUNNING +1.5V_MAIN
AC: 12.8V RUN: RUNNING
NO AC: BATTERY VOLTAGE INTREPID CORE
1625 NOT RUNNING TURNS ON OUTPUT @ 2.4V AGP I/O +5V_MAIN
ON1/ON2
SHUTDOWN: RUNNING
SLEEP: RUNNING VCC SHDN
RUN: RUNNING
+5V_MAIN
DCDC_EN_L
AFTER PMU IS UP AND RUNNING
DCDC_EN_L WILL PULL ON1/ON2
DC/DC
RC AT 1M*0.047UF @ 24V (MAX1717)
+3V_PMU STARTS 2.0MSEC AFTER DCDC_EN_L BECOMES LOW
LOW IN SHUTDOWN
+BATT
+5V_MAIN
PG 34
LDO +3V_PMU
RUN/SS - 5V EXT_VCC
+4_6V_BU TURNS ON AT >1V +5V_MAIN +PBUS (12.8V) SHUTDOWN: STOPPED
C PG 32
<100UA ALLOWED
INTERNAL ZENER CLAMP TO 6V
VCC DC/DC SLEEP: STOPPED C
MAIN 3V/5V PGOOD 3V_5V_OK (LTC1778) GPU_VCORE RUN: RUNNING
PG 20
DC/DC SHUTDOWN: STOPPED +1.2V/+1.0V
(LTC3707) HOLDS BOTH RUN/SS AT GND
DCDC_EN SLEEP: D3HOT/D3COLD CPU_VCORE
VCC PG 33 STBYMD
WHEN IT’S CONNECTED TO GND
RUN: RUNNING (+1.4V/+1.5V)
TURNS CONTROL TO RUN/SS SLEEP
+PBUS WHEN IT’S OPEN
D3_COLD
TURNS ON AS LOW AS 0.8V/TYP 1.5V
SHUTDOWN: STOPPED INTERNAL 1.2UA CURRENT SOURCE
SLEEP: RUNNING GPU_VCORE RUN/SS

1_5V_2_5V_OK WILL NOT PULL LOW UNTIL
RUN: RUNNING SEQUENCING
BACKUP 12.8V CHARGES BACKUP BATTERY
INTERNAL ZENER CLAMP TO 6V
+3.3V_MAIN
+5V_MAIN TURNS ON
HOWEVER, 5V SHOULD TURN ON ~2.23MS AFTER
<100UA ALLOWED 1M & 0.1UF @14V, IT TAKES DCDC_EN_L OR PMU_POWERUP_L
BATTERY TURNS ON AT >1V

RUN/SS - 3V
~5.88MS TO START SWITCHER 1_5V_2_5V_OK
D3_HOT
BECOMES ’1’; MUCH LESS THAN THE
RC CHARGING AT INT_VCC (5V)
DCDC_EN_L
D3_HOT
24V IS OUTPUT ONLY FROM
BACKUP BATTERY
RC AT 1M*0.1UF @ 24V
CHARGER INPUT STARTS ~4.25MSEC AFTER DCDC_EN_L BECOMES LOW
SHUT-DOWN RUN SLEEP RUN SHUT-DOWN
NO INRUSH PROTECTION
& BOOST OUTPUT WHEN ONLY BATTERY IS CONNECTED SLEEP
B PG 32 +24V_PBUS SLEEP_L_LS5 B
BACKUP BATTERY CIRCUIT CHARGES OFF +PBUS
DCDC_EN
AND PREVENTS +PBUS AND +24V_PBUS FROM DROPPING BELOW 6V DC/DC DCDC_EN_L
(UNTIL DRAINED)
(LTC3411) +5V_MAIN ~11MS
+1.8V_MAIN
BATTERY PG 35 +5V_SLEEP
MAXBUS +3V_MAIN ~13.5MS
CHARGER SHUTDOWN: STOPPED BROADCOM
SLEEP: STOPPED +3V_SLEEP
(MAX1772) RUN: RUNNING 3V_5V_OK 2.4V - ??? MS
PG 31 +2_5V_MAIN 2.6 MS
+2_5V_SLEEP
+BATT +1_5V_MAIN 2.6 MS
NO INRUSH PROTECTION +1_5V_SLEEP

3S 3P PRISMATIC CELLS WHEN ONLY BATTERY IS CONNECTED
1_5V_2_5V_OK
(MAX1715 OUTPUT)
BATTERY VOLTAGE 1_5V_2_5V_OK POWER BLOCK DIAGRAM

A +PBUS
(AT LTC1778 RUN/SS)
A
GPU_VCORE ~???MS NOTICE OF PROPRIETARY PROPERTY
FEED-IN PATH (D3HOT)
GPU_VCORE AGREES TO THE FOLLOWING
PG 31 (D3COLD) I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

+1_8V_MAIN III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1.9 MS
APPLE COMPUTER INC.

D 051-6459 A
SCALE SHT OF
NONE 3 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BOARD HOLES
CHASSIS MOUNTS
ASICS HEATSINK
OMIT
MOUNTS I/O AREA INVERTER
ZT10 OMIT
255R158 ZT5 1
PCB SPECS
1 146R126
1 SH1 D
D OMIT 2
OG-503040
SHLD-SM
ZT2 CHGND5
3
255R158
1
OMIT BS1 CHGND2

STDOFF-217ODX150IDX35H-TH
ZT11 1
255R158
THICKNESS : 1.2 MM / 0.047 IN 1
CHGND1
OMIT
1/2 OZ CU THICKNESS: 0.7 MILS OMIT
ZT6
235R126
ZT83
146R126
1.0 OZ CU THICKNESS: 1.4 MILS 1
1
OMIT CHGND6
ZT16
235R126
1 SPEAKER CLIPS
IMPEDANCE : 50 OHMS +/- 10% SP6 SP1 SP3 SP5 SP2
DIELECTRIC: FR-4 SPKR_CLIP_P84 SPKR_CLIP_P84 SPKR_CLIP_P84 SPKR_CLIP_P84 SPKR_CLIP_P84
LAYER COUNT: 12 CONDUCTIVE MOUNTS

1 1 1 1 1
SIGNAL TRACE WIDTH: 4 MILS OMIT

ZT4
SIGNAL TRACE SPACING: 4 MILS 1
235R126 SP4
SPKR_CLIP_P84
C PREPREG THICKNESS: 2-3 MILS 1
C
SEE PCB CAD FILES FOR MORE SPECIFIC INFO.

GROUND VIAS
ZT48 ZT57 ZT22
BOARD STACK-UP AND CONSTRUCTION ZT77
HOLE-VIA-20R10
1
ZT35
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1
20R10 TH VIA OR VIA IN PAD

ZT81 ZT50 ZT56 ZT1 ZT25
HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10
HOLE-VIA-20R10 HOLE-VIA-20R10
1 SIGNAL (1/3 OZ + COPPER PLATING) 1 1 1 1 1
ZT24 ZT44 ZT72 ZT80 ZT3

2 PREPREG (3MIL)
HOLE-VIA-20R10 HOLE-VIA-20R10 1 1 1
1 1
GROUND (1/2 OZ) ZT73
ZT38 ZT66 ZT55 HOLE-VIA-20R10
ZT32
HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 1
HOLE-VIA-20R10
1 1
LAMINATE (4MIL) 1 1
3 SIGNAL (1/2 OZ) ZT36 ZT67 ZT29 ZT75 ZT31

HOLE-VIA-20R10 HOLE-VIA-20R10 1 1 1
1 1
PREPREG (3MIL) ZT63
4 SIGNAL (1/2 OZ) ZT27 ZT52 ZT74 ZT26
B HOLE-VIA-20R10
1
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1 HOLE-VIA-20R10
1
B
LAMINATE (4MIL) ZT82 ZT61
5 GROUND (1/2 OZ) ZT40 ZT53 HOLE-VIA-20R10 HOLE-VIA-20R10 ZT23
HOLE-VIA-20R10 HOLE-VIA-20R10 1 1 HOLE-VIA-20R10
1 1 1
ZT79 ZT54
6 PREPREG (2MIL) CUT POWER PLANE(1 OZ) ZT39
HOLE-VIA-20R10
ZT70
1
HOLE-VIA-20R10
1
ZT19
HOLE-VIA-20R10
1 1 1
ZT37 ZT71 ZT68 ZT51

LAMINATE (3MIL) HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 ZT17
7 CUT POWER PLANE(1 OZ) 1 1 1 1 HOLE-VIA-20R10
1
ZT28 ZT78 ZT60 ZT42

HOLE-VIA-20R10 ZT15
8 PREPREG (2MIL) GROUND (1/2 OZ)
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1 1 HOLE-VIA-20R10
1
ZT30 ZT69 ZT58 ZT64

HOLE-VIA-20R10 HOLE-VIA-20R10 ZT13
LAMINATE (4MIL) 1 1 1 1
HOLE-VIA-20R10
9 SIGNAL (1/2 OZ) 1
ZT34 ZT65 ZT41 ZT76

HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 ZT12
10 PREPREG (3MIL) 1 1 1 1 HOLE-VIA-20R10
SIGNAL (1/2 OZ) ZT62
1
ZT33 ZT47 ZT9 HOLE-VIA-20R10 ZT14

HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 1 HOLE-VIA-20R10
LAMINATE (4MIL) 1 1 1
1
11 GROUND (1/2 OZ) ZT7 ZT59
ZT43 ZT45 ZT18
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1 HOLE-VIA-20R10 BOARD INFORMATION
A 12 PREPREG (3MIL) SIGNAL (1/3 OZ + COPPER PLATING) ZT46 ZT49 ZT8 ZT21
1
NOTICE OF PROPRIETARY PROPERTY

A
HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 ZT20
1 1 1 1 HOLE-VIA-20R10
1 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
APPLE COMPUTER INC.

D 051-6459 A
SCALE SHT OF
NONE 4 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MAXBUS_SLEEP 5 7 8 15 16 23 34 38
1_5V_MAXBUS
+1_5V_SLEEP
CPU_VCORE_SLEEP
CPU_OVDD DECOUPLING NETWORK R702
5 34 38 39
CPU_VCORE DECOUPLING NETWORK 1
0 2
MPC7447 PULL-UPS
5%
1/16W
C25 C342 C344 C223 1 C91 1 C114 1 C104 1 C103 1 C110 1 C190 C189 R2061 1 C72 1 C48 1 C38 1 C74 1 C275 1 C46 1 C47 1 C170 MF
R2411 10uF 10uF
1
10uF
1
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
1
0.1uF 470 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1UF 0.1UF
603
38 34 23 16 15 8 7 5 MAXBUS_SLEEP
470 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% +1_8V_SLEEP 1_8V_MAXBUS
5% 20%
6.3V
20%
6.3V
20%
6.3V
20%
10V 10V
2 CERM 2 10V 10V
2 CERM 2 10V 2 10V 2 10V
20%
10V
5%
1/16W 10V
2 CERM 2 10V 10V
2 CERM 2 10V 2 10V 10V
2 CERM 2 10V
CERM 2 10V R693
1/16W 2 CERM 2 CERM CERM CERM CERM CERM 2 CERM CERM CERM CERM CERM
MF
402 2
CERM
805
CERM
805 805 402 402 402 402 402 402 402 402
MF
402 2
402 402 402 402 402 402 402 402
1
0 2
R58
CPU_TBEN 1
10K 2
5% 8 5
1/16W 5%
MF
1 C188 1 C155 603 1/16W
MF R160
C346 C8 C153 C138 1 C191 1 C112 1 C168 1 C149 1 C111 1 C150 1 C105 1 C73 1 C39 1 C107 1 C90 1 C257 1 C272 1 C92 10K
D
1
10uF
1
10uF
1
0.1uF
1
0.1uF 0.1uF
20%
0.1uF
20% 20%
0.1uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20%
0.1uF 0.1uF
20% 20%
0.1uF
20%
0.1uF
20%
0.1uF 0.1UF
20%
0.1UF
20% 0.1UF
20%
5 CPU_CHKS_L
402
1
5%
2
D
20% 20% 20% 20% 10V 2 10V 10V 2 10V 2 10V 2 10V 2 10V 10V 2 10V 10V 2 10V 2 10V 10V 2 10V 2 10V 2 10V
6.3V
2 CERM
6.3V
2 CERM
10V
2 CERM
10V
2 CERM 2 CERM
402
CERM
402
2 CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
2 CERM
402
CERM
402
2 CERM
402
CERM
402
CERM
402
2 CERM
402
CERM
402
CERM
402 CERM
402
R73 1/16W
MF
805 805 402 402
CPU_SHD0_L 1
10K 2
402
5
5%
1/16W
MF R87
1 C106 402 10K
1 C12 1 C340 1 C193 1 C154 1 C115 1 C113 1 C152 1 C151 1 C202 1 C201 1 C192 1 C224 1 C40 1 C194 1 C203 1 C273 1 C41 1 C169 1 C139 0.1UF
5 CPU_SHD1_L 1 2
2.2uF 2.2uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1UF 0.1UF 20% 5%
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
20%
10V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM
10V
2 CERM
10V
2 CERM
10V
2 CERM
10V
2 CERM
10V
2 CERM
10V
2 CERM
20%
10V
2 CERM
10V
2 CERM
10V
2 CERM
10V
2 CERM
10V
2 CERM
10V
2 CERM
10V
2 CERM
10V
2 CERM
10V
2 CERM 2 10V
CERM R139 1/16W
MF
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
CPU_MCP_L 1
10K 2
402
805 805 402 402 402 5
5%
1/16W
MF
402
R108
CPU_LSSD_MODE 1
10K 2
5
MORE 0805 10UF CAPS ON VCORE
POWER SUPPLY PAGE (PG 33) 5%
R72 1/16W
MF
H10
H12
J11
J13
K10
K12
K14
L11
L13
M10
M12
C12
E18
G18
P11
R13
R16
U12
U16
V10
V14
PLCAE SHORT CLOSE TO CENTER OF CPU 10K
H8
J7
J9
K8
L7
L9
M8
B4
C2
D5
F2
H3
J5
K2
L5
M3
N6
P2
P8
R4
T6
T9
U2
V4
V7
A8
CPU_L2TSTCLK 1 2 402
XW31
SM
5
5%
VDD OVDD AVDD 1/16W
R57
25 ADT7460_VCORE_MON 1 2 MF
OMIT CPU_VCORE_SLEEP 5 34 38 39
402
1
1K 2
39 5 CPU_CHKSTP_OUT_L
D2 B7
36 8 CPU_BR_L BR* BVSEL CPU_BUS_VSEL 7 5%
36 8 CPU_BG_L M1
BG* 2
R106 R148 1/16W
MF
NC SYSCLK A10 SYSCLK_CPU 8 36 402 1
10K 2
402
CPU_SRWX_L
1 C195 1 C347 1 C258 1 C345 36 8 CPU_TS_L L4
TS* CLKOUT H2 CPU_CLKOUT_SPN
1%
1/16W
5
5%
10UF 10UF 10UF 10UF MF
20% 20% 20% 20% PLLCFG0 B8 CPU_PLL_CFG<0> 7
CPU_AVDD 1 402
1/16W
MF R120
2 6.3V 2 6.3V 2 6.3V 2 6.3V E11 C8 38 402 10K
CERM
805
CERM
805
CERM
805
CERM
805
5 CPU_PULLDOWN A0 PLLCFG1 CPU_PLL_CFG<1> 7
5 CPU_PMONIN_L 1 2
H1 C7
A1 PLLCFG2 CPU_PLL_CFG<2> 7 5%
C11
A2 PLLCFG3 D7 CPU_PLL_CFG<3> 7
1 C137 1 C136 R109 1/16W
MF
C G3
F10
A3 PLL_EXT A7
M2
CPU_PLL_CFG<4> 7
0.1uF
20%
2.2uF
20%
5 CPU_EMODE1_L 1
10K 2
402
C
36 8 CPU_ADDR<0> A4 DBG* CPU_DBG_L 8 36
10V
2 CERM
10V
2 CERM
5%
1 C156 1 C341 1 C225 1 C343 36 8 CPU_ADDR<1> L2
A5 DRDY* R3 CPU_DRDY_L 8 36 402 805
1/16W
MF R98
10UF 10UF 10UF 10UF 36 8 CPU_ADDR<2> D11
A6 DTI0 G1 CPU_EDTI 5
402
1
1K 2
20% 20% 20% 20% 5 CPU_PULLUP
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 36 8 CPU_ADDR<3> D1
A7 DTI1 K1 CPU_DTI<0> 8 36 5%
805 805 805 805 C10 TABLE_5_HEAD
P1 1/16W
CPU_ADDR<4> A8 DTI2 CPU_DTI<1>
36 8
CPU_ADDR<5> G2
A9
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
DTI3 N1 CPU_DTI<2>
8 36
R107 MF
402
36 8 TABLE_5_ITEM 8 36
10K
36 8 CPU_ADDR<6> D12
A10 337S2733 1 IC,APOLLO7,1.X,1.3GHZ,1.XV CORE,85C U43 CRITICAL 1_30_VCORE CPU INTERNAL PLL FILTERING 39 23 7 5 CPU_HRESET_L 1 2
PLACE BELOW CPU L3 TABLE_5_ITEM
5%
IN FORMER L3 AREA
36 8 CPU_ADDR<7> A11 337S2807 1 IC,APOLLO7,1.X,1.33GHZ,1.32V VCORE,85C U43 CRITICAL 1_32_VCORE 1/16W
36 8 CPU_ADDR<8> G4
A12 TDI B9 JTAG_CPU_TDI 5 23 39
MF
402 R129
36 8 CPU_ADDR<9> T2
A13 TDO A4 JTAG_CPU_TDO_TP 39 1
10K 2
30 5 CPU_SMI_L
F4 F1
36 8 CPU_ADDR<10> A14 TMS JTAG_CPU_TMS 5 23 39 5%
V1 C6 1/16W
36 8 CPU_ADDR<11> A15 TCK JTAG_CPU_TCK 5 23 39
R59 MF
J4 A5 402
36 8 CPU_ADDR<12> A16 OMIT
TRST* JTAG_CPU_TRST_L 5 23 39
470
R2 E8 470OHM FOR BOOT BANGER 39 23 5 JTAG_CPU_TMS 1 2
36 8 CPU_ADDR<13> A17 LSSDMODE* CPU_LSSD_MODE 5
K5 G8 5%
36 8 CPU_ADDR<14>
CPU_ADDR<15> W2
A18
A19
U43 L1TSTCLK
L2TSTCLK B3
CPU_L1TSTCLK
CPU_L2TSTCLK
5 1/16W
MF
R128
36 8
36 8 CPU_ADDR<16> J2
A20
800MHZ 5 402
470
36 8 CPU_ADDR<17> K4
A21 APOLLO_MPC7445_360 TA* K6 CPU_TA_L 8 36
470OHM FOR BOOT BANGER 39 23 5 JTAG_CPU_TDI 1
5%
2
36 8 CPU_ADDR<18> N4
A22 BGA TEA* L1 CPU_TEA_L 8 36 1/16W
(1 OF 3) MF
36 8 CPU_ADDR<19> J3
A23 R79 402
36 8 CPU_ADDR<20> M5
A24 MPC7447 14 5 MPIC_CPU_INT_L 1
10K 2
P5 E1
36 8 CPU_ADDR<21> A25 TBEN CPU_TBEN 5 8 5%
N3 P4 1/16W
36 8 CPU_ADDR<22> A26 QREQ* CPU_QREQ_L 8 36 MF
36 8 CPU_ADDR<23> T1
A27 QACK* G5 CPU_QACK_L 8 36
402 R65
V2 A3 1
10K 2
36 8 CPU_ADDR<24> A28 CKSTP_IN* 39 5 CPU_SRESET_L
B 36 8 CPU_ADDR<25>
CPU_ADDR<26>
U1
N5
A29
A30
CKSTP_OUT* B1 CPU_CHKSTP_OUT_L 5 39 5%
1/16W
MF
B
36 8
CPU_ADDR<27> W1
A31
R130 402
36 8
1
10K 2
B12 5 CPU_L1TSTCLK
36 8 CPU_ADDR<28> A32
C4 5%
36 8 CPU_ADDR<29> A33 D4 1/16W
36 8 CPU_ADDR<30> G10
A34
INT*
F9
MPIC_CPU_INT_L 5 14 MF
402
R60
B11 SMI* CPU_SMI_L 5 30
1
10K 2
36 8 CPU_ADDR<31> A35 C9 5 CPU_EDTI
MCP* CPU_MCP_L 5
5%
A2
C1 SRESET* CPU_SRESET_L 5 39
R97 1/16W
NC AP0 D8
MF
E3 HRESET* CPU_HRESET_L 5 7 23 39 10K 402
NC AP1 39 23 5 JTAG_CPU_TCK 1 2
H6
NC AP2 5%
F5 1/16W
NC AP3 MF
402
R61
NC G7 AP4 CPU_PULLDOWN 1
470 2
5
PMON_IN* D9 CPU_PMONIN_L 5 5%
E5
36 8 CPU_TT<0> TT0 A9 NC
1/16W
E6 PMON_OUT* MF
36 8 CPU_TT<1> TT1 MAXBUS_SLEEP 5 7 8 15 16 23 34 38
402
F6
36 8 CPU_TT<2> TT2 G9
E9 BMODE0* CPU_EMODE0_L 7 BBANG
36 8 CPU_TT<3> TT3 F8
C5 BMODE1* CPU_EMODE1_L 5 1
R86
36 8 CPU_TT<4> TT4
36 8 CPU_TBST_L F11
TBST* 470
470OHM FOR BOOT BANGER 5%
G6 1/16W
36 8 CPU_TSIZ<0> TSIZ0 A11 MF
F7 EXT_QUAL CPU_PULLDOWN 5
2 402
36 8 CPU_TSIZ<1> TSIZ1
E7
36 8 CPU_TSIZ<2> TSIZ2 39 23 5 JTAG_CPU_TRST_L
36 8 CPU_GBL_L E2 GBL* TEST0 A12 CPU_CHKS_L 5
NO_BBANG
A
36 8
36 8
CPU_WT_L
CPU_CI_L
D3
J1
WT*
CI*
TEST1
TEST2
B6
B10
CPU_PULLUP 5
1
R85
200
MPC7447 MAXBUS
36 8
36 8
CPU_AACK_L
CPU_ARTRY_L
R1
N2
AACK*
ARTRY*
TEST3
TEST4
E10
D10
CPU_SRWX_L
CPU_PULLDOWN
5
5
5%
1/16W
MF NOTICE OF PROPRIETARY PROPERTY
A
E4 2 402
5 CPU_SHD0_L SHD0* THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
H5
5 CPU_SHD1_L SHD1* PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
B2 AGREES TO THE FOLLOWING
36 8 CPU_HIT_L HIT*
GND III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

B5
C3
D6
D13
E17
F3
G17
H4
H7
H9
H11
H13
J6
J8
J10
J12
K7
K3
K9
K11
K13
L6
L8
L10
L12
M4
M7
M9
M11
M13
N7
P3
P9
P12
R5
R14
R17
T7
T10
U3
U13
U17
V5
V8
V11
V15
APPLE COMPUTER INC.

D 051-6459 A
SCALE SHT OF
NONE 5 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BOOT BANGER - LMU PERORMS THIS FUNCTION IF NEEDED

NC F18 NC_F18
OMIT
SEE PAGE 22
NC F17 NC_F17 U43
NC F19 NC_F19
NC H19 NC_H19
800MHZ
NC H18 NC_H18
BGA
(3 OF 3)
NC H17 NC_H17
APOLLO_MPC7445_360
D NC H16
NC E19
NC_H16
NC_E19
D
R15 OMIT NC D18 NC_D18
36 8 CPU_DATA<0> D0
W15 NC F16 NC_F16
36 8
36 8
CPU_DATA<1>
CPU_DATA<2> T14
D1
D2
U43 NC G16 NC_G16
36 8 CPU_DATA<3> V16 D3 800MHZ NC D19 NC_D19
W16 NC F15 NC_F15
36 8 CPU_DATA<4> D4 BGA
T15 NC G19 NC_G19
36 8 CPU_DATA<5> D5 (2 OF 3)
U15 NC E16 NC_E16
CPU_DATA<6> D6
APOLLO_MPC7445_360
36 8
P14 NC D17 NC_D17
36 8 CPU_DATA<7> D7
V13 NC D16 NC_D16
36 8 CPU_DATA<8> D8
36 8 CPU_DATA<9> W13 D9
36 8 CPU_DATA<10> T13 D10
36 8 CPU_DATA<11> P13 D11
U14 NC P15 NC_P15
36 8 CPU_DATA<12> D12
W14 NC L15 NC_L15
36 8 CPU_DATA<13> D13
36 8 CPU_DATA<14> R12 D14 NC N15 NC_N15
T12 NC P18 NC_P18
36 8 CPU_DATA<15> D15
W12 NC N14 NC_N14
36 8 CPU_DATA<16> D16
V12 NC M14 NC_M14
36 8 CPU_DATA<17> D17
N11 NC M17 NC_M17
36 8 CPU_DATA<18> D18
N10 NC N13 NC_N13
36 8 CPU_DATA<19> D19
R11 NC N16 NC_N16
36 8 CPU_DATA<20> D20
U11 NC M19 NC_M19
36 8 CPU_DATA<21> D21
W11 NC M16 NC_M16
36 8 CPU_DATA<22> D22
T11 NC P19 NC_P19
36 8 CPU_DATA<23> D23
R10 NC N17 NC_N17
CPU_DATA<24> D24
C
36 8
36 8 CPU_DATA<25> N9 D25 NC M15

NC L17
NC_M15 C
36 8 CPU_DATA<26> P10 D26 NC_L17
U10 NC L14 NC_L14
36 8 CPU_DATA<27> D27
R9 NC K15 NC_K15
36 8 CPU_DATA<28> D28
W10 NC J14 NC_J14
36 8 CPU_DATA<29> D29
U9 NC J18 NC_J18
36 8 CPU_DATA<30> D30
V9 NC J19 NC_J19
36 8 CPU_DATA<31> D31
W5 NC J15 NC_J15
36 8 CPU_DATA<32> D32
U6 NC K19 NC_K19
36 8 CPU_DATA<33> D33
T5 NC J16 NC_J16
36 8 CPU_DATA<34> D34
U5 NC H15 NC_H15
36 8 CPU_DATA<35> D35
36 8 CPU_DATA<36> W7 D36 NC L16 NC_L16
R6 NC P16 NC_P16
36 8 CPU_DATA<37> D37
P7 NC M18 NC_M18
36 8 CPU_DATA<38> D38
V6 NC L19 NC_L19
36 8 CPU_DATA<39> D39
P17 NC L18 NC_L18
36 8 CPU_DATA<40> D40
R19 NC K18 NC_K18
36 8 CPU_DATA<41> D41
V18 NC J17 NC_J17
36 8 CPU_DATA<42> D42
R18 NC K16 NC_K16
36 8 CPU_DATA<43> D43
V19 NC C19 NC_C19
36 8 CPU_DATA<44> D44
T19 NC D15 NC_D15
36 8 CPU_DATA<45> D45
U19 NC G15 NC_G15
36 8 CPU_DATA<46> D46
36 8 CPU_DATA<47> W19 D47 NC C18 NC_C18
U18 NC A16 NC_A16
36 8 CPU_DATA<48> D48
W17 NC B19 NC_B19
36 8 CPU_DATA<49> D49
W18 NC A19 NC_A19
36 8 CPU_DATA<50> D50
B 36 8
36 8
CPU_DATA<51>
CPU_DATA<52>
T16
T18
D51
D52
NC D14
NC E15
NC_D14
NC_E15
B
T17 NC B15 NC_B15
36 8 CPU_DATA<53> D53
W3 NC B17 NC_B17
36 8 CPU_DATA<54> D54
V17 NC C17 NC_C17
36 8 CPU_DATA<55> D55
U4 NC C16 NC_C16
36 8 CPU_DATA<56> D56
U8 NC G13 NC_G13
36 8 CPU_DATA<57> D57
36 8 CPU_DATA<58> U7 D58 NC E14 NC_E14
R7 NC H14 NC_H14
36 8 CPU_DATA<59> D59
P6 NC G14 NC_G14
36 8 CPU_DATA<60> D60
R8 NC C15 NC_C15
36 8 CPU_DATA<61> D61
W8 NC A17 NC_A17
36 8 CPU_DATA<62> D62
T8 NC G12 NC_G12
36 8 CPU_DATA<63> D63
NC F14 NC_F14
T3 NC F13 NC_F13
NC DP0
W4 NC E13 NC_E13
NC DP1
T4 NC B16 NC_B16
NC DP2
W9 NC A15 NC_A15
NC DP3
NC M6 DP4 NC C14 NC_C14
V3 NC A18 NC_A18
NC DP5
N8 NC A13 NC_A13
NC DP6
W6 NC F12 NC_F12
NC DP7
NC A14 NC_A14
NC G11 NC_G11
NC C13 NC_C13
MPC7447/BBANG
A NC N12
NC N18
NC_N12
NC_N18 NOTICE OF PROPRIETARY PROPERTY
A
NC K17 NC_K17 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
NC N19 NC_N19 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
NC B18 NC_B18
NC E12 NC_E12 II NOT TO REPRODUCE OR COPY IT
NC B13 NC_B13 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
NC B14 NC_B14
NC A6 NC_A6 SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.

D 051-6459 A
SCALE SHT OF
NONE
6 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU FREQUENCY CONFIGURATION

CPU PLL CONFIG CIRCUITRY
38 34 23 16 15 8 7 5 MAXBUS_SLEEP APOLLO 7
CORE FREQUENCY
1
R9 1
R10 1
R11 1
R12 1
R2
NO STUFF
MULTIPLIER (AT BUS FREQUENCY) CPU_PLL_CFG
10K
5% 5%
10K
5%
10K 10K
5%
10K
5%
167MHZ 133MHZ
1/16W 1/16W 1/16W 1/16W 1/16W 4 0123
D MF
2 402
MF
2 402
MF
2 402
MF
2 402
MF
2 402 (Bus-to-Core) (MHZ) E ABCD HEX D
CPU_PLL_CFG<0>
CPU_PLL_CFG<1>
5
5
0.0X PLL OFF 0 1111 0F
CPU_PLL_CFG<2>
CPU_PLL_CFG<3>
5
5
1.0X PLL BYPASS 0 0011 03
1
CPU_PLL_CFGEXT CPU_PLL_CFG<4> 5
2.0X 333 267 0 0100 04
S
+5V_SLEEP NOW REQUIRED FOR PLL_STOP_L R01A R00A R10A R01B R00B R10B R01C R00C R10C R01D R00D R10D R01E R10E NO STUFF R00E 3.0X 500 400 0 1000 08
G
PULLUP TO ENSURE THAT Vgs OF PASS
TRANSISTOR ON CPU_PLL_CFG<4> IS MET. NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF Q1
2N7002DW
2
1
1
R19 1
R20 1
R21 1
R22 1
R23 1
R24 1
R25 1
R26 1
R13 1
R14 1
R15 1
R16 1
R17 1
R18 SOT-363 R27 4.0X 667 533 0 1010 0A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+3V_SLEEP +5V_SLEEP 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
MF MF MF MF MF MF MF MF MF MF MF MF MF MF
STUFF PASS TRANSISTOR ONLY IF
MF
2 402
5.0X 833 667 0 1011 0B
2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402
R10E, R01E, OR PULLUP STUFFED
CPU_PLL_FS01
5.5X 917 733 0 1001 09
R31 R331 1
R48
47K
5%
82K
5%
10K
5% 3 6.0X 1000 800 0 1101 0D
1/16W 1/16W 1/16W 7 PLL_STOP_L 3
MF MF MF D
402 2 402 2 2 402
NO STUFF 6.5X 1083 867 0 0101 05
D Q1
1 G S 2N7002DW
30 7 CPU_PLL_STOP_OC
5 G S
SOT-363 7.0X 1167 933 0 0010 02
Q3 2
2N7002
SM CPU_PLL_FS00
4 7.5X 1250 1000 0 0001 01
6 8.0X 1333 1067 0 1100 0C
D
Q2 8.5X 1417 1133 0 0110 06
C 7 PLL_STOP_L
2 G S
2N7002DW
SOT-363
C
Q2 9.0X 1500 1200 1 0111 17
2N7002DW 3 1
SOT-363
D CPU_PLL_FS10
9.5X 1583 1267 0 0111 07
30 7 CPU_PLL_STOP_OC 5 G S CPU_PLL_STOP_BASE
10.0X 1667 1333 1 1010 1A
3
4 R47 10.5X 1750 1400 1 1000 18
249K 2
1 1 Q4 STATE ENCODING CPU_PLL_STOP_OC CPU_VCORE_HI_OC
1% 2N3904 11.0X 1833 1467 1 1001 19
1/16W SM
MF
402
2 LOW SPEED 0 0
HIGH SPEED 0 1 11.5X 1917 1533 0 0000 00
PLL DISABLE 1 X 12.0X 2000 1600 1 1011 1B
CPU_VCORE_HI_OC
34 30
12.5X 2083 1667 1 1111 1F
13.0X 2167 1733 1 0101 15
CPU CONFIGURATION 13.5X

14.0X
2250
2333
1800
1867
0
1
1110 0E
1100 1C
15.0X 2500 2000 1 0001 11
16.0X 2667 2133 1 1101 1D
B B
17.0X 2833 2267 1 0000 10
MAXBUS VSEL 18.0X 3000 2400 1 0010 12
INVERTED HRESET_L
20.0X 3333 2667 1 0011 13
38 34 23 16 15 8 7 5 MAXBUS_SLEEP
BUSTYPE SELECT 21.0X 3500 2800 1 0100 14
CRITICAL 1.5V INTERFACE 24.0X 4000 3200 1 0110 16
1_5V_MAXBUS
1_5V_MAXBUS R149
U1 1
22 2
28.0X 4667 3733 1 1110 1E
5
SN74AUC1G04
R4 39 23 7 5 CPU_HRESET_L CPU_EMODE0_L 5
2 4 1
22 2
5%
39 23 7 5 CPU_HRESET_L CPU_HRESET_INV CPU_BUS_VSEL 5 1/16W
04 MF
SC70-5 5% 402
3 1/16W
MF
402 1_8V_MAXBUS
APOLLO ONLY SUPPORTS MAXBUS
R51
10
5% 1.8V INTERFACE
1/16W
MF
402 2
CPU CONFIGURATION
A DESKTOP HAD PROBLEM USING NOTICE OF PROPRIETARY PROPERTY
A
SIGNAL TIED APPLICATION
INVERTER TO INVERT HRESET_L THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
CPU_EMODE0_L HIGH 60X BUS MODE PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
NEED TO CHARACTERIZE (PROCESSOR) AGREES TO THE FOLLOWING
CPU_HRESET_L MAX BUS MODE I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
CPU_HRESET_L 2.5V INTERFACE II NOT TO REPRODUCE OR COPY IT
CPU_BUS_VSEL III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

LOW 1.8V INTERFACE
(PROCESSOR) SIZE DRAWING NUMBER REV.
CPU_HRESET_INV 1.5V INTERFACE
APPLE COMPUTER INC.
D 051-6459 A
SCALE SHT OF
NONE 7 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE FOLLOWING STRAP BITS CAN BE
CHANGED BY SOFTWARE:
INTREPID BOOT STRAPS R227
4.7
1/
2/
3/
D47 - SELAGPSPREADCLK - SLEEP/WAKE CYCLE REQUIRED
D46 - SELPCI1SPREADCLK - SLEEP/WAKE CYCLE REQUIRED
D44 - PLL4MODESEL_NXT<0> - SLEEP/WAKE CYCLE REQUIRED
38 14 12 +1_5V_INTREPID_PLL 1 2 38 +1_5V_INTREPID_PLL7
4/ D43 - PLL4MODESEL_NXT<1> - SLEEP/WAKE CYCLE REQUIRED
MAXBUS_SLEEP 5% 5/ D42 - PLL4MODESEL_NXT<2> - SLEEP/WAKE CYCLE REQUIRED
38 34 23 16 15 8 7 5
BIT 32 TO 39 C308 1
1/16W
MF 6/ D33 - ANALYZERCLK_EN_H - IMMEDIATE EFFECT MAXBUS PULL-UPS MAXBUS_SLEEP 5 7 8 15 16 23 34 38
402
0.22UF IF A STRAP IS NOT LISTED, THEN
20%
6.3V
NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF CERM 2 H26 IT CANNOT BE CHANGED BY SOFTWARE RP21
402
VDD15A_7 10K
R6421 R1351 R1231 R1531 R1661 R1791 R6511 R1781 (PLL6) 36 8 5 CPU_TS_L 2 7
10K 10K 10K 10K 10K 10K 10K 10K 5%

RP21
5% 5% 5% 5% 5% 5% 5% 5% CRITICAL 1/16W
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W D10 SM1 10K
D MF
402 2
MF
402 2
MF
402 2
MF
402 2
MF
402 2
MF
402 2
MF
402 2
MF
402 2
36 8 5 CPU_BR_L
E29
U45 D_0
D_1 G12
CPU_DATA<0>
CPU_DATA<1>
6 36
6 36
36 8 5 CPU_TA_L 1 8
D
6 CPU_DATA<32> E26
BR INPUT
INTREPID-REV2.1 D_2 E11 CPU_DATA<2> 6 36 RP21 5%
1/16W
36 8
36 8 5 CPU_BG_L BG NO BUS KEEPER BGA H11 CPU_DATA<3>
10K SM1
36 8 6 CPU_DATA<33> D_3 6 36
36 8 5 CPU_ARTRY_L 4 5
D_4 B9 CPU_DATA<4> 6 36
36 8 6 CPU_DATA<34>
D_5 B8 CPU_DATA<5> 6 36
5%
1/16W RP23
36 8 6 CPU_DATA<35>
36 8 5 CPU_TS_L
B27 TS NO BUS KEEPER SM1 10K
A9 CPU_DATA<6> CPU_BR_L 1 8
36 8 6 CPU_DATA<36> (1 OF 9)
D_6 6 36 36 8 5
36 5 CPU_ADDR<0>
D24 A_0 D_7 A8 CPU_DATA<7> 6 36 5%
36 8 6 CPU_DATA<37>
36 5 CPU_ADDR<1>
D25
A_1 D_8 E12 CPU_DATA<8> 6 36
RP24 1/16W
SM1
36 8 6 CPU_DATA<38> 10K
36 5 CPU_ADDR<2>
A27 D11 CPU_DATA<9> 36 8 5 CPU_HIT_L
3 6
36 8 6 CPU_DATA<39> A_2 D_9 6 36
36 5 CPU_ADDR<3>
E24 B10 CPU_DATA<10>
A_3 D_10 6 36 5%
RP23
G23 J13 1/16W
R1361 R6431 R6391 R6571 R6641 R6731 R1431 R6741 36 5 CPU_ADDR<4> A_4 D_11 CPU_DATA<11> 6 36 SM1 10K
B26 A10 36 8 5 CPU_DRDY_L
3 6
10K 10K 10K 10K 10K 10K 10K 10K 36 5 CPU_ADDR<5> A_5 D_12 CPU_DATA<12> 6 36
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W 36 5 CPU_ADDR<6>
A26
A_6 D_13 D12 CPU_DATA<13> 6 36 RP23 5%
1/16W
MF
402 2
MF
402 2
MF
402 2
MF
402 2
MF
402 2
MF
402 2
MF
402 2
MF
402 2 36 5 CPU_ADDR<7>
D23
A_7 D_14 E13 CPU_DATA<14> 6 36
4
10K 5
SM1
36 8 5 CPU_TEA_L
36 5 CPU_ADDR<8>
A25 A_8 D_15 G13 CPU_DATA<15> 6 36
36 5 CPU_ADDR<9>
E23
A_9 D_16 B11 CPU_DATA<16> 6 36
5%
1/16W RP23
10K
1: TDI output
0: TDI input (JTAG)
DDR_TPDModeEnable_h
SM1
1: Active
0: Inactive
AnalyzerClk_En_h
1: Active low
0: Active high
DDR_TPDEn_Pol
1: Active low
0: Active high
ExtPLL_SDwn_Pol
Spare
Spare
Spare
Spare
36 5 CPU_ADDR<10>
J22 D13 CPU_DATA<17>
A_10 D_17 6 36
36 8 5 CPU_AACK_L 2 7
36 5 CPU_ADDR<11>
B25 A_11 D_18 A11 CPU_DATA<18> 6 36
5%
36 5 CPU_ADDR<12>
H22
A_12
MAXBUS
D_19 G14 CPU_DATA<19> 6 36 RP24 1/16W
SM1
36 5 CPU_ADDR<13>
G22 INTERFACE H14 CPU_DATA<20>
10K
A_13 D_20 6 36
36 8 5 CPU_DBG_L 4 5
36 5 CPU_ADDR<14>
D22 E14 CPU_DATA<21>
A_14 D_21 6 36
5%
36 5 CPU_ADDR<15>
B24
A_15 D_22 B12 CPU_DATA<22> 6 36
1/16W
SM1
RP21
36 5 CPU_ADDR<16>
B23 G15 CPU_DATA<23>
10K
A_16 D_23 6 36
36 8 5 CPU_BG_L 3 6
36 5 CPU_ADDR<17>
E22 B13 CPU_DATA<24>
A_17 D_24 6 36
5%
38 34 23 16 15 8 7 5 MAXBUS_SLEEP
BIT 40 TO 47 36 5 CPU_ADDR<18>
J21
A_18 D_25 H15 CPU_DATA<25> 6 36 RP24 1/16W
SM1
36 5 CPU_ADDR<19>
G21 D14 CPU_DATA<26>
10K
A_19 D_26 6 36
36 8 5 CPU_QREQ_L 2 7
C NO STUFF
1
NO STUFF NO STUFF SSCG NO STUFF NO_SSCG NO_SSCG NO_SSCG
36 5 CPU_ADDR<20>
36 5 CPU_ADDR<21>
E21
A24
A_20
A_21
D_27
D_28
B14
A12
CPU_DATA<27>
CPU_DATA<28>
6 36
5%
1/16W
C
R122 R142 R164 R1341 R184 R177 R1521 R1651
1 1 1 1
36 5 CPU_ADDR<22>
D21 A_22 D_29 G16 CPU_DATA<29>
6 36
SM1
10K 10K 10K 10K 10K 10K 10K 10K 6 36
5% 5% 5% 5% 5% 5% 5% 5% 36 5 CPU_ADDR<23>
A23 E15 CPU_DATA<30>
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W A_23 D_30 6 36
MF MF MF MF MF MF MF MF 36 5 CPU_ADDR<24>
H20 J16 CPU_DATA<31>
402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 A_24 D_31 6 36
36 5 CPU_ADDR<25>
B22 D15 CPU_DATA<32>
A_25 D_32 6 8 36
36 8 6 CPU_DATA<40> H21 A14
36 5 CPU_ADDR<26> A_26 D_33 CPU_DATA<33> 6 8 36
36 8 6 CPU_DATA<41> A22 A13
36 8 6 CPU_DATA<42> E20 D16
CPU_DATA<43> B21 E16
36 8 6
36 8 6
36 8 6
CPU_DATA<44>
CPU_DATA<45>
36 5 CPU_ADDR<29>
36 5 CPU_ADDR<30>
D20
A21
A_29
A_30
D_36
D_37 G17
B15
CPU_DATA<36>
CPU_DATA<37>
6 8 36
6 8 36
38 34 23 16 15 8 7 5 MAXBUS_SLEEP
INTREPID BOOT STRAPS
36 8 6 CPU_DATA<46>
36 5 CPU_CI_L
G26
CI
D_39 H17 CPU_DATA<39> 6 8 36 BIT 56 TO 63
36 8 6 CPU_DATA<47> A15 CPU_DATA<40>
A29 D_40 6 8 36
36 5 CPU_GBL_L GBL
NO_SSCG SSCG SSCG SSCG B16 CPU_DATA<41>
A28 D_41 6 8 36
NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF
36 5 CPU_TBST_L TBST
R6401 R6521 R6651 R644 R6831 R6751 R658 R666 1 1 1
36 5 CPU_TSIZ<0>
G24
TSIZ_0
D_42 E17 CPU_DATA<42> 6 8 36
R1401 R1611 R1751 R1321 R1311 R1501 R1741 R1821
10K 10K 10K 10K 10K 10K 10K 10K D_43 A16 CPU_DATA<43>
5% 5% 5% 5% 5% 5% 5% 5% 36 5 CPU_TSIZ<1>
H24
TSIZ_1
6 8 36 10K 10K 10K 10K 10K 10K 10K 10K
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W J18 CPU_DATA<44> 5% 5% 5% 5% 5% 5% 5% 5%
MF MF MF MF MF MF MF MF D26 D_44 6 8 36
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
36 5 CPU_TSIZ<2> TSIZ_2
402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 H18 CPU_DATA<45> MF MF MF MF MF MF MF MF
E25 D_45 6 8 36
402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2
36 5 CPU_TT<0> TT_0 D17 CPU_DATA<46>
G25 D_46 6 8 36
36 5 CPU_TT<1> TT_1 G18 CPU_DATA<47> 36 8 6 CPU_DATA<56>
BIT2 BIT1 BIT0 D_47 6 8 36
Spare
Spare
1: Active
0: Inactive
InternalSpreadEn
0: PLL5 (NO SPREAD)

1: PLL4
PCI1 Source Clock
0: PLL5 (NO SPREAD)

1: PLL4
PCI0 Source Clock
36 5 CPU_TT<2>
B28
TT_2 A17 CPU_DATA<48> 36 8 6 CPU_DATA<57>
D27 D_48 6 8 36
36 5 CPU_TT<3> TT_3
PLL4MODESEL_NXT[2:0] B17 CPU_DATA<49> 36 8 6 CPU_DATA<58>
J25 D_49 6 8 36
000: 166.4MHZ (2.5X) 36 5 CPU_TT<4> TT_4 E18 CPU_DATA<50> 36 8 6 CPU_DATA<59>
001: 149.76MHZ D28 D_50 6 8 36
36 5 CPU_WT_L WT B18 CPU_DATA<51> 36 8 6 CPU_DATA<60>
010: 133.12MHZ (2.0X) D_51 6 8 36
011: 99.84MHZ (1.5X) B29 D18 36 8 6 CPU_DATA<61>
36 8 5 CPU_AACK_L AACK NO BUS KEEPER - PU D_52 CPU_DATA<52> 6 8 36
100: 83.20MHZ H23 A18 36 8 6 CPU_DATA<62>
B MODE A (2.5X) IS FOR STATIC OPERATION

MODE C (2.0X) IS FOR CLOCK SLEW OPERATION
36 8 5 CPU_ARTRY_L
36 8 5 CPU_HIT_L
B31
ARTRY
HIT
NO BUS KEEPER - PU
INPUT - PU
D_53
D_54 A19
CPU_DATA<53>
CPU_DATA<54>
6 8 36
6 8 36
36 8 6 CPU_DATA<63> B
H19 CPU_DATA<55> NO STUFF
D_55 6 8 36
1 1 1 1 1 1 1 1
36 8 5 CPU_QREQ_L
A32 D_56 B19 CPU_DATA<56> 6 8 36 R654 R669 R677 R646 R647 R660 R678 R685
QREQ INPUT - PD J19 CPU_DATA<57> 10K 10K 10K 10K 10K 10K 10K 10K
38 34 23 16 15 8 7 5 MAXBUS_SLEEP D_57 6 8 36
5% 5% 5% 5% 5% 5% 5% 5%
A20 CPU_DATA<58> 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
D_58
BIT 48 TO 55 36 5 CPU_QACK_L
G27
QACK NO BUS KEEPER - ?
D_59 D19 CPU_DATA<59>
6 8 36
6 8 36
MF
402 2
MF
402 2
MF
402 2
MF
402 2
MF
402 2
MF
402 2
MF
402 2
MF
402 2
30 INT_SUSPEND_REQ_L
AK9
SUSPENDREQ E19 CPU_DATA<60>
AM8 D_60 6 8 36
SSCG SSCG NO STUFF NO STUFF NO STUFF NO STUFF 30 INT_SUSPEND_ACK_L SUSPENDACK G19
1: GPIOs
0: REQ/GNT
PCI1_REQ2_L / PCI1_GNT2_L
1: GPIOs
0: REQ/GNT
1: GPIOs
0: REQ/GNT
D_61 CPU_DATA<61> 6 8 36
Spare
Spare
Spare
1: B-mode interface
0: Legacy interface
FireWire PHY interface
1: 60x bus (G3)

0: Max Bus (G4)
Processor Bus Mode
R133 R1211 R1631 R151 R162 R141 R1831 R176
1 1 1 1 1
FB BUFFER HAS 50 OHM OUTPUT IMPEDANCE Vin = Intrepid Vcore (1.5V) D_62 B20 CPU_DATA<62> 6 8 36
10K 10K 10K 10K 10K 10K 10K 10K G20 CPU_DATA<63>
5% 5% 5% 5% 5% 5% 5% 5%
36 8 INT_CPUFB_IN J24 Vout = MaxBus rail (1.8V) D_63 6 8 36
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W CPU_FB_IN
MF MF MF MF MF MF MF MF H16 A30
402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 36 8 INT_CPUFB_OUT CPU_FB_OUT DBG CPU_DBG_L
R1971 SYSCLK_LA_TP G8
NO BUS KEEPER - PU 5 8 36
511 ANALYZER_CLK
36 8 6 CPU_DATA<48>
1% G28 CPU_DRDY_L
1/16W INPUT - PU DRDY 5 8 36
36 8 6 CPU_DATA<49>
MF 30 CPU_CLK_EN
AH9
402 2 STOPCPUCLK
36 8 6 CPU_DATA<50>
K25 CPU_DTI<0>
NO BUS KEEPER - ? DTI_0 5 36
36 8 6 CPU_DATA<51>
INTREPID_ACS_REF H13 D29 CPU_DTI<1>
ACS_REF NO BUS KEEPER - ? DTI_1 5 36
36 8 6 CPU_DATA<52>
R144 NO BUS KEEPER - ? DTI_2 B30 CPU_DTI<2> 5 36
36 8 6 CPU_DATA<53>
1
0 2 J15
36 5 SYSCLK_CPU 36 SYSCLK_CPU_UF CPU_CLK
36 8 6 CPU_DATA<54>
NO BUS KEEPER - PU E27 CPU_TA_L
5%
TA 5 8 36
36 8 6 CPU_DATA<55> 1/16W NO BUS KEEPER - PU TEA E28 CPU_TEA_L 5 8 36

MF INTREPID OUTPUTS HIGH BY DEFAULT
NO_SSCG NO_SSCG NO STUFF NO STUFF 402
5 CPU_TBEN
A31 VSSA_7
1 1 1 1 1 1 1 1 1 TBEN
R645 R641 R668 R659 R667 R653 R684 R676 R137 NO BUS KEEPER - PU (PLL6)
10K 10K 10K 10K 10K 10K 10K 10K 1K H25
5% 5% 5% 5% 5% 5% 5% 5% 1%
1/16W
MF
402 2
1/16W
MF
402 2
1/16W
MF
402 2
1/16W
MF
402 2
1/16W
MF
402 2
1/16W
MF
402 2
1/16W
MF
402 2
1/16W
MF
402 2
1/16W
MF
402 2 Intrepid MaxBus
A SHORT = 1" SHORTER THAN MATCHED LENGTH
LONG = 1" LONGER THAN MATCHED LENGTH
NO STUFF NOTICE OF PROPRIETARY PROPERTY
A
1: Active
0: Inactive
BUF_REF_CLK_OUTEnable_h
1: External source
0: PLL5
SelPLL4ExtSrc
Spare
1: TI PHY workaround
0: Normal 1394b
TI 1394b workaround
Spare
BIT2 BIT1 BIT0

R167 R215 R207 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
MaxBus output impedance 2
0 1 1
0 2 1
0 2 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
36 8 INT_CPUFB_OUT 36 INT_CPUFB_OUT_SHORT 36 INT_CPUFB_OUT_NORM 36 INT_CPUFB_LONG
111: 28.6 ohm 5% 5% 5%
1/16W 1/16W 1/16W I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
011: 33.3 ohm MF NO STUFF MF MF
101: 40 ohm
402
R2251 402 R2081 402 II NOT TO REPRODUCE OR COPY IT
0 0 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

001: 50 ohm 5% 5% NO STUFF
1/16W 1/16W
110: 66.6 ohm MF SIZE DRAWING NUMBER REV.
MF R226 402 2 R196
010: 100 ohm
100: 200 ohm 36 8 INT_CPUFB_IN
402 2
1
0 2 36 INT_CPUFB_IN_NORM 1
0 2
APPLE COMPUTER INC.
D 051-6459 A
5% 5%
000: 200 ohm SCALE SHT OF
1/16W
MF
402
1/16W
MF
402 NONE 8 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SERIES RESISTORS FOR CLOCK/CONTROL SIGNALS RP33
4
22 5
36 9 SYSCLK_DDRCLK_A1_UF SYSCLK_DDRCLK_A1 11 36
RP33 5%
1/16W
22
PINS ARE SWAPABLE FOR RPAKS 36 9 SYSCLK_DDRCLK_A1_L_UF
3 6
SM1
SYSCLK_DDRCLK_A1_L 11 36
5%
1/16W RP34
DDR_A_0 H35 MEM_ADDR<0> 9 36

36 9 SYSCLK_DDRCLK_A0_UF
SM1
RP34
1
22
5%
8 SYSCLK_DDRCLK_A0 11 36
1MB BOOT ROM
CLOCKS
MEM_DATA<0> AK32 1/16W
36 10 DDR_DATA_0 G35 SM1
MEM_DATA<1> AK33 DDR_A_1 MEM_ADDR<1> 9 36 22
36 10 DDR_DATA_1 2 7
D 36 10 MEM_DATA<2> AK31 DDR_DATA_2

CRITICAL
DDR_A_2 G36
F36
MEM_ADDR<2>
MEM_ADDR<3>
9 36
36 9 SYSCLK_DDRCLK_A0_L_UF
5%
SYSCLK_DDRCLK_A0_L 11 36
+3V_MAIN D
36 10 MEM_DATA<3> AK35
DDR_DATA_3 U45 DDR_A_3
F35 MEM_ADDR<4>
9 36
1/16W
SM1 RP33
DDR_DATA_4INTREPID-REV2.1
MEM_DATA<4> AK36 DDR_A_4 9 36
22
36 10
BGA E35 MEM_ADDR<5> 36 9 SYSCLK_DDRCLK_B1_UF
2 7 SYSCLK_DDRCLK_B1
MEM_DATA<5> AJ32 DDR_A_5 9 36 11 36
36 10 DDR_DATA_5 (2 OF 9) E36 MEM_ADDR<6>
36 10 MEM_DATA<6> AJ35
DDR_DATA_6
DDR_A_6
G32
9 36
RP33 5%
1/16W
DDR_A_7 MEM_ADDR<7> 22 SM1
36 10 MEM_DATA<7> AJ36
DDR_DATA_7
DDR_A_8 D36 MEM_ADDR<8>
9 36
36 9 SYSCLK_DDRCLK_B1_L_UF
1 8 SYSCLK_DDRCLK_B1_L 11 36
1 C460 1 C470 1 C479
36 10 MEM_DATA<8> AG33
DDR_DATA_8
9 36
2.2UF 0.1UF 0.1UF
H36 MEM_ADDR<9> 5% 20% 20% 20%
36 10 MEM_DATA<9> AG35
DDR_DATA_9
DDR_A_9
G33
9 36
1/16W
SM1
RP34 10V
2 CERM 2 10V
CERM
10V
2 CERM
MEM_DATA<10> AH35 DDR_A_10 MEM_ADDR<10> 9 36 22 805 402 402
36 10 DDR_DATA_10 H33 MEM_ADDR<11> 36 9 SYSCLK_DDRCLK_B0_UF
3 6 SYSCLK_DDRCLK_B0 11 36
MEM_DATA<11> AG36 DDR_A_11 9 36
36 10 DDR_DATA_11 D35 MEM_ADDR<12> 5%
MEM_DATA<12> AH36 DDR_A_12 9 36
RP34 1/16W
36 10 DDR_DATA_12 L30 SM1
MEM_DATA<13> AH32 DDR_BA_0 MEM_BA<0> 9 36 22
36 10 DDR_DATA_13 M29 MEM_BA<1> 36 9 SYSCLK_DDRCLK_B0_L_UF
4 5 SYSCLK_DDRCLK_B0_L 11 36
MEM_DATA<14> AG32 DDR_BA_1 9 36
36 10 DDR_DATA_14
36 10 MEM_DATA<15> AG31
DDR_DATA_15 DDRCS_0 AN34 MEM_CS_L<0> 9 36
5%
1/16W RP36
AE32 AN36
SM1
1
22 8 11 30 31
36 10 MEM_DATA<16> DDR_DATA_16 DDRCS_1 MEM_CS_L<1> 9 36 ’0’ & ’1’ GO TO SLOT A 36 9 MEM_CS_L<0> RAM_CS_L<0> 11 36
AF35 AL35 ’2’ & ’3’ GO TO SLOT B
36 10 MEM_DATA<17> DDR_DATA_17 DDRCS_2 MEM_CS_L<2> 9 36
RP36 5% VPP VCC
1/16W
36 10 MEM_DATA<18> AF36
DDR_DATA_18 DDRCS_3 AL33 MEM_CS_L<3> 9 36 22 SM1 U17
MEM_DATA<19> AE36 36 9 MEM_CS_L<1>
3 6 RAM_CS_L<1> 11 36 FEPR-1MX8
36 10 DDR_DATA_19 DDR AJ31 3.3V
MEMORY DDR_DQS_0 MEM_DQS<0> 21 25
CS
10 36
AE35 5% 39 37 26 24 17 12 PCI_AD<0> PCI_AD<24> 12 17 24 26 37 39
36 10 MEM_DATA<20> DDR_DATA_20 INTERFACE AH31 MEM_DQS<1> 1/16W RP35 A0 TSOP DQ0
AE33 DDR_DQS_1 10 36
SM1 39 37 26 24 17 12 PCI_AD<1>
20 26 PCI_AD<25>
36 10 MEM_DATA<21> DDR_DATA_21 AD32 MEM_DQS<2>
22 A1 OMIT DQ1 12 17 24 26 37 39
AD36 DDR_DQS_2 10 36
36 9 MEM_CS_L<2>
4 5 RAM_CS_L<2> 11 36 39 37 26 24 17 12 PCI_AD<2> 19 27 PCI_AD<26> 12 17 24 26 37 39
36 10 MEM_DATA<22> DDR_DATA_22 AB30 MEM_DQS<3>
A2 DQ2
AD35 DDR_DQS_3 10 36
5% 39 37 26 24 17 12 PCI_AD<3>
18 28 PCI_AD<27> 12 17 24 26 37 39
36 10 MEM_DATA<23> DDR_DATA_23 V30 MEM_DQS<4> RP35 1/16W A3 DQ3
AA36 DDR_DQS_4 10 36
SM1 39 37 26 24 17 12 PCI_AD<4> 17 32 PCI_AD<28>
36 10 MEM_DATA<24> DDR_DATA_24 P32 MEM_DQS<5>
22 A4 DQ4 12 17 24 26 37 39
36 9 MEM_CS_L<3>
2 7 RAM_CS_L<3> 11 36 39 37 26 24 17 12 PCI_AD<5> 16 33 PCI_AD<29> 12 17 24 26 37 39
36 10 MEM_DATA<25> DDR_DATA_25 N29 MEM_DQS<6>
A5 DQ5
5% 39 37 26 24 17 12 PCI_AD<6> 15 34 PCI_AD<30> 12 17 24 26 37 39
36 10 MEM_DATA<26> DDR_DATA_26 A6 DQ6
MEM_DATA<27> AB36
DDR_DATA_27
DDR_DQS_7 L32 MEM_DQS<7> 10 36
1/16W
SM1 RP36 39 37 26 24 17 12 PCI_AD<7> 14
A7 DQ7
35 PCI_AD<31> 12 17 24 26 37 39
36 10
22 8
AB35 AJ33 2 7 39 37 26 24 17 12 PCI_AD<8>
C 36 10
36 10
MEM_DATA<28>
MEM_DATA<29> AC36
DDR_DATA_28
DDR_DATA_29
DDR_DM_0
DDR_DM_1 AH33
MEM_DQM<0>
MEM_DQM<1>
10 36
10 36
36 9 MEM_CKE<0>
RP36 5%
1/16W
RAM_CKE<0> 9 11 36
39 37 26 24 17 12 PCI_AD<9>
7
A8
A9
C
AA32 AD33 39 37 26 24 17 12 PCI_AD<10> 36
36 10 MEM_DATA<30> DDR_DATA_30 DDR_DM_2 MEM_DQM<2> 10 36 22 SM1 A10
AB33 AC35 36 9 MEM_CKE<1>
4 5 RAM_CKE<1> 9 11 36 39 37 26 24 17 12 PCI_AD<11> 6
36 10 MEM_DATA<31> DDR_DATA_31 DDR_DM_3 MEM_DQM<3> 10 36 A11
CKE
+3V_MAIN 5
V36 T35 5% 39 37 26 24 17 12 PCI_AD<12>
36 10 MEM_DATA<32> DDR_DATA_32 DDR_DM_4 MEM_DQM<4> 10 36
1/16W RP35 A12
U33 T33 SM1 39 37 26 24 17 12 PCI_AD<13> 4
1
22 8
A13
U32 N32 36 9 MEM_CKE<2> RAM_CKE<2> 9 11 36 39 37 26 24 17 12 PCI_AD<14>
3
36 10 MEM_DATA<34> DDR_DATA_34 DDR_DM_6 MEM_DQM<6> 10 36 A14
V35 L33 5% 39 37 26 24 17 12 PCI_AD<15> 2
RP35 1/16W A15
T30 39 37 26 24 17 12 PCI_AD<16> 1
36 10 MEM_DATA<36>
U36
DDR_DATA_36
DDRRAS L29 MEM_RAS_L 9 36
36 9 MEM_CKE<3>
3
22
6
SM1
RAM_CKE<3>
R3381 R3861 39 37 26 24 17 12 PCI_AD<17>
40
A16
36 10 MEM_DATA<37> DDR_DATA_37 H32 MEM_CAS_L
9 11 36 10K 10K A17
U35 DDRCAS 9 36
5% 5% 5% 39 37 26 24 17 12 PCI_AD<18> 13
36 10 MEM_DATA<38> DDR_DATA_38 K30 MEM_WE_L 1/16W 1/16W 1/16W A18
36 10 MEM_DATA<39> T36
DDR_DATA_39
DDRWE
AN35
9 36
SM1 RP31 MF
402 2
MF
402 2 39 37 26 24 17 12 PCI_AD<19> 37
A19
P33 DDRCKE0 MEM_CKE<0> 9 36 22 39 37 26 24 17 12 PCI_AD<20>
38
36 10 MEM_DATA<40> DDR_DATA_40 AM35 MEM_CKE<1> 36 9 MEM_ADDR<0>
1 8 RAM_ADDR<0> 11 36
R357 A20
MEM_DATA<41> R30 DDRCKE1 9 36 ’0’ & ’1’ GO TO SLOT A
36 10 DDR_DATA_41 1K
36 10 MEM_DATA<42> P35
DDR_DATA_42
DDRCKE2 AM36 MEM_CKE<2> 9 36
’2’ & ’3’ GO TO SLOT B
RP25 5%
1/16W 39 24 12 ROM_CS_L 1 2 39 24 ROM_ONBOARD_CS_L 22
CE
DDRCKE3 AL36 MEM_CKE<3> 9 36 22 SM1
5% 24
P36 1 8 39 24 12 ROM_OE_L
36 10 MEM_DATA<43> DDR_DATA_43 36 9 MEM_ADDR<1> RAM_ADDR<1> 11 36 1/16W OE
R36 AB32 MF 39 24 12 ROM_RW_L 9
36 10 MEM_DATA<44> DDR_DATA_44 DDR_SELHI_0 MEM_MUXSEL_H<0> 10 36 5% 402 WE
36 10 MEM_DATA<45> R35
DDR_DATA_45 DDR_SELHI_1 AE29 MEM_MUXSEL_H<1> 10 36 ’0’S ARE SAME POLARITY (ACTIVE-LO)
1/16W
SM1
RP25 ROM_WP_L 12
WP
22 10
R33 N30 ’1’S ARE SAME POLARITY (ACTIVE-HI) 2 7 30 13 INT_RESET_L
36 10 MEM_DATA<46> DDR_DATA_46 DDR_SELLO_0 MEM_MUXSEL_L<0> 10 36 36 9 MEM_ADDR<2> RAM_ADDR<2> 11 36 PWD
36 10 MEM_DATA<47> R32
DDR_DATA_47 DDR_SELLO_1 T32 MEM_MUXSEL_L<1> 10 36 5% GND
36 10 MEM_DATA<48> N35
DDR_DATA_48
RP25 1/16W
SM1
OVERRIDE ROM MODULE
INTERCEPTS ROM CHIP SELECT
M36 DDR_MCLK_0_P Y32 SYSCLK_DDRCLK_A0_UF 9 36
4
22 5 23 39
36 10 MEM_DATA<49> DDR_DATA_49 36 9 MEM_ADDR<3> RAM_ADDR<3> 11 36
Y33 SYSCLK_DDRCLK_A0_L_UF
MEM_DATA<50> L35 DDR_MCLK_0_N 9 36
36 10 DDR_DATA_50 Y35 SYSCLK_DDRCLK_A1_UF
5%
MEM_DATA<51> M35 DDR_MCLK_1_P 9 36 1/16W
RP25
36 10 DDR_DATA_51 Y36 SM1
MEM_DATA<52> M33 DDR_MCLK_1_N SYSCLK_DDRCLK_A1_L_UF 9 36 22
36 10 DDR_DATA_52 Y30 INT_DDRCLK2_P_TP 36 9 MEM_ADDR<4>
3 6 RAM_ADDR<4> 11 36
MEM_DATA<53> L36 DDR_MCLK_2_P
36 10 DDR_DATA_53
MEM_DATA<54> N33 DDR_DATA_54
DDR_MCLK_2_N W30 INT_DDRCLK2_N_TP RP30 5%
1/16W
36 10
22
B 36 10 MEM_DATA<55> M30
J32
DDR_DATA_55
DDR_MCLK_3_P
DDR_MCLK_3_N
W32
W33
SYSCLK_DDRCLK_B0_UF
SYSCLK_DDRCLK_B0_L_UF
9 36
9 36
36 9 MEM_ADDR<5>
1 8
SM1
RAM_ADDR<5> 11 36
TABLE_5_HEAD
B
36 10 MEM_DATA<56> DDR_DATA_56 5%
MEM_DATA<57> J33 DDR_DATA_57
DDR_MCLK_4_P V33 SYSCLK_DDRCLK_B1_UF 9 36 1/16W
SM1
RP30 341S1255 1 BOOTROM,P84 U17 CRITICAL ?
TABLE_5_ITEM
36 10
J35 DDR_MCLK_4_N V32 SYSCLK_DDRCLK_B1_L_UF 9 36 22
2 7
ADDR
36 10 MEM_DATA<58> DDR_DATA_58 36 9 MEM_ADDR<6> RAM_ADDR<6> 11 36

W35 INT_DDRCLK5_P_TP
MEM_DATA<59> K32 DDR_MCLK_5_P
36 10 DDR_DATA_59 5%
MEM_DATA<60> K33
DDR_DATA_60
DDR_MCLK_5_N W36 INT_DDRCLK5_N_TP RP31 1/16W
SM1
36 10
J36 AA22 3
22 6
36 10 MEM_DATA<61> DDR_DATA_61 DDR_REF INT_MEM_REF_H 38 36 9 MEM_ADDR<7> RAM_ADDR<7> 11 36
MEM_DATA<62> K36
36 10 DDR_DATA_62 5%
MEM_DATA<63> K35
DDR_DATA_63
DDR_VREF_0 Y22 INT_MEM_VREF 9 38 1/16W
SM1
RP30
36 10
DDR_VREF_1 T22 22
36 9 MEM_ADDR<8> 4 5 RAM_ADDR<8> 11 36
RP31 5%
1/16W
1 22 SM1
R199 36 9 MEM_ADDR<9>
2 7 RAM_ADDR<9> 11 36
1K 5%
1%
1/16W 1/16W RP31
MF SM1 22 PULL-DOWN RESISTORS TO ENSURE
MEM_VREF 2 402 36 9 MEM_ADDR<10>
4 5 RAM_ADDR<10> 11 36
CKE STAYS LOW AFTER INTREPID
5%
RP26 1/16W
SM1
2.5V I/O SHUTS OFF
22
38 16 15 10 +2_5V_INTREPID 36 9 MEM_ADDR<11>
4 5 RAM_ADDR<11> 11 36
36 11 9 RAM_CKE<0>
5%
1/16W
SM1 RP30 36 11 9 RAM_CKE<1>
22 RAM_CKE<2>
36 9 MEM_ADDR<12>
3 6 RAM_ADDR<12> 11 36 11 9
R1981 36
RAM_CKE<3>
10K
1%
RP26 5%
1/16W
36 11 9
1/16W 22 SM1
MF
402 2
36 9 MEM_BA<0>
2
5%
7 RAM_BA<0> 11 36 R5001 R4391 R4091
10K 10K 10K
R3871
10K
INT - DDR/BOOTROM
BA
A INT_MEM_VREF 9 38
1/16W
SM1
1
RP26
22
8
5%
1/16W
MF
5%
1/16W
MF
5%
1/16W
MF
5%
1/16W
MF NOTICE OF PROPRIETARY PROPERTY
A
36 9 MEM_BA<1> RAM_BA<1> 11 36 402 2 402 2 402 2 402 2
R1911 C245 1 5%
10K 0.1UF RP26 1/16W
SM1
1% 20%
10V
22 AGREES TO THE FOLLOWING
1/16W 36 9 MEM_WE_L
3 6 RAM_WE_L
MF CERM 2 11 36
402 2 402
5%
CNTL
1/16W R250 II NOT TO REPRODUCE OR COPY IT

SM1
1
22 2
36 9 MEM_CAS_L RAM_CAS_L 11 36
5% SIZE DRAWING NUMBER REV.

R238 1/16W
36 9 MEM_RAS_L 1
22
5%
2
MF
402 RAM_RAS_L 11 36
APPLE COMPUTER INC.
D 051-6459 A
SCALE SHT OF
1/16W
MF
402 NONE 9 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
38 16 15 10 9 +2_5V_INTREPID
BIT 0..15 38 16 15 10 9 +2_5V_INTREPID
BIT 16..31 38 16 15 10 9 +2_5V_INTREPID
BIT 32..47 38 16 15 10 9 +2_5V_INTREPID
BIT 48..63
D D
1 C735 1 C727 1 C743 1 C736 1 C738 1 C737
1 C741 1 C747 1 C752 1 C753 1 C742 1 C748 20%
0.1UF 0.1UF
20% 20%
0.1UF 0.1UF
20% 20%
0.1UF 0.1UF
20%
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 10V 10V 10V 10V 10V 10V
20% 20% 20% 20% 20% 20% 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
10V
2 CERM 402 402 402 402 402 402
402 402 402 402 402 402
CRITICAL CRITICAL
E8
F3
F8
E8
F3
F8
CRITICAL
E8
F3
F8
CRITICAL
E8
F3
F8
VDD VDD
VDD 36 11 RAM_DATA_B<32>
G1 DB0* DA11 C10 RAM_DATA_A<41> 11 36 36 11 RAM_DATA_B<48> G1 DB0* DA11 C10 RAM_DATA_A<57> 11 36
VDD 36 11 RAM_DATA_B<16> G1 DB0* DA11 C10 RAM_DATA_A<25> 11 36
36 11 RAM_DATA_B<0> G1 DB0* DA11 C10 RAM_DATA_A<9> 11 36 36 11 RAM_DATA_B<33>
J1 DB1* DA12 A10 RAM_DATA_A<42> 11 36 36 11 RAM_DATA_B<49> J1 DB1* DA12 A10 RAM_DATA_A<58> 11 36
RAM_DATA_B<17> J1 DB1* DA12 A10 RAM_DATA_A<26>
36 11 RAM_DATA_B<1> J1 DB1* DA12 A10 RAM_DATA_A<10> 11 36
36 11
K2 U12
11 36
36 11 RAM_DATA_B<34>
K2 DB2* U10 DA13 A8 RAM_DATA_A<43> 11 36 36 11 RAM_DATA_B<50> K2 DB2* U9 DA13 A8 RAM_DATA_A<59> 11 36
RAM_DATA_B<18> DB2* DA13 A8 RAM_DATA_A<27>
36 11 RAM_DATA_B<2> K2 DB2* U13
CBTV4020
DA13 A8 RAM_DATA_A<11> 11 36
36 11
RAM_DATA_B<19> J4 DB3*
CBTV4020
DA14 A7 RAM_DATA_A<28>
11 36
J4 DB3*
CBTV4020
BGA DA14 A7 RAM_DATA_A<44> 11 36 36 11 RAM_DATA_B<51> J4 DB3*
CBTV4020
BGA DA14 A7 RAM_DATA_A<60> 11 36
J4 36 11 BGA 11 36
36 11 RAM_DATA_B<3> DB3* BGA DA14 A7 RAM_DATA_A<12> 11 36
K5 A5 36 11 RAM_DATA_B<36>
K5 DB4* DA15 A5 RAM_DATA_A<45> 11 36 36 11 RAM_DATA_B<52> K5 DB4* DA15 A5 RAM_DATA_A<61> 11 36
36 11 RAM_DATA_B<20> DB4* DA15 RAM_DATA_A<29> 11 36
36 11 RAM_DATA_B<4> K5 DB4* DA15 A5 RAM_DATA_A<13> 11 36 36 11 RAM_DATA_B<37>
K7 DB5* DA16 B4 RAM_DATA_A<46> 11 36 36 11 RAM_DATA_B<53> K7 DB5* DA16 B4 RAM_DATA_A<62> 11 36
36 11 RAM_DATA_B<21> K7 DB5* DA16 B4 RAM_DATA_A<30> 11 36
36 11 RAM_DATA_B<5> K7 DB5* DA16 B4 RAM_DATA_A<14> 11 36 36 11 RAM_DATA_B<38>
K8 DB6* DA17 A2 RAM_DATA_A<47> 11 36 36 11 RAM_DATA_B<54> K8 DB6* DA17 A2 RAM_DATA_A<63> 11 36
36 11 RAM_DATA_B<22> K8 DB6* DA17 A2 RAM_DATA_A<31> 11 36
36 11 RAM_DATA_B<6> K8 DB6* DA17 A2 RAM_DATA_A<15> 11 36 36 11 RAM_DATA_B<39>
K10 DB7* DA18 B1 RAM_DQS_A<5> 11 36 36 11 RAM_DATA_B<55> K10 DB7* DA18 B1 RAM_DQS_A<7> 11 36
36 11 RAM_DATA_B<23> K10 DB7* DA18 B1 RAM_DQS_A<3> 11 36
36 11 RAM_DATA_B<7> K10 DB7* DA18 B1 RAM_DQS_A<1> 11 36 36 11 RAM_DQS_B<4>
H10 DB8* DA19 D1 RAM_DQM_A<5> 11 36 36 11 RAM_DQS_B<6> H10 DB8* DA19 D1 RAM_DQM_A<7> 11 36
36 11 RAM_DQS_B<2> H10 DB8* DA19 D1 RAM_DQM_A<3> 11 36
36 11 RAM_DQS_B<0> H10 DB8* DA19 D1 RAM_DQM_A<1> 11 36 36 11 RAM_DQM_B<4>
F10 DB9* 36 11 RAM_DQM_B<6> F10 DB9*
36 11 RAM_DQM_B<2> F10 DB9*
36 11 RAM_DQM_B<0> F10 DB9* 36 11 RAM_DATA_B<40>
D10 DB10* 36 11 RAM_DATA_B<56> D10 DB10*
36 11 RAM_DATA_B<24> D10 DB10*
36 11 RAM_DATA_B<8> D10 DB10* 36 11 RAM_DATA_B<41>
B10 DB11* 36 11 RAM_DATA_B<57> B10 DB11*
36 11 RAM_DATA_B<25> B10 DB11* DH0 F2 MEM_DATA<32> 9 36 DH0 F2 MEM_DATA<48> 9 36
36 11 RAM_DATA_B<9> B10 DB11* DH0 F2 MEM_DATA<16> 9 36 36 11 RAM_DATA_B<42>
A9 DB12* 36 11 RAM_DATA_B<58> A9 DB12*
A9 DH0 F2 MEM_DATA<0> 9 36 36 11 RAM_DATA_B<26> A9 DB12* DH1 H2 MEM_DATA<33> 9 36 DH1 H2 MEM_DATA<49> 9 36
36 11 RAM_DATA_B<10> DB12* DH1 H2 MEM_DATA<17> 9 36 36 11 RAM_DATA_B<43>
B7 DB13* 36 11 RAM_DATA_B<59> B7 DB13*
B7 DH1 H2 MEM_DATA<1> 9 36 36 11 RAM_DATA_B<27> B7 DB13* DH2 J2 MEM_DATA<34> 9 36 DH2 J2 MEM_DATA<50> 9 36
36 11 RAM_DATA_B<11> DB13* DH2 J2 MEM_DATA<18> 9 36 36 11 RAM_DATA_B<44>
A6 DB14* 36 11 RAM_DATA_B<60> A6 DB14*
A6
DH2 J2 MEM_DATA<2> 9 36 36 11 RAM_DATA_B<28> A6 DB14* DH3 J3 MEM_DATA<35> 9 36 DH3 J3 MEM_DATA<51> 9 36
36 11 RAM_DATA_B<12> DB14* DH3 J3 MEM_DATA<19> 9 36 36 11 RAM_DATA_B<45>
A4 DB15* 36 11 RAM_DATA_B<61> A4 DB15*
DH3 J3 A4 DH4 J5 DH4 J5
C 36 11
36 11
RAM_DATA_B<13>
RAM_DATA_B<14>
A4
A3
DB15*
DB16*
DH4 J5
MEM_DATA<3>
MEM_DATA<4>
9 36
9 36
36 11
36 11
RAM_DATA_B<29>
RAM_DATA_B<30> A3
DB15*
DB16*
DH4 J5
DH5 J6
MEM_DATA<20>
MEM_DATA<21>
9 36
9 36
A3
A1
DB16*
DB17*
DH5 J6
MEM_DATA<36>
MEM_DATA<37>
9 36
9 36
36 11
36 11
RAM_DATA_B<62>
RAM_DATA_B<63>
A3
A1
DB16*
DB17*
DH5 J6
MEM_DATA<52>
MEM_DATA<53>
9 36
9 36
C
A1
DH5 J6 MEM_DATA<5> 9 36 36 11 RAM_DATA_B<31> A1 DB17* DH6 J8 MEM_DATA<38> 9 36 DH6 J8 MEM_DATA<54> 9 36
36 11 RAM_DATA_B<15> DB17* DH6 J8 MEM_DATA<22> 9 36 36 11 RAM_DQS_B<5>
C1 DB18* 36 11 RAM_DQS_B<7> C1 DB18*
C1 DH6 J8 MEM_DATA<6> 9 36 36 11 RAM_DQS_B<3> C1 DB18* DH7 J9 MEM_DATA<39> 9 36 DH7 J9 MEM_DATA<55> 9 36
36 11 RAM_DQS_B<1> DB18* DH7 J9 MEM_DATA<23> 9 36 36 11 RAM_DQM_B<5>
E1 DB19* 36 11 RAM_DQM_B<7> E1 DB19*
E1
DH7 J9 MEM_DATA<7> 9 36 36 11 RAM_DQM_B<3> E1 DB19* DH8 H9 MEM_DQS<4> 9 36 DH8 H9 MEM_DQS<6> 9 36
36 11 RAM_DQM_B<1> DB19* DH8 H9 MEM_DQS<2> 9 36
DH8 H9 MEM_DQS<0> 9 36 DH9 F9 MEM_DQM<4> 9 36 DH9 F9 MEM_DQM<6> 9 36
DH9 F9 MEM_DQM<2> 9 36
DH9 F9 MEM_DQM<0> 9 36
E9 DH10 E9 MEM_DATA<40> 9 36 DH10 E9 MEM_DATA<56> 9 36
DH10 MEM_DATA<24> 9 36
DH10 E9 MEM_DATA<8> 9 36 DH11 C9 MEM_DATA<41> 9 36 DH11 C9 MEM_DATA<57> 9 36
DH11 C9 MEM_DATA<25> 9 36 36 11 RAM_DATA_A<32>
F1 DA0 36 11 RAM_DATA_A<48> F1 DA0
F1 DA0 DH11 C9 MEM_DATA<9> 9 36 36 11 RAM_DATA_A<16> F1 DA0 DH12 B9 MEM_DATA<42> 9 36 DH12 B9 MEM_DATA<58> 9 36
36 11 RAM_DATA_A<0> DH12 B9 MEM_DATA<26> 9 36 36 11 RAM_DATA_A<33>
H1 DA1 36 11 RAM_DATA_A<49> H1 DA1
H1 DA1 DH12 B9 MEM_DATA<10> 9 36 36 11 RAM_DATA_A<17> H1 DA1 DH13 B8 MEM_DATA<43> 9 36 DH13 B8 MEM_DATA<59> 9 36
K1 DA2 36 11 RAM_DATA_A<50> K1 DA2
K1 DA2
DH13 B8 MEM_DATA<11> 9 36 36 11 RAM_DATA_A<18> K1 DA2 DH14 B6 MEM_DATA<44> 9 36 DH14 B6 MEM_DATA<60> 9 36
K3 DA3 DH14 B6 MEM_DATA<12> 9 36 36 11 RAM_DATA_A<19> K3 DA3 DH15 B5 MEM_DATA<45> 9 36 DH15 B5 MEM_DATA<61> 9 36
K4 DA4
K6 DA5
J7 DA6 36 11 RAM_DATA_A<54> J7 DA6
J7 DA6 DH17 B2 MEM_DATA<15> 9 36 36 11 RAM_DATA_A<22> J7 DA6 DH18 C2 MEM_DQS<5> 9 36 DH18 C2 MEM_DQS<7> 9 36
36 11 RAM_DATA_A<6> DH18 C2 MEM_DQS<3> 9 36 36 11 RAM_DATA_A<39>
K9 DA7
DH18 C2 MEM_DQS<1> 9 36 36 11 RAM_DATA_A<23> K9 DA7 DH19 E2 MEM_DQM<5> 9 36 DH19 E2 MEM_DQM<7> 9 36
36 11 RAM_DATA_A<7> DH19 E2 MEM_DQM<3> 9 36 36 11 RAM_DQS_A<4>
J10 DA8 36 11 RAM_DQS_A<6> J10 DA8
J10 DA8
DH19 E2 MEM_DQM<1> 9 36 36 11 RAM_DQS_A<2> J10 DA8
G10 DA9 G10 DA9
36 11 RAM_DQS_A<0> 36 11 RAM_DQM_A<4> 36 11 RAM_DQM_A<6>
36 11 RAM_DQM_A<2> G10 DA9
36 11 RAM_DQM_A<0> G10 DA9 36 11 RAM_DATA_A<40>
E10 DA10 SEL E3 RAM_MUXSEL_H 10 36 36 11 RAM_DATA_A<56> E10 DA10 SEL E3 RAM_MUXSEL_H 10 36
36 11 RAM_DATA_A<24> E10 DA10 SEL E3 RAM_MUXSEL_L 10 36
36 11 RAM_DATA_A<8> E10 DA10 SEL E3 RAM_MUXSEL_L 10 36
GND GND
GND
C5
C6
D2
D9
G2
G9
H5
H6
C5
C6
D2
D9
G2
G9
H5
H6
GND
C5
C6
D2
D9
G2
G9
H5
H6
C5
C6
D2
D9
G2
G9
H5
H6
B B
SEL = LOW; HOST = B PORT; A PORT = 100OHM TO GND
SEL = HIGH; HOST = A PORT; B PORT = 100OHM TO GND
MEM_MUXSEL_H<0> AND MEM_MUXSEL_L<0> ARE ACTIVE LOW
MEM_MUXSEL_H<1> AND MEM_MUXSEL_L<1> ARE ACTIVE HIGH
ADDED 0 OHM RESISTORS IN CASE POLARITY IS WRONG
NO STUFF
R242 R243
1
0 2 1
0 2
MEM_MUXSEL_L<0> RAM_MUXSEL_L MEM_MUXSEL_L<1> RAM_MUXSEL_L
36 9
5%
1/16W
10 36 36 9
5%
1/16W
10 36
16BIT 2:1 DDR MUXES

A MF
402
MF
402
A
NO STUFF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
R252 R239
1
0 2 1
0 2
36 9 MEM_MUXSEL_H<0> RAM_MUXSEL_H 10 36 36 9 MEM_MUXSEL_H<1> RAM_MUXSEL_H 10 36
5% 5%
1/16W 1/16W III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
MF MF
402 402
APPLE COMPUTER INC.

D 051-6459 A
SCALE SHT OF
NONE 10 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+2_5V_MAIN +2_5V_MAIN +2_5V_MAIN 201 CRITICAL +2_5V_MAIN
201 CRITICAL
38 11 DDR_VREF
2 1 DDR_VREF +2_5V_MAIN
DDR_VREF 1 2 DDR_VREF VREF1 VREF0 11 38
38 11 VREF0 VREF1 11 38
4 3
3 4 VSS1 VSS0
VSS0 VSS1 6 J22 5
36 10 RAM_DATA_A<0> 5
7
DQ0 J19
AS0A42-D2S
DQ4
6
8
RAM_DATA_A<4> 10 36
36 10
36 10
RAM_DATA_B<4>
RAM_DATA_B<5> 8
DQ4
DQ5
AS0A42-D2R DQ0
F-RT-SM DQ1
7
RAM_DATA_B<0>
RAM_DATA_B<1>
10 36
10 36
DDR VREF
36 10 RAM_DATA_A<1> DQ1 F-RT-SM DQ5 RAM_DATA_A<5> 10 36
10 9 1
R449 ONE 0.1UF PER SLOT
9 10 VDD1 VDD0
VDD0 VDD1 RAM_DQM_B<0> 12 11 RAM_DQS_B<0> 1K
RAM_DQS_A<0> 11 12 RAM_DQM_A<0>
36 10
DM0 DQS0 10 36
1%
36 10 DQS0 DM0 10 36
RAM_DATA_B<6> 14 13 RAM_DATA_B<2> 1/16W
RAM_DATA_A<2> 13 14 RAM_DATA_A<6>
36 10 DQ6 DQ2 10 36
MF
36 10 DQ2 DQ6 10 36
16 15
15 16 VSS3 VSS2 2 402
VSS2 VSS3 RAM_DATA_B<7> 18 17 RAM_DATA_B<3> DDR_VREF
RAM_DATA_A<3> 17 18 RAM_DATA_A<7>
36 10
DQ7 DQ3 10 36 11 38
36 10 DQ3 DQ7 10 36
RAM_DATA_B<12> 20 19 RAM_DATA_B<8>
19 20 36 10 DQ12 DQ8 10 36
1
36 10 RAM_DATA_A<8> DQ8 DQ12 RAM_DATA_A<12> 10 36
22 21 R440 1 C542 1 C482
D RAM_DATA_A<9>
21
23
VDD2 VDD3
22
24 RAM_DATA_A<13> 10
36 10 RAM_DATA_B<13> 24
VDD3
DQ13
VDD2
DQ9
23 RAM_DATA_B<9> 10 36 1%
1K
1/16W
0.1UF
20%
0.1UF
20%
D
36 10 DQ9 DQ13 36 10V
25 26 36 10 RAM_DQM_B<1> 26
DM1 DQS1
25 RAM_DQS_B<1> 10 36 MF 2 CERM 2 10V
CERM
RAM_DQS_A<1> RAM_DQM_A<1>
36 10 DQS1 DM1 10 36
28 27 2 402 402 402
27 28 VSS5 VSS4
VSS4 VSS5 RAM_DATA_B<14> 30 29 RAM_DATA_B<10>
RAM_DATA_A<10> 29 30 RAM_DATA_A<14> 10
36 10 DQ14 DQ10 10 36
36 10 DQ10 DQ14 36
36 10
DQ15 DQ11 10 36
36 10 DQ11 DQ15 36
34 33
33 34 VDD5 VDD4
VDD4 VDD5 36 35 SYSCLK_DDRCLK_B0
SYSCLK_DDRCLK_A0 35 36 VDD6 CK0 9 36
36 9 CK0 VDD6 38 37 SYSCLK_DDRCLK_B0_L
SYSCLK_DDRCLK_A0_L 37 38 VSS6 CK0* 9 36
36 9 CK0* VSS6 40 39
39 40 VSS8 VSS7
VSS7 VSS8 KEY
KEY RAM_DATA_B<20> 42 41 RAM_DATA_B<16>
36 10 RAM_DATA_A<16>
RAM_DATA_A<17>
41
43
DQ16 DQ20
42
44
RAM_DATA_A<20> 10
RAM_DATA_A<21> 10
36
36 10
36 10 RAM_DATA_B<21> 44
DQ20
DQ21
DQ16
DQ17
43 RAM_DATA_B<17>
10 36
10 36
DDR BYPASS CAPS
36 10 DQ17 DQ21 36
46 45
45 46 VDD8 VDD7 +2_5V_MAIN
36 10 RAM_DQS_A<2> 47
VDD7
DQS2
VDD8
DM2
48 RAM_DQM_A<2> 10 36
36 10 RAM_DQM_B<2> 48
50
DM2 DQS2
47
49
RAM_DQS_B<2> 10 36 SLOT "A"
36 10 RAM_DATA_B<22> DQ18 RAM_DATA_B<18> 10 36
RAM_DATA_A<18> 49 50 RAM_DATA_A<22> 10 DQ22
36 10 DQ18 DQ22 36
52 51
51 52 VSS10 VSS9
36 10 DQ23 DQ19 10 36
36 10 DQ19 DQ23 36
56 55
36 10 RAM_DATA_A<24> 55
DQ24 DQ28
56 RAM_DATA_A<28> 10 36
58
DQ28 DQ24
57
RAM_DATA_B<24> 10 36 1 C602 1 C601
57 58 VDD10 VDD9 10UF 10UF
VDD9 VDD10 60 59 20% 20%
36 10 RAM_DATA_B<29> DQ25 RAM_DATA_B<25> 10 36 6.3V 6.3V
RAM_DATA_A<25> 59 60 RAM_DATA_A<29> 10 DQ29 2 CERM 2 CERM
36 10 DQ25 DQ29 36
RAM_DQM_B<3> 62 61 RAM_DQS_B<3> 805 805
36 10
DM3 DQS3 10 36
36 10 DQS3 DM3 10 36
64 63
63 64 VSS12 VSS11
36 10 DQ30 DQ26 10 36
36 10 DQ26 DQ30 36
36 10
DQ31 DQ27 10 36
36 10 DQ27 DQ31 36
70 69
69 70 VDD12 VDD11
VDD11 VDD12 72 71
NC
71
RFU0 RFU1
72 NC NC
74
RFU1 RFU0
73
NC 1 C573 1 C526 1 C525 1 C490 1 C527
NC 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
C NC
73
75
RFU2
VSS13
RFU3
VSS14
74
76
NC NC
76
RFU3
VSS14
RFU2
VSS13
75 20%
10V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM
C
STANDARD NC
NC
77
79
81
RFU4
RFU6
RFU5
RFU7
78
80
82
NC
NC
REVERSED NC
NC
78
80
82
RFU5
RFU7
VDD14
RFU4
RFU6
VDD13
77
79
81
NC
NC
402 402 402 402 402
SLOT "A" NC
NC
83
85
VDD13
RFU8
RFU10
VDD14
RFU9
RFU11
84
86
NC
NC
SLOT "B" NC
NC
84
86
88
RFU9
RFU11
RFU8
RFU10
83
85
87
NC
NC
1 C595 1 C524 1 C549 1 C523 1 C481
VSS16 VSS15
FACTORY SLOT NC
NC
87
89
91
VSS15
RFU12
RFU13
VSS16
VSS17
VDD15
88
90
92
CUSTOMER SLOT 90
92
94
VSS17
VDD15
RFU12
RFU13
89
91
93
NC
NC
0.1UF
20%
10V
2 CERM
402
0.1UF
20%
10V
2 CERM
402
0.1UF
20%
10V
2 CERM
402
0.1UF
20%
10V
2 CERM
402
0.1UF
20%
10V
2 CERM
402
93 94 VDD17 VDD16
VDD16 VDD17 RAM_CKE<2> 96 95 RAM_CKE<3>
RAM_CKE<1> 95 96 RAM_CKE<0>
36 9
CKE0 CKE1 9 36
36 9 CKE1 CKE0 9 36
98 97
97 98 NC RFU15 RFU14 NC
NC RFU14 RFU15 NC 100 99
36 11 9 RAM_ADDR<11> A12 RAM_ADDR<12> 9 11 36
RAM_ADDR<12> 99 100 RAM_ADDR<11> A11
36 11 9 A12 A11 9 11 36
RAM_ADDR<8> 102 101 RAM_ADDR<9>
101 102 36 11 9
A8 A9 9 11 36
36 11 9 RAM_ADDR<9>
103
A9 A8
104
RAM_ADDR<8> 9 11 36
104
VSS19 VSS18
103 FOR RETURN CURRENT
VSS18 VSS19 RAM_ADDR<6> 106 105 RAM_ADDR<7>
36 11 9
A6 A7 9 11 36
36 11 9 A7 A6 9 11 36
36 11 9 A4 A5 9 11 36
36 11 9 A5 A4 9 11 36
109 110 36 11 9 A2 A3 9 11 36 +2_5V_MAIN
36 11 9
36 11 9
RAM_ADDR<3>
RAM_ADDR<1> 111
A3
A1
A2
A0
112
RAM_ADDR<2>
RAM_ADDR<0>
9 11 36
9 11 36
36 11 9 RAM_ADDR<0> 112
114
A0 A1
111
113
RAM_ADDR<1> 9 11 36 SLOT "B"
113 114 VDD19 VDD18
VDD18 VDD19 RAM_BA<1> 116 115 RAM_ADDR<10>
RAM_ADDR<10> 115 116 RAM_BA<1>
36 11 9
BA1 A10_AP 9 11 36
36 11 9 A10_AP BA1 9 11 36
RAM_RAS_L 118 117 RAM_BA<0>
RAM_BA<0> 117 118 RAM_RAS_L
36 11 9
RAS* BA0 9 11 36
36 11 9 BA0 RAS* 9 11 36
120 119
36 11 9 RAM_WE_L 119
WE* CAS*
120 RAM_CAS_L 9 11 36
36 11 9 RAM_CAS_L
122
CAS* WE*
121
RAM_WE_L 9 11 36 1 C589 1 C530
RAM_CS_L<0> 121 122 RAM_CS_L<1>
36 9 RAM_CS_L<3>
S1* S0* RAM_CS_L<2> 9 36 10UF 10UF
36 9 S0* S1* 9 36
124 123 20% 20%
123 124 NC NC RFU17 RFU16 NC 2 6.3V
CERM 2 6.3V
CERM
NC RFU16 RFU17 126 125 805 805
125 126 VSS21 VSS20
B 36 10 RAM_DATA_A<32> 127
VSS20
DQ32
VSS21
DQ36
128 RAM_DATA_A<36> 10 36
RAM_DATA_B<37>
128
130
DQ36 DQ32
127
129
RAM_DATA_B<32>
RAM_DATA_B<33>
10 36 B
36 10 DQ37 DQ33 10 36
36 10 DQ33 DQ37 36
132 131
131 132 VDD21 VDD20
VDD20 VDD21 RAM_DQM_B<4> 134 133 RAM_DQS_B<4>
36 10
DM4 DQS4 10 36
36 10 DQS4 DM4 10 36
136 135
36 10 RAM_DATA_A<34> 135
DQ34 DQ38
136 RAM_DATA_A<38> 10 36
138
DQ38 DQ34
137
RAM_DATA_B<34> 10 36 1 C551 1 C550 1 C596 1 C597 1 C522
137 138 VSS23 VSS22 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
VSS22 VSS23 140 139 20% 20% 20% 20% 20%
RAM_DATA_B<39> RAM_DATA_B<35>
36 10
DQ39 DQ35 10 36
2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
10V
2 CERM
36 10 DQ35 DQ39 36
RAM_DATA_B<44> 142 141 RAM_DATA_B<40> 402 402 402 402 402
36 10 DQ44 DQ40 10 36
36 10 DQ40 DQ44 36
144 143
143 144 VDD23 VDD22
VDD22 VDD23 RAM_DATA_B<45> 146 145 RAM_DATA_B<41>
36 10
DQ45 DQ41 10 36
36 10 DQ41 DQ45 36
RAM_DQM_B<5> 148 147 RAM_DQS_B<5>
36 10 DM5 DQS5 10 36
36 10 DQS5 DM5 10 36
150 149
149 150 VSS25 VSS24
151
VSS24 VSS25
152 36 10 RAM_DATA_B<46> 152
DQ46 DQ42
151 RAM_DATA_B<42> 10 36
1 C761 1 C565 1 C548 1 C594 1 C489
36 10 RAM_DATA_A<42> DQ42 DQ46 RAM_DATA_A<46> 10 36
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
153 154 36 10 DQ47 DQ43 10 36 20% 20% 20% 20% 20%
36 10 RAM_DATA_A<43> DQ43 DQ47 RAM_DATA_A<47> 10 36 10V 10V 10V 10V 10V
156 155 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
155 156 VDD25 VDD24 402 402 402 402 402
VDD24 VDD25 SYSCLK_DDRCLK_B1_L 158 157
157 158 SYSCLK_DDRCLK_A1_L
36 9 CK1* VDD26
VDD26 CK1* 9 36
SYSCLK_DDRCLK_B1 160 159
159 160 SYSCLK_DDRCLK_A1
36 9
CK1 VSS26
VSS26 CK1 9 36
162 161
161 162 VSS28 VSS27
36 10 DQ52 DQ48 10 36
36 10 DQ48 DQ52 36
36 10
DQ53 DQ49 10 36
36 10 DQ49 DQ53 36
168 167
167 168 VDD28 VDD27
VDD27 VDD28 RAM_DQM_B<6> 170 169 RAM_DQS_B<6>
36 10 DM6 DQS6 10 36
36 10 DQS6 DM6 10 36
36 10
DQ54 DQ50 10 36
36 10 DQ50 DQ54 36
174 173
173 174 VSS30 VSS29
36 10 RAM_DATA_A<51> 175
VSS29
DQ51
VSS30
DQ55
176 RAM_DATA_A<55> 10 36
36 10
36 10
RAM_DATA_B<55>
RAM_DATA_B<60>
176
178
DQ55 DQ51
DQ56
175
177
RAM_DATA_B<51>
RAM_DATA_B<56>
10 36
10 36
DDR SODIMM CONNS
A 36 10 RAM_DATA_A<56> 177
179
DQ56
VDD29
DQ60
VDD30
178
180
RAM_DATA_A<60> 10 36
180
182
DQ60
VDD30 VDD29
179
181 NOTICE OF PROPRIETARY PROPERTY
A
RAM_DATA_A<57> 181 182 RAM_DATA_A<61> 10 DQ61
36 10 DQ57 DQ61 36
RAM_DQM_B<7> 184 183 RAM_DQS_B<7>
36 10
DM7 DQS7 10 36
36 10 DQS7 DM7 10 36
185 186 +3V_MAIN VSS32 VSS31 AGREES TO THE FOLLOWING
36 10
DQ62 DQ58 10 36
36 10 DQ58 DQ62 36
190 189 +3V_MAIN
+3V_MAIN RAM_DATA_A<59> 189 190 RAM_DATA_A<63> 10 DQ63 II NOT TO REPRODUCE OR COPY IT
36 10 DQ59 DQ63 36
192 191
191 192 VDD32 VDD31 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
VDD31 VDD32 194 193 INT_I2C_DATA0
INT_I2C_DATA0 193 194 SA0 SDA 11 13 23 39
39 23 13 11 SDA SA0 196 195 INT_I2C_CLK0 SIZE DRAWING NUMBER REV.
195 196 SA1 SCL 11 13 23 39
39 23 13 11 INT_I2C_CLK0
197
SCL SA1
198 ADDR=0XA0(WR)/0XA1(RD) ADDR=0XA2(WR)/0XA3(RD) 198
SA2 VDDSPD
197
D 051-6459 A
VDDSPD SA2 200 199
199 200 NC RFU19 RFU18 NC APPLE COMPUTER INC.
NC RFU18 RFU19 NC SCALE SHT OF
202
202
NONE 11 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AGP PULL-UPS/PULL DOWNS

R146
+1_5V_INTREPID_PLL 1
4.7 2 +1_5V_INTREPID_PLL5
38 14 12 8 38
5% +3V_GPU 18 19 21 38
R112 C160 1
1/16W
MF
+1_5V_INTREPID_PLL 1
4.7 2 +1_5V_INTREPID_PLL6 0.22UF 402
38 14 12 8 38
38 21 19 18 16 15 12 +1_5V_AGP 20%
5% 6.3V
1/16W CERM 2
C83 1 MF 402 RP19
0.22UF 402 10K
D 20%
6.3V
CERM 2
18 12 AGP_BUSY_L
2
5%
7
D
402 1/16W
R192 NOTE: Designs using AGP slot should RP19 SM1
33
1
R209 use 52-ohm a resistor here. 1
10K 8
1 2 12 STOP_AGP_L
39 36 24 CLK33M_AIRPORT 60.4
J11
5% 1% V14 5%
1/16W VDD15A_6 1/16W 1/16W
MF 39 24 12 AIRPORT_PCI_REQ_L AR17 PCI_REQ_0 (PLL4)
PCIAD_0 AM10 PCI_AD<0> 9 17 24 26 37 39
MF VDD15A_5 SM1
402
AR8 2 402 (PLL5)
17 12 CBUS_PCI_REQ_L AR16 PCI_REQ_1 PCIAD_1 PCI_AD<1> 9 17 24 26 37 39
R147 26 12 USB2_PCI_REQ_L AT17 PCI_REQ_2 CRITICAL PCIAD_2 AK12 PCI_AD<2> 9 17 24 26 37 39

AN19
U45 +1_5V_AGP 12
38
15 16 18 19 21
AJ8 12 STP_AGP INTREPID-REV2.1 AGPREQ AT33

STOP_AGP_L AGP_REQ_L 12 18 37
33 PCIAD_3 PCI_AD<3> 9 17 24 26 37 39
AJ24
36 17 CLK33M_CBUS 1 2 39 24 AIRPORT_PCI_GNT_L AT16 PCI_GNT_0 U45 AN10 PCI_AD<4>
INT_AGPPVT
AGPPVT BGA AGPGNT AM29 AGP_GNT_L 12 18 37
AN18 PCIAD_4 9 17 24 26 37 39
AB20 (3 OF 9)
5% CBUS_PCI_GNT_L 38 18 12 INT_AGP_VREF
1/16W
17
INTREPID-REV2.1
PCI_GNT_1
PCIAD_5 AT8 PCI_AD<5> 9 17 24 26 37 39
AB21
AGPVREF0
AGPAD0 AR19 AGP_AD<0> 18 37
MF 26 USB2_PCI_GNT_L AN17 PCI_GNT_2 BGA AGPVREF1 CRITICAL
AN11
402 (7 OF 9) PCIAD_6 PCI_AD<6> 9 17 24 26 37 39 AGPAD1 AM19 AGP_AD<1> 18 37
NEC_USB 36 CLK33M_AIRPORT_UF AR18 PCI_CLK0 PCIAD_7 AH13 PCI_AD<7> 9 17 24 26 37 39 AGPAD2 AT20 AGP_AD<2> 18 37 RP22
R157 AH18 AK13 AT19 10K
36 CLK33M_CBUS_UF PCI_CLK1 PCI/ROM PCIAD_8 PCI_AD<8> 9 17 24 26 37 39 18 12 AGP_BUSY_L AGP_BUSY AGPAD3 AR20 AGP_AD<3> 18 37
37 18 12 AGP_REQ_L
4 5
22 AT18 AR9
36 26 CLK33M_USB2 1 2 36 CLK33M_USB2_UF PCI_CLK2 INTERFACE PCIAD_9 PCI_AD<9> 9 17 24 26 37 39 CLK66M_AGP_15V_TP AK28 AGP_CLK AGPAD4 AT21 AGP_AD<4> 18 37
5%
5% 36 INT_PCI_FB_OUT AM18 PCI_CLK_OUT PCIAD_10 AR10 PCI_AD<10> 9 17 24 26 37 39 36 INT_AGP_FB_IN AK27
AGP_FB_IN Vin = Vcore (1.5V) AGPAD5 AN20 AGP_AD<5> 18 37
1/16W
SM1
RP20
1/16W
AJ19 VOUT = 3.3V AT9 AK25 10K
MF
402
36 INT_PCI_FB_IN PCI_CLK_IN PCIAD_11 PCI_AD<11> 9 17 24 26 37 39 36 INT_AGP_FB_OUT AGP_FB_OUT Vout = AGPIO (1.5V) AGPAD6 AR21 AGP_AD<6> 18 37
37 18 12 AGP_GNT_L
4 5
OUTPUT IMPEDANCE IS ABOUT 20OHM VIN = 1.5V (CORE) PCIAD_12 AR11 PCI_AD<12> 9 17 24 26 37 39 AGPAD7 AN21 AGP_AD<7> 18 37
37 26 24 17 PCI_PAR
AT14 PCI_PAR Need divider for 3.3V slot! 5%
R171 39
PCI_FRAME_L AN16 PCI_FRAME
PCIAD_13 AM12 PCI_AD<13> 9 17 24 26 37 39
R217 AGPAD8 AM21 AGP_AD<8> 18 37 RP20 1/16W
SM1
33
26 24 17
39
12
37 PCIAD_14 AN12 PCI_AD<14> 9 17 24 26 37 39
0 2 AGPAD9 AT22 AGP_AD<9> 18 37
10K
1 2 PCI_TRDY_L AT15 PCI_TRDY 37 18 12 AGP_FRAME_L
3 6
26 24 17 12
AK11 1
5%
39 37
PCI_IRDY_L AH16 PCIAD_15 PCI_AD<15> 9 17 24 26 37 39 AGPAD10 AR22 AGP_AD<10> 18 37
26 24 17 12 PCI_IRDY AT11 5% 5%
1/16W
MF
39 37
PCI_STOP_L AR15
PCIAD_16 PCI_AD<16> 9 17 24 26 37 39 1/16W AGPAD11 AN22 AGP_AD<11> 18 37 1/16W
RP19
26 24 17 12 PCI_STOP AT10 MF SM1
402 39 37
PCI_DEVSEL_L AM17 PCIAD_17 PCI_AD<17> 9 17 24 26 37 39 402 AGPAD12 AM22 AGP_AD<12> 18 37 10K
26 24 17 12 PCI_DEVSEL AN13 37 18 12 AGP_DEVSEL_L
4 5
39 37 PCIAD_18 PCI_AD<18> 9 17 24 26 37 39 AGP AGPAD13 AN23 AGP_AD<13> 18 37
PCI_CBE<0> AR14 PCI_CBE_0 PCIAD_19 AM13 PCI_AD<19> INTERFACES AGPAD14 AR23 AGP_AD<14> 5%
39 37 26 24 17 9 17 24 26 37 39
AGP_FB_CLK IS ROUTED THE SAME LENGTH AS CLK66M_GPU_AGP 18 37
1/16W
1
R186 39 37 26 24 17 PCI_CBE<1> AK16 PCI_CBE_1 PCIAD_20 AR12 PCI_AD<20> 9 17 24 26 37 39 AGPAD15 AT24 AGP_AD<15> 18 37 RP22 SM1
47 10K
C 5%
1/16W
MF
39 37 26 24 17
39 37 26 24 17
PCI_CBE<2>
PCI_CBE<3>
AM16
AJ15
PCI_CBE_2
PCI_CBE_3
PCIAD_21
PCIAD_22
AJ11
AT12
PCI_AD<21>
PCI_AD<22>
17 24 26 37 39
17 24 26 37 39
AGPAD16 AM23
AGPAD17 AR24
AGP_AD<16>
AGP_AD<17>
18 37
18 37
37 18 12 AGP_IRDY_L
2
5%
7
C
2 402
36 CLK66M_GPU_AGP_UF AK17 ROM_OVRLY_EN
PCIAD_23 AM11 PCI_AD<23> 17 24 26 37 39 AGPAD18 AT25 AGP_AD<18> 18 37
1/16W
SM1 RP22
AM9 PCIAD_24 AR13 PCI_AD<24> 9 17 24 26 37 39 AGPAD19 AR25 AGP_AD<19> 18 37
3
10K 6
12 INT_ROM_CS_L
INT_ROM_OE_L AR7
ROM_CS
PCIAD_25 AK15 PCI_AD<25> 9 17 24 26 37 39
AGP I/O REFERENCE AGPAD20 AM24 AGP_AD<20> 18 37
37 18 12 AGP_TRDY_L
12 ROM_OE AH15 (PLACE CLOSE TO INTREPID AGP BALLS) 5%

INT_ROM_RW_L AN9 PCIAD_26 PCI_AD<26> 9 17 24 26 37 39 AGPAD21 AN25 AGP_AD<21> 18 37
RP20 1/16W
12 ROM_WE AN14 SM1
PCIAD_27 PCI_AD<27> 9 17 24 26 37 39 AGPAD22 AL24 AGP_AD<22> 18 37 10K
38 21 19 18 16 15 12 +1_5V_AGP 2 7
PCI FEEDBACK CLOCK MATCHES LONGEST PCI CLOCK ROUTE AT13 37 18 12 AGP_STOP_L
PCIAD_28 PCI_AD<28> 9 17 24 26 37 39 AGPAD23 AR26 AGP_AD<23> 18 37
AK14
PCIAD_29 PCI_AD<29> 9 17 24 26 37 39 AGPAD24 AT26 AGP_AD<24> 18 37
5%
AN15
AGPAD25 AM25
1/16W
SM1 RP19
R169 PCIAD_30 PCI_AD<30> 9 17 24 26 37 39 AGP_AD<25> 18 37
10K
33 (PLL4) PCIAD_31 AM15 PCI_AD<31> 9 17 24 26 37 39 R185 1 AGPAD26 AN26 AGP_AD<26> 18 37 37 18 12 AGP_RBF_L
3 6
36 18 CLK66M_GPU_AGP 1 2
VSSA_6 4.99K AGPAD27 AM26 AGP_AD<27> 18 37 5%
5%
1/16W
J10 1%
1/16W AGPAD28 AR27 AGP_AD<28> 18 37 RP22 1/16W
SM1
MF MF 10K
402 402 2 AGPAD29 AT27 AGP_AD<29> 18 37
18 12 AGP_WBF_L
1 8
INT_AGP_VREF 12 18 38
AGPAD30 AR28 AGP_AD<30> 18 37
5%
AGPAD31 AN27 AGP_AD<31> 18 37
1/16W
SM1 RP20
R1801 10K
4.99K
1 C247 AGPCBE_0 AM20 AGP_CBE<0> 18 37 12 AGP_PIPE_L
1 8
1% 0.22UF AGPCBE_1 AT23 AGP_CBE<1> 18 37 5%

1/16W 20% 1/16W
MF 2 6.3V
CERM AGPCBE_2 AN24 AGP_CBE<2> 18 37
R193 SM1
402 2 402
AGPCBE_3 AL25 AGP_CBE<3> 18 37
1
10K 2
37 18 12 AGP_AD_STB<0>
AGPPAR AT29 AGP_PAR 18 37 5%

1/16W
PCI PULL-UPS AGPFRAME AN28 AGP_FRAME_L 12 18 37 MF
402
R187
AGPTRDY AR29 AGP_TRDY_L 12 18 37 1
10K 2
37 18 12 AGP_AD_STB<1>
+3V_SLEEP SIMPLY PROVIDING REFERENCE TO CHIP AGPIRDY AT28 AGP_IRDY_L 12 18 37 5%

BECAUSE SINGLE AGP PWR PLANE AND CLOSE PROXIMITY OF CHIPS 1/16W
RP17 AGPSTOP AM28 AGP_STOP_L 12 18 37
10K AGPDEVSEL AM27

R230 MF
402
B 39 37 26 24 17 12 PCI_FRAME_L
3 6
AGP_SBA0 AT32
AGP_DEVSEL_L
AGP_SBA<0>
12 18 37
18 37
37 18 12 AGP_SB_STB 1
10K 2 B
5% 5%
1/16W
SM1
RP18 AGP_SBA1 AR32 AGP_SBA<1> 18 37
1/16W
MF
10K AM31 AGP_SBA<2> 402
39 37 26 24 17 12 PCI_DEVSEL_L
1 8 AGP_SBA2 18 37
5%
SERIES RESISTORS FOR BOOTROM CONTROL SIGNALS AGP_SBA3 AN31 AGP_SBA<3> 18 37
RP17 1/16W
SM1 AGP_SBA4 AR31 AGP_SBA<4> 18 37
10K PLACE CLOSE TO INTREPID SIDE AT31 AGP_SBA<5>
39 37 26 24 17 12 PCI_IRDY_L
1 8 AGP_SBA5 18 37
AGP_SBA6 AM30 AGP_SBA<6>

5%
1/16W RP17 AGP_SBA7 AN30 AGP_SBA<7>
18 37
R194
SM1 10K
18 37
1
10K 2
37 18 12 AGP_AD_STB_L<0>
39 37 26 24 17 12 PCI_TRDY_L
2 7 R103 AGP_SB_STB_P AH25 AGP_SB_STB 12 18 37 5%
5%
22 1/16W
RP17 1/16W 12 INT_ROM_CS_L 1 2 ROM_CS_L 9 24 39 AGP_SB_STB_N AG25 AGP_SB_STB_L 12 18 37 MF R170
SM1 402 10K
10K 5%
39 37 26 24 17 12 PCI_STOP_L
4 5 1/16W
MF R77 AGP_ST0 AN29 AGP_ST<0> 18 37 18 12 AGP_AD_STB_L<1> 1 2
5% INT_ROM_OE_L
402
1
22 2 ROM_OE_L
AGP_ST1 AT30 AGP_ST<1> 18 5%
1/16W
12 9 24 39
1/16W
SM1 RP18 5%
AGP_ST2 AR30 AGP_ST<2> 18
R216 MF
402
10K 1/16W 10K
39 24 12 AIRPORT_PCI_REQ_L
2 7 R82 MF
402
AGP_AD_STB0_P AK20 AGP_AD_STB<0> 12 18 37 37 18 12 AGP_SB_STB_L 1 2
5% 1
22 2 AGP_AD_STB0_N AK19 AGP_AD_STB_L<0> 12 18 37 5%
12 INT_ROM_RW_L ROM_RW_L 9 24 39 1/16W
1/16W AK30 AK21
SM1 5% 18 12 AGP_WBF_L AGP_WBF AGP_AD_STB1_P AGP_AD_STB<1> 12 18 37 MF
1/16W 402
AK22 AGP_AD_STB_L<1>
MF AGP_AD_STB1_N 12 18 37
402
AJ29 AGP_PIPE_L
AGPPIPE 12
AK24 AGP_RBF_L
AGPRBF 12 18 37
VSSA_5
(PLL5)
+3V_MAIN V13
RP18
10K
INTREPID AGP/PCI
A 26 12 USB2_PCI_REQ_L
4
5%
5

A
RP18 1/16W
SM1
10K THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
17 12 CBUS_PCI_REQ_L
5% I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1/16W
SM1 II NOT TO REPRODUCE OR COPY IT
USB2 AND CBUS REQ REMAINS ON
+3V_MAIN BECAUSE THESE CHIPS
ARE POWERED IN SLEEP APPLE COMPUTER INC.
D 051-6459 A
SCALE SHT OF
NONE 12 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CLKENET_LINK_TX
TEST PULL-UPS/DOWNS
36 27
V5 UIDE_DATA<0>
ATA_D0
CRITICAL 24 37
T1
U45 ATA_D1
U1
UIDE_DATA<1> 24 37
R630 +3V_MAIN
UIDE_DATA<2> 10 RP16
INTREPID-REV2.1 ATA_D2
24 37
37 27 ENET_PHY_TX_EN 1 2 37 ENET_LINK_TX_EN
U2 UIDE_DATA<3> 10K
BGA ATA_D3 24 37
5%
V4 39 13 JTAG_ASIC_TDI
3 6
(5 OF 9) ATA_D4 UIDE_DATA<4> 24 37 1/16W
MF
V2 UIDE_DATA<5> 402 5%
ATA_D5
W1
24 37
R624 CRITICAL RP16 1/16W
SM1
ATA_D6 UIDE_DATA<6> 24 37
10 H9
TX_CLK U45 10K
V1 37 27 ENET_PHY_TX_ER 1 2 37 ENET_LINK_TX_ER 39 27 13 JTAG_ASIC_TMS
1 8
ATA_D7 UIDE_DATA<7> A7
W2
24 37
5%
TX_EN INTREPID-REV2.1 5%
ATA_D8 UIDE_DATA<8> 24 37 A5 BGA
D ATA_D9 W8
W4
UIDE_DATA<9> 24 37
1/16W
MF
402
ENET_LINK_TXD<0> H10
TX_ER
TXD_0
(4 OF 9)
1/16W
SM1 R117
10K
D
37 13
27 13 JTAG_ENET_TDI 2 1
UATA100 W5 UIDE_DATA<11> 37 13 ENET_LINK_TXD<1> E9
TXD_1 5%
ATA_D11 24 37
ENET_LINK_TXD<2> D8 1/16W
ATA_D12 Y2 UIDE_DATA<12> 24 37
37 13 TXD_2 MF
ENET_LINK_TXD<3> A6 RESET U5 INT_RESET_L 402
Y1 TXD_3
37 13
ENET_LINK_TXD<4> B7 TXD_4
MISC 9 30
R621
ATA_D14 W7 UIDE_DATA<14> 24 37
37 13
PURESET T2 INT_PU_RESET_L 25 30 1
10K 2
ENET_LINK_TXD<5> G10 13 INT_TST_PLLEN_PD
ATA_D15 Y8 UIDE_DATA<15> 24 37
37 13 TXD_5
ENET_LINK_TXD<6> D9 5%
37 13 TXD_6 1/16W
ATA_A0 Y5 UIDE_ADDR<0> 24 37 ENET_LINK_TXD<7> E10
TXD_7
PHY_DATA0 L4 FW_LINK_DATA<0> 28 37 MF RP16
37 13
PHY_DATA1 M4 FW_LINK_DATA<1> 402 10K
ATA_A1 AB1 UIDE_ADDR<1> 24 37
28 37
39 27 13 JTAG_ASIC_TCK 2 7
36 27 CLKENET_LINK_RX
J12 P7 FW_LINK_DATA<2>
ATA_A2 Y7 UIDE_ADDR<2> 24 37 RX_CLK PHY_DATA2 28 37
C4 N5 5%
37 27 ENET_RX_DV RX_DV PHY_DATA3 FW_LINK_DATA<3> 28 37 1/16W
ATA_VREF Y15 UIDE_REF 38
37 27 ENET_RX_ER
D2
RX_ER PHY_DATA4 K1 FW_LINK_DATA<4>
R626 SM1
Y4
28 37
1
1K 2
ATA_RST UIDE_RST_L 24 37
PHY_DATA5 K2 FW_LINK_DATA<5> 28 37
39 27 13 JTAG_ASIC_TRST_L
37 27 ENET_LINK_RXD<0>
D3
UDMA - STOP ATA_WR AA1 UIDE_DIOW_L 24 37 RXD_0 GB ETHERNET L2 FW_LINK_DATA<6> 5%
PHY_DATA6
UDMA - HOSTDMARDY/HSTROBE ATA_RD AA2 UIDE_DIOR_L 24 37
R51 37 27 ENET_LINK_RXD<1>
E7
RXD_1
PHY_DATA7 N4 FW_LINK_DATA<7>
28 37 1/16W
MF RP16
AA5 1
82 2 37 27 ENET_LINK_RXD<2>
D6
RXD_2
28 37 402
10K
UDMA - DEVICEDMARDY/DSTROBE ATA_CHRDY UIDE_IOCHRDY 24 37 HD_DMARQ 24 37
ATA_CS0 AA4 UIDE_CS0_L 5% 37 27 ENET_LINK_RXD<3>

B4 RXD_3 FIREWIRE PHY_LPS M1 FW_PHY_LPS 28
R34 13 INT_JTAG_TEI 4 5
24 37
1/16W A4 P5 1
22 2 5%
AB2 37 27 ENET_LINK_RXD<4> RXD_4 PHY_CTL0 FW_LINK_CNTL<0> 28 37 FW_PHY_LREQ 28 37
ATA_CS1 UIDE_CS1_L 24 37 MF
R629 1/16W
402 D7 L1 SM1
AC1 37 27 ENET_LINK_RXD<5> RXD_5 PHY_CTL1 FW_LINK_CNTL<1> 28 37 5%
1K
ATA_DMACK UIDE_DMACK_L 24 37 1/16W 1 2
ATA_DMARQ AC2 37 UIDE_DMARQ R92 37 27 ENET_LINK_RXD<6>
G9
RXD_6 PHY_LREQ M2 37 FW_LINK_LREQ MF
402
13 INT_TST_MONIN_PD
AA8 1
82 2 37 27 ENET_LINK_RXD<7>
E8
RXD_7 FWR_PCLK T7 CLKFW_LINK_PCLK 28 36
5%
ATA_INTRQ 37 UIDE_INTRQ HD_INTRQ 24 37 1/16W
5%
R124 36 27 CLKENET_LINK_GBE_REF
L13
GBE_REFCLK R145 MF
402
1/16W 10 H12 22
MF 36 27 CLKENET_PHY_GTX 1 2 36 CLKENET_LINK_GTX GTX_CLK FWR_LCLK U14 36 CLKFW_LINK_LCLK 1 2 CLKFW_PHY_LCLK 28 36
+3V_MAIN 402 E6
CS_CE1 AD1 CSLOT_CE1_L_SPN 5%
1/16W
37 27 ENET_CRS CRS FW_LINKON N2 FW_LKON 28 5%
1/16W
C5
CS_CE2 AB4 CSLOT_CE2_L_SPN MF 37 27 ENET_COL COL FW_PINT N1 FW_PINT 28 37 MF
AB5 1
402
37 27 ENET_MDIO
B5
MDIO
402
I2C PULL-UPS
CS_IORD CSLOT_IORD_L_SPN R52 37 27 ENET_MDC
B6 +3V_MAIN
AD2 10K MDC
C CARDSLOT
CS_IOWR
CS_OE AC4
CSLOT_IOWR_L_SPN
CSLOT_OE_L_SPN
5%
1/16W
MF
RP12
2
2.2K
7
C
AE1 CSLOT_WE_L_SPN 39 23 13 11 INT_I2C_CLK0
CS_WE 2 402 39 13 JTAG_ASIC_TDI
AK8 TDI
CS_WAIT AE2 CSLOT_IOWAIT_L_PU AT5 5%
27 13 JTAG_ENET_TDI TDO 1/16W
CS_WAIT IS AN INPUT 39 27 13 JTAG_ASIC_TCK
AP5
TCK
SM1 RP12
AR5 1
2.2K 8
39 27 13 JTAG_ASIC_TMS TMS 39 23 13 11 INT_I2C_DATA0
IDEDD0 AC5 EIDE_DATA<0> 24 37
39 27 13 JTAG_ASIC_TRST_L
AN6
TRSTN TEST IICCLK_0 AN2 INT_I2C_CLK0 11 13 23 39 5%
IDEDD1 AD4 EIDE_DATA<1> 24 37
13 INT_JTAG_TEI
AH10
TEI IICDATA_0 AN1 INT_I2C_DATA0
RP12 1/16W
SM1
AF1 EIDE_DATA<2>
11 13 23 39
2.2K
IDEDD2 24 37
13 INT_TST_MONIN_PD
AM7
TST_MONIN 39 25 14 13 INT_I2C_CLK1 4 5
IDEDD3 AG1 EIDE_DATA<3> 24 37 AK10 AK5
INT_TST_MONOUT_TP TST_MONOUT IICCLK_1 INT_I2C_CLK1 13 14 25 39 5%
IDEDD4 AF2 EIDE_DATA<4> 1/16W
AH1
24 37
13 INT_TST_PLLEN_PD
AR6 TST_PLLEN IICDATA_1 AM3 INT_I2C_DATA1 13 14 25 39 SM1 RP12
IDEDD5 EIDE_DATA<5> 24 37 2.2K
AD5 39 25 14 13 INT_I2C_DATA1 3 6
IDEDD6 EIDE_DATA<6> 24 37
IDEDD7 AG2 EIDE_DATA<7> 24 37

5%
1/16W
IDEDD8 AE4 EIDE_DATA<8> SM1
IDEDD9 AE5 EIDE_DATA<9>

24 37
24 37
ENET_TXD SERIES TERMINATION
AF4
IDEDD10
IDEDD11 AH2
EIDE_DATA<10>
EIDE_DATA<11>
24 37
24 37
ADDR
BUS I2C-0 I2C-1 I2C-2 PMU
IDEDD12 AD7 EIDE_DATA<12>
RP15 (MAIN) (MAIN) (SLEEP) (SLEEP)
24 37
22 A0-WR
IDEDD13 AG4 EIDE_DATA<13> ENET_PHY_TXD<0> 2 7 ENET_LINK_TXD<0> RAM - STANDARD
IDEDD14 AJ1 EIDE_DATA<14>
24 37
24 37
37 27
5%
13 37
A1-RD J20 - PG 12 N/A N/A N/A

IDEDD15 AJ2 EIDE_DATA<15> 24 37
1/16W
SM1 RP14 A2-WR RAM - REVERSED
4
22
5 N/A N/A N/A
IDE IDEA0 AF5 EIDE_ADDR<0> 24 37
37 27 ENET_PHY_TXD<1> ENET_LINK_TXD<1> 13 37
A3-RD J23 - PG 12
AE7 5%
IDEA1 EIDE_ADDR<1> 24 37
RP14 1/16W AC-WR DASH MODEM
N/A
IDEA2 AK1 EIDE_ADDR<2> 24 37
ENET_PHY_TXD<2> 3
22
6
SM1
ENET_LINK_TXD<2> AD-RD N/A N/A J9 - PG 25
AG5 CSLOT_ADDR3_SPN 37 27 13 37
IDEA3
AE-WR BOOTBANG E2PROM
B IDEA4
IDEA5
AH4
AL1
CSLOT_ADDR4_SPN
CSLOT_ADDR5_SPN
5%
1/16W
SM1 RP14
22 AF-RD U37 - PG 23 N/A N/A N/A B
IDEA6 AK2 CSLOT_ADDR6_SPN NOT USING CARDSLOT INTERFACE 37 27 ENET_PHY_TXD<3> 1 8 ENET_LINK_TXD<3> 13 37
84-WR LMU
IDEA7 AH5 CSLOT_ADDR7_SPN 5% N/A N/A N/A
IDEA8 AF7 CSLOT_ADDR8_SPN RP14 1/16W
SM1
85-RD U36 - PG 23
IDEA9 AG7 CSLOT_ADDR9_SPN 2

22
7 58-WR FAN CONTROLLER
N/A
37 27 ENET_PHY_TXD<4> ENET_LINK_TXD<4> 13 37
59-RD N/A U3 - PG 24 N/A
IDECHRDY AK4 EIDE_IOCHRDY 24 37
5%
IDECS0 AB7
1/16W
RP15 6A-WR SNAPPER SOUND
EIDE_CS0_L 24 37
SM1
22 N/A N/A N/A
IDECS1 AM1 EIDE_CS1_L 24 37 37 27 ENET_PHY_TXD<5> 3 6 ENET_LINK_TXD<5> 13 37 6B-RD J12 - PG 24
IDERST AJ4 EIDE_RST_L RP15 5%

1/16W D0-WR CLOCK SLEW SSCG
N/A
IDEWR AM2 EIDE_WR_L
24 37
24 37
22 SM1
D1-RD N/A U56 - PG 15 N/A
37 27 ENET_PHY_TXD<6> 1 8 ENET_LINK_TXD<6> 13 37
IDERD AL2 EIDE_RD_L 24 37
5%
IDEDMACK AG8 EIDE_DMACK_L 24 37 1/16W
RP15 ADDR LSB INDICATES READ (’1’) OR WRITE (’0’) MODES
AH7 SM1
IDEDMARQ EIDE_DMARQ 24 37 22
AA7 37 27 ENET_PHY_TXD<7> 4 5 ENET_LINK_TXD<7> 13 37
IDEINTRQ EIDE_INT 24 37
5%
1/16W
SM1
JTG_RSTN_L TST_TEI_H JTG_TDO_H JTG_TDI_H TST_PLLEN_H ANALYZER_CLK

(I/O) (I/O) DESCRIPTION
1
R154 1 X X X X X JTAG MODE
1K
1% EXTPLL DDR_
1/16W
MF 0 0 SHUTDOWN TPDENABLE 0 (OUTPUT) NORMAL OPERATION INT - ENET/FW/UATA
2 402 (OUTPUT) (OUTPUT)
SELECTED
0 0 (OUTPUT) 0(I) 1 PLL OUTPUTS VIEW PLLS (SOFTWARE) EIDE/I2C
A 0 0
HWPLL_
TESTSEL5
(INPUT)
1(I) 1 SELECTED
PLL OUTPUTS VIEW PLLS (HARDWARE) NOTICE OF PROPRIETARY PROPERTY
A
SYNC/MEM DATA
0 1 0(I) 0(I) MEMWE BYPASS ATPG NORMAL THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
0 1 0(I) 1(I) 0 X(I) ATPG IDDQ I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
0 1 0(I) 1(I) 1 X(I) TEST TRI-STATE III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
FUNCTIONAL TEST WITHOUT
0 1 1(I) 0(I) 0 X(I) POSTSCALAR BYPASS SIZE DRAWING NUMBER REV.
0 1 1(I) 0(I) 1 X(I) FUNCTIONAL

POSTSCALAR
TEST WITH
BYPASS
APPLE COMPUTER INC.
D 051-6459 A
0 1 1(I) 1(I) X X(I) FUNCTIONAL TEST IDDQ SCALE SHT OF
NONE 13 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+2_5V_MAIN NO STUFF +1_5V_INTREPID_PLL 8 12 38
R244
4.7
R291 CRITICAL
1 2 +1_5V_INTREPID_PLL8 38
USB PORT ASSIGNMENTS
1
0 2
5%
1/16W
5%
U7 C424 1 R278 1 C353 1 MF
402 PORT A - RIGHT USB 1
1/16W LT1962-ADJ 15.8K 0.22UF
MF MSOP 0.01UF 1% 20%
8 20% 6.3V INTREPID_USB
+1_8V_MAIN
603 38 LTC1962_INT_VIN IN OUT 1 16V 1/16W CERM 2 R168
CERM 2 MF
402 2 402 4.7 R89
+3V_SLEEP R264 NC 7 NC 402 1 C419 1 2 +1_5V_INTREPID_PLL4 38
26 14 USB_DAP 1
24 2 USB_D2P
0 ADJ 2 LT1962_INT_ADJ 10UF 5%
26
1 2 C433 1 NC 6 NC 20%
6.3V
2 CERM C200 1
1/16W
MF
INTREPID_USB 5%
1/16W
5% 1UF 402 R80 MF
RP29 1/16W 20%
10V BYP 3 LT1962_INT_BYP R2771 805 0.22UF
20% 24 402
10K MF CERM 2 5 GND 4 68.1K 6.3V USB_DAM 1 2 USB_D2M
4 5 603 SHDN CERM 2 R156 26 14 26
D 5%
1/16W
AIRPORT_PCI_INT_L 14 24 39 603 1%
1/16W
MF
402
1
4.7 2 +1_5V_INTREPID_PLL3 38 +3V_MAIN 1
NEC_USB
R699 R707 1
NEC_USB
5%
1/16W
MF
D
402 2 402
SM1 5% 10K 10K
1/16W 5% 5%
+3V_MAIN C182 1 MF
402
1/16W 1/16W
0.22UF
20%
MF
2 402
MF
2 402
PORT B - UNUSED
R7 6.3V
CERM 2 R125 2 RP48
2
10K 1 USB_PWREN_EF_L
402 4.7 10K
14 1 2 +1_5V_INTREPID_PLL2 38 14 USB_DBP
6 3
R113 5%
1/16W 5%
1/16W
L1 5%
1/16W
10K MF
402 C148 1 MF FERR-EMI-100-OHM SM1 RP7
2 1 USB_OC_EF_L 402 SM
14
0.22UF 10K
5% 20% 14 USB_DBM
5 4
1/16W RP47 6.3V
CERM 2 R155
MF
402 8
10K 1
402 4.7 1 5%
1/16W
USB_OC_AB_L 14 1 2 +1_5V_INTREPID_PLL1 38 SM1
RP47 5%
1/16W
USB POWER FAULT SIGNALS 5% 38 +3V_INTREPID_USB PORT C - LEFT USB
6
10K 3 SM1 C198 1 1/16W
MF
USB_PWREN_CD_L 14 402
0.22UF INTREPID_USB
5%
1/16W
RP7 20%
6.3V
1 C84 1 C85 1 C97 R614
SM1 10K CERM 2 0.01UF 0.1UF 10UF 24
1 8 USB_PWREN_AB_L +3V_MAIN +2_5V_MAIN 402 20% 20% 20%
14
16V USB_DCP 1 2 USB_D1P
2 CERM 2 10V
CERM 2 6.3V
CERM
26 14 26
RP47 5% 402 402 805 INTREPID_USB 5%
VDD15A_1 AA16
VDD15A_2 AJ12
VDD15A_3 AJ17
VDD15A_4 AJ18
VDD15A_8 AG29
1/16W
10K SM1 R609 1/16W
VDDU33_1 T8
VDDU33_2 U8
7 2 USB_OC_CD_L MF
14
1 1 USB_DCM 1
24 2
402
USB_D1M
26 14 26
PCI_
(PLL1)
PCI_
(PLL2)
PCI_
(PLL3)
PCI_
(PLL7)
(PLL9)
5% SSCG NEC_USB NEC_USB
1/16W RP48 SSCG SSCG 5%
SM1
1
10K 8
C698 1
L22 L18 1
R701 1
R708 1/16W
MF
USB2_PCI_INT_L 14 26 0.1UF 10K 10K 402
20% 400-OHM-EMI 400-OHM-EMI
RP6 5%
1/16W
10V
CERM 2
SM-1 SM-1 5%
1/16W
5%
1/16W
PORT D - UNUSED
10K SM1 402 CRITICAL MF MF
4 5 INT_EXTINT14_PU 14
2 402 2 402
5% RP29 2 2 U45 SCCTXDA AF9 COMM_TXD_L 25 39
1/16W INTREPID-REV2.1 SCCRTSA AN3 COMM_RTS_L RP46
C SM1 2
10K
7 INT_EXTINT8_PU 14
+3V_CG_PLL_MAIN
SSCG SSCG
38
BGA
(6 OF 9) SCCDTRA AF10 COMM_DTR_L
25 39
25 39
14 USB_DDP
7
10K 2
C
RP6 5%
1/16W 39 30 26 24 20 18 17 MAIN_RESET_L
1 C692 1 C691 SCCRXDA AG11 COMM_RXD 25 39
5%
10K SM1 1UF 0.1UF SCCGPIOA AG9 COMM_GPIO_L 25 39 RP46 1/16W
2 7 1
INT_GPIO1_PU 14 34
R638 20%
10V
20%
10V 14 CG_FSEL
G5 GPIO0 VIA SCCTRXCA AT4 COMM_TRXC 25 39 10K SM1
5%
1/16W
RP51 NO STUFF 5%
10K 2 CERM
603
2 CERM
402 34 14 INT_GPIO1_PU
E1 GENERAL
GPIO1 VCORE_A/B PURPOSE
SEL
14 USB_DDM
8 1
SM1 10K SSCG 1/16W MISO SCCTXDB AR4 PMU_FROM_INT 30 5%

2 7 COMM_RING_DET_L 14 25 30 39
R6311 R6251 MF
2 402 R698
39 25 COMM_SHUTDOWN
J7
GPIO2 I/O’S
REQ* SCCRTSB AL5 PMU_REQ_L 14 30
1/16W
SM1
RP47 5%
1/16W
0
5%
10K 38 +2_5V_CG_MAIN 0
39 25 COMM_RESET_L
F2 GPIO3
MOSI SCCRXDB AG10 PMU_TO_INT 30
5
10K 4 SM1 1/16W 5%
1/16W 28 FW_PHY_PD 1 2 14 FW_PHY_PD_INT J8
GPIO4 PORT E - BLUETOOTH
INT_GPIO15_PU 14 MF MF SSCG H5 ACK* SCCGPIOB AP4 PMU_ACK_L 30
5% RP46 402 2 402 2

NO STUFF 1 C686
5%
1/16W
25 SND_HP_MUTE_L
L9
GPIO5
SCK SCCTRXCB AM5 PMU_CLK 30
R67
1/16W 10K MF 25 SND_AMP_MUTE_L GPIO6 22
SM1 1 0.1UF 402 USB_DEP 1 2 BT_USB_DP
3 6 INT_MOD_CLKOUT_UF 14 R682 20% 14 INT_GPIO9_PU
H4
GPIO9 USB_VD0_P L8 USB_DAP 14 26
37 14 24 37 39
VDD1 10
VDDA 12
VDDQ 18
10K 10V 5%
VDD0 1
VDDC 5
2 CERM J5
RP51 5% 5% 39 25 14 SND_HW_RESET_L GPIO11 USB_VD0_N L7 USB_DAM 14 26
R50 1/16W
MF
1/16W 1/16W 402 K8
10K SM1 MF 14 INT_GPIO12_PU GPIO12 22 402
4 5 PMU_INT_L 14 USB_VD1_P G2 USB_DBP 14 37 14 USB_DEM 1 2 BT_USB_DM 24 37 39
30
2 402 14 INT_GPIO15_PU
F1
GPIO15
5% RP51 CRITICAL K7 USB_VD1_N G1 USB_DBM 14 5%
27 INT_ENET_RST_L GPIO16 1/16W
1/16W
SM1 1
10K 8
U42 SSCG
USB_PRTPWR0 J4 USB_PWREN_AB_L 14
MF
402
CBUS_INT_L 14 17
CY28512D R634 39 30 25 14 COMM_RING_DET_L
F33 EXTINT0 K4 USB_OC_AB_L
RP29 5%
1/16W
36 14 INT_REF_CLK_OUT 20 CLKIN TSSOP
SSCG CPU0 16 CG_CLKOUT 1
33 2 INT_REF_CLK_IN 14 30 14 PMU_INT_L
E34
EXTINT1
USB_PWRFLT0 14
PORT F - MODEM
10K 36
1 8 SM1
PMU_INT_NMI 14 30 14 CG_FSEL 3 FSEL OUTPUT IMPEDANCE ~18-20OHM 5% 18 AGP_INT_L
C33
EXTINT2 USB_VD2_P H2 USB_DCP 14 26 R91
INTERNAL 250K PULL-UP 1/16W
14 INT_EXTINT3_PU
D34
EXTINT3 USB_VD2_N H1 USB_DCM 22
5%
1/16W
RP1 39 25 13 INT_I2C_CLK1 9 SCLK
MF
402 B33
14 26
37 14 USB_DFP 1 2 MODEM_USB_DP 25 37 39
10K 39 25 SND_LIN_SENSE_L EXTINT4 5%
SM1 1 8 USB_VD3_P M7 USB_DDP
PMU_REQ_L 14 30
39 25 13 INT_I2C_DATA1 8 SDATA 27 ENET_ENERGY_DET
A33
EXTINT5
USB_VD3_N M8 USB_DDM
14
R90 1/16W
MF
RP46 5% 39 24 14 AIRPORT_PCI_INT_L
E31
EXTINT6 USB 14
1
22 2
402
1/16W 37 14 USB_DFM MODEM_USB_DM 25 37 39
10K SM1 CG_ADDRSEL 14 ADDRSEL INTERNAL 250K PULL-DOWN G30 INTERRUPTS J2
17 14 CBUS_INT_L EXTINT7 USB_PRTPWR1 USB_PWREN_CD_L 14 5%
4 5 INT_MOD_DTO_UF 14 SSCG D31 J1 1/16W
14 INT_EXTINT8_PU EXTINT8 POWERBOOK SPARE USB_PWRFLT1 USB_OC_CD_L 1 1
RP48 CG_RESET_L 17 RESET* 14 MF
R114 R115
5%
1/16W
10K
R281 30 14 PMU_INT_NMI
C32
EXTINT9 RP8 402
15K 15K
SM1 13 PD* 0 USB_VD4_P K5 USB_DEP 14 37 47
B 4 5 INT_GPIO12_PU 14
30 14 SYSTEM_CLK_EN
38 34 14 VCORE_VGATE 1
5%
2 14 INT_EXTINT10_PU
14 INT_EXTINT11_PU
B32
E30
EXTINT10
EXTINT11
VGATE/LOCK INTERRUPT
USB_VD4_N L5 USB_DEM 14 37
2 7 SND_TO_AUDIO 25 39
5%
1/16W
MF
5%
1/16W
MF
B
RP51 5%
1/16W
CG_LOCK 2 LOCK OPEN-DRAIN OUTPUT
2
SSCG
1/16W
J9
CBUS_IREQ_L
P8
5%
1/16W RP8 402 2 2 402
3
10K 6 SM1
INT_EXTINT3_PU
SSCG 4 ODSEL INTERNAL 250K PULL-UP
R100 MF
402
14 INT_EXTINT12_PU
F4
EXTINT12 FAN PWM USB_VD5_P USB_DFP 14 37
SM1 47
14 75 14 INT_EXTINT13_PU EXTINT13 BRIGHTNESS PWM USB_VD5_N N8 USB_DFM 3 6
RP6 R636 14 37 SND_SYNC 25 39
VSS0
VSS1
VSSA
VSSC
VSSQ
5% NO STUFF 5% D1
0 1 1/16W 14 INT_EXTINT14_PU EXTINT14 CONTRAST PWM
1/16W
SM1 3
10K
6 38 34 14 VCORE_VGATE 1 2 R656 MF
39 25 SND_HP_SENSE_L
E2
EXTINT15
USB_PRTPWR2 M5 USB_PWREN_EF_L 14
RP8 5%
1/16W
INT_EXTINT13_PU 14 10K 1 402 N7 SM1
5% 5% 14 INT_EXTINT16_PU
H7 USB_PWRFLT2 USB_OC_EF_L 14 47
1/16W PLACE R68 CLOSE TO INTREPID SIDE EXTINT16 4 5 SND_SCLK
7
19
11
15
RP48 5%
1/16W MF
1/16W
MF OTHERWISE A LOT OF OVERSHOOT/UNDERSHOOT 26 14 USB2_PCI_INT_L
G4
EXTINT17
25 36 39
10K SM1 402

2 402 AUD_DTO R4 INT_SND_TO_AUDIO 5%
2 7 INT_EXTINT16_PU 14 5 MPIC_CPU_INT_L
D30
CPU_INT
AUD_DTI R7 INT_AUDIO_TO_SND
1/16W
SM1 RP8
25 39
47
5%
1/16W RP29 30 26 PMU_PME_L
AJ7
PCIPME AUD_SYNC T5 INT_SND_SYNC 1 8 SND_CLKOUT 25 36 39
SM1 10K 30 INT_PROC_SLEEP_REQ_L
AT6 P2 INT_SND_SCLK
NO STUFF PROCSLEEPREQ AUD_BITCLK RP56 5%
AN8 R5 1/16W
R49 30 INT_PEND_PROC_INT PENDPROCINT AUD_CLKOUT INT_SND_CLKOUT 47 SM1
RP24 5%
1/16W 0 AUDIO/I2S
2 7 MOD_DTO 25 39
10K SM1 36 CLK18M_INT_EXT 1 2 36 CLK18M_INT_XIN U4
XTAL_IN MOD_DTO R2 14 INT_MOD_DTO_UF HWPLL_
SIGNAL NAME
5% NO STUFF 36 CLK18M_INT_XOUT V15
XTAL_OUT MOD_DTI T4 INT_MOD_DTI 25 39
RP56 5%
1/16W TESTMUXSEL
5% 1/16W 47 SM1
5 MOD_BITCLK_B_H
1/16W RP7 CRITICAL MF
402
R622 30 14 SYSTEM_CLK_EN
AN7
STOPXTAL CLOCKS MOD_SYNC R1 14 INT_MOD_SYNC_UF 3 6 MOD_SYNC 25 39
SM1 10K 10M V8 14 INT_MOD_BITCLK_UF 4 MOD_CLKOUT_B_H
NO STUFF 2 1
AT7
MOD_BITCLK
P1
5%
1/16W RP56
J1 5% 30 INT_WATCHDOG_L WATCHDOG MOD_CLKOUT 14 INT_MOD_CLKOUT_UF SM1 47 3 MOD_DTO_B_H
RP6 5%
1/16W U.FL-R_SMT
1/16W
MF
1
R632 1 8 MOD_BITCLK 25 39
10K SM1 F-ST-SM NO STUFF 402 0 +3V_SLEEP 5% 2 MOD_SYNC_B_H
1 8 INT_GPIO9_PU 14 3 1
R28 CRITICAL 5%
1/16W 36 14 INT_REF_CLK_OUT
U15
BUF_REF_CLK_OUT RP56 1/16W
SM1 1 MOD_DTI_B_H
47
5%
1/16W 5%
51 Y1 MF
2 402
36 14 INT_REF_CLK_IN
K9
SS_REF_CLK_IN 4 5 MOD_CLKOUT 25 39
0 JTG_TDO_H
SM1 1 1/16W 18.432M
1 2
MF IICCLK_2 AL4 5%
1/16W
R720 2
2 402
8X4.5MM-SM
CLK18M_XTAL_IN 36 IIC
IICDATA_2 AH8 2
R29 2
R102 SM1
10K
1
5%
1/16W
2
RP1
FW_PHY_PD_INT 14
CRYSTAL LOAD CAPACITANCE IS 16PF

C15 1
22PF
1 C140
22PF
5%
1K
1/16W
5%
1K
1/16W
INT - USB/GPIOS/I2S
A
(PLL1)
(PLL2)
(PLL3)
(PLL7)
VSSA_8
(PLL9)
VSSU_1
VSSU_2
MF MF
MF 10K 5% 5%
A
VSSA1
VSSA2
VSSA3
VSSA4
402 3 6
50V 50V 1 402 1 402
INT_MOD_DTI_UF CERM 2 2 CERM
402 402
5%
RP1 1/16W
SM1
10K INT_I2C_CLK2 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AA15
AJ13
AJ16
AK18
AH29
R9
R8
25 39
2 7 INT_MOD_BITCLK_UF 14 AGREES TO THE FOLLOWING
INT_I2C_DATA2 25 39
5%
1/16W
RP1 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
SM1 4
10K 5 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_5_HEAD

INT_MOD_SYNC_UF 14
TABLE_5_ITEM TABLE_ALT_HEAD
5%
R111 1/16W 116S1104 1 RES,METAL FILM,10 K OHM,5,1/16W,0402,SM R100 NO_SSCG PART NUMBER ALTERNATE FOR
PART NUMBER
BOM OPTION REF DES COMMENTS:
100K 2 SM1
1
5%
1/16W
SND_HW_RESET_L 14 25 39
197S0004 197S0035 Y1 ALT FOR SIWARD
TABLE_ALT_ITEM
APPLE COMPUTER INC.

D 051-6459 A
MF SCALE SHT OF
402
NONE 14 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+2_5V_MAIN
+2_5V_SLEEP
NO STUFF
R2871 1
R399 38 21 19 18 16 12 +1_5V_AGP
0 0
5% 5%
1/10W 1/10W +3V_MAIN
FF FF +1_5V_MAIN
805 2 2 805
38 34 23 16 8 7 5 MAXBUS_SLEEP
38 16 10 9 +2_5V_INTREPID
D D
AD20
AE20
AE23
AF22
AH19
AH22
AH28
AJ21
AJ23
AL19
AL22
AL28
AL30
AN32
AP19
AP22
AP25
AP28
AP31
AR33
AR34
AA11
AA12
AC12
AC13
AC14
AD21
AE15
AE17
AF25
AL10
AB3
AB6
F30
AE3
AE6
AH3
AH6
AK6
F7
F9
G3
G6
AA25 AGP_IO_VDD VDD3.3 AL13
C12 AA29 AL16
C15 AB25 AL3
C18 AB27 AL7
C21 U45 AB31 AM4
C24
INTREPID-REV2.1 AB34
BGA AN5
C27 (8 OF 9) AC25 AA21 AP10
C30 AC27 AA24
U45 AP13
C9 AC28 AB13
INTREPID-REV2.1 AP16
BGA
F12 AE31 AB15 (9 OF 9) K3
F15 AE34 AB17 K6
F18 AF28 AB19 N24
F21 AH30 AC17 N3
F24 AH34 AC19 N6
F27 VDD1.8/CPUVIO AK34 AC23 P13
M15 AP35 AD13 P14
M16 C35 AD15 POWER R22
M19 G31 AD22 T12
M22 G34 P15 T18
M23 K31 P18 T3
N18 K34 P20 VDD3.3 T6
N21 N28
VDD2.5 P21
VDD1.5 U12
N23 N31 R17 W12
P16 N34
C P19 N36
R20
T13
W13
W3
C
P25 U17 W6
P28
POWER/GROUND U18 AP2
R25 U24 AP7
R27 V16 AR3
T25 V19 B3
T28 V20 C2
T29 V22 C6
T31 W16 D32
T34 W24 D5
U25 Y13 B34
U28 Y18 E4
L24 V25
M14 V29
M17 W25
M18 W31
M20 W34
M21 Y27
M24 Y29 AD28
M28 E33 AD3
M3 AD31
M31 AN33 AD34
M32 AN4 AD6

AE14
GROUND
M34 AP1
M6 AP12 AE16
M9 AP15 AE18
B N15
N25
AP18
AP21
AE19
AE21 U19
B
P12 AP24 AE22 U22
P17 AP27 AE28 U27
P22 AP3 AG21 U29
P29 AP30 AG23 V10
P4 AP33 AG24 V12
R14 AP34 AG3 V17

VSS AG30 V18
R16 AP36
AG34 VSS V21
R18 AP6
R19 AP9 AG6 V24
VSS AH20
R21 AR2 V3
R23 AR35 AH21 V31
R24 AT3 AH23 V34
R26 AT34 AH27 V6

VSS W11
R29 B2
R3 B35 AK3 W14
R31 C1 AK7 W23
R34 C10 AL12 W26
R6 C13 AL15 Y11
T11 C16 AL18 Y12
T14 C19 AL21 Y14
T23 C22 AL27 Y16
T24 C25 AL31 Y19
T27
U10
C28
C3
AL34
AL6
Y23
Y24 Intrepid Power
A U16 C31 AL9 Y25
A
C34
AGP_IO_VSS
A3
A34
AA20
AA27
AA3
AA31
AA34
AA6
AB11
AB12
AB14
AB16
AB18
AB24
AB28
AB29
AC11
AC15
AC16
AC18
AC20
AC22
AC26
AD12
AD23
AD25
J6
J34
J31
J3
G7
F6
F34
F31
F3
F28
F25
F22
F19
F16
F13
F10
D4
D33
C7
C36

APPLE COMPUTER INC.

D 051-6459 A
SCALE SHT OF
NONE 15 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+1_5V_MAIN
24 Balls 30 Balls
38 34 23 15 8 7 5 MAXBUS_SLEEP
INTREPID MAXBUS DECOUPLING 4 X 10UF (0805) 4 X 10UF (0805)
32 X 0.22UF (0402) INTREPID CORE DECOUPLING 29 X 0.22UF (0402)
C204 1 C348 1 1 C239 1 C240 1 C350 1 C312 1 C176 1 C288 1 C313 1 C94 1 C286 1 C158 C128 1 C101 1 1 C147 1 C243 1 C262 1 C242 1 C227 1 C181 1 C142 1 C215 1 C278 1 C264
10uF 10uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 10uF 10uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 2 6.3V 2 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 6.3V 2 6.3V 2 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM
805 805 402 402 402 402 402 402 402 402 402 402 805 805 402 402 402 402 402 402 402 402 402 402
D C236 1 C196 1 1 C174 1 C206 1 C259 1 C237 1 C238 1 C95 1 C117 1 C241 1 C260 1 C314 C157 1 C315 1 1 C244 1 C212 1 C178 1 C179 1 C177 1 C159 1 C161 1 C162 1 C280 1 C279 D
10uF 10uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 10uF 10uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 2 6.3V 2 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 6.3V 2 6.3V 2 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM
805 805 402 402 402 402 402 402 402 402 402 402 805 805 402 402 402 402 402 402 402 402 402 402
1 C173 1 C171 1 C175 1 C226 1 C172 1 C207 1 C118 1 C287 1 C119 1 C349 1 C144 1 C246 1 C211 1 C263 1 C180 1 C213 1 C197 1 C208 1 C214
0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
+3V_MAIN
1 C205 1 C209
0.22uF 0.22uF 57 Balls
20% 20%
6.3V 6.3V
4 X 10UF (0805)
2 CERM
402
2 CERM
402 INTREPID 3.3V DECOUPLING 72 X 0.22UF (0402)
38 21 19 18 15 12 +1_5V_AGP
C164 1 C395 1 1 C375 1 C351 1 C53 1 C42 1 C21 1 C185 1 C31 1 C143 1 C123 1 C121
21 Balls 10uF 10uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
INTREPID AGP I/O DECOUPLING 4 X 10UF (0805) 6.3V 2

CERM
6.3V 2
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
805 805 402 402 402 402 402 402 402 402 402 402
24 X 0.22UF (0402)
C371 1 C231 1 1 C356 1 C297 1 C268 1 C217 1 C355 1 C267 1 C250 1 C298 1 C377 1 C216 C10 1 C9 1 1 C33 1 C184 1 C43 1 C35 1 C261 1 C60 1 C52 1 C199 1 C57 1 C19 C
C 10uF
20%
10uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
10uF
20%
10uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
CERM 2 CERM 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM CERM 2 CERM 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
805 805 402 402 402 402 402 402 402 402 402 402 805 805 402 402 402 402 402 402 402 402 402 402
C281 1 C394 1 1 C228 1 C230 1 C265 1 C378 1 C357 1 C229 1 C325 1 C393 1 C324 1 C323 1 C16 1 C108 1 C55 1 C32 1 C125 1 C45 1 C76 1 C277 1 C28 1 C26
10uF 10uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
CERM 2 CERM 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
805 805 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
1 C251 1 C266 1 C249 1 C34 1 C23 1 C120 1 C146 1 C141 1 C30 1 C145 1 C96 1 C54 1 C50
0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402 402 402 402
1 C75 1 C122 1 C51 1 C59 1 C163 1 C126 1 C98 1 C109 1 C56 1 C27
38 15 10 9 +2_5V_INTREPID 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF
44 Balls 20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
INTREPID DDR DECOUPLING 4 X 10UF (0805)
51 X 0.22UF (0402)
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
B 10uF
20%
6.3V
10uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
B
CERM 2 CERM 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
805 805 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
10uF 10uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 2 6.3V 2 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM
805 805 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
1 C321 1 C318 1 C399 1 C410 1 C335 1 C369 1 C384 1 C294 1 C406 1 C405
0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
6.3V
2 CERM
402 402 402 402 402 402 402 402 402 402
1 C404 1 C400 1 C386 1 C289 1 C387 1 C401 1 C354 1 C389 1 C309 1 C398
0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402 402 402 402 402 402 402 402 402 402
1 C337 1 C290 1 C402 1 C397 1 C368 1 C334 1 C388 1 C293 1 C319 1 C336
Intrepid Decoupling
A 0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20% NOTICE OF PROPRIETARY PROPERTY
A
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1 C316 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
0.22uF
20%
6.3V
2 CERM SIZE DRAWING NUMBER REV.
402
APPLE COMPUTER INC.

D 051-6459 A
SCALE SHT OF
NONE
16 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCI1510 PULL-UPS +3V_MAIN

39 30 26 24 20 18 17 14 MAIN_RESET_L
THIS PROPERLY SHUTS DOWN
CARDBUS POWER FOR PSUEDO-D3COLD
+3V_MAIN
+3V_MAIN
1 C813 1 C795 1 C798 1 C790 1
R348
10UF 0.22UF 0.22UF 0.22UF 47
20% 20% 20% 20%
R757 6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM 5%
1/16W
+5V_MAIN MAKE SURE VCC AND VPP ARE WIDE PLANE/TRACES
10K
D
1
5%
2 CBUS_PCI_PERR_L 17
805 402 402 402 MF
2 402
U19 TO MINIMIZE INDUCTANCE! D
R756 1/16W
MF NO STUFF TPS2211
10K 402 NC 9
V_12 SSOI AVPP
10 +VPP_CBUS_SW 17 38
1 2 CBUS_PCI_SERR_L 17
R3731 5
V_5_1
5% 1 C796 1 C797 1 C791 10K 6 11
1/16W
MF R753 0.22UF 0.22UF 0.22UF 5%
1/16W V_5_2 AVCC0 +VCC_CBUS_SW 17 38
402 10K 20% 20% 20% MF 3

V_3_1 AVCC1
12
1 2 CBUS_SUSPEND_PU 17
2 6.3V 2 6.3V 2 6.3V
CERM 402 2
CERM CERM 4 13
5% 402 402 402 V_3_2 AVCC2
1/16W
MF
402 R7621 1
VCCD0 C773 1 1 C467
10K 2 0.1UF 0.1UF
5% VCCD1 CRITICAL 20%
10V
20%
10V
1/16W 15
VPPD0 CERM 2 2 CERM
MF 402 402
+2_5V_MAIN 402 2 14
VPPD1
TPS2211_SHDN_L_PU 16
A7 C13 D5 E1 M1 N7 N11
SHTDWN
7 8 NC
GND OC
VCC
1 C789
0.22UF H10 CRITICAL B11
0.1UF ARE USED TO INCREASE ESD DISCHARGES OF UP TO 10KV
20%
6.3V
NC CLK_48_RSVD/NC CLAMP FOR PC-CARD VCCCB
2 CERM CLAMP FOR PCI VCCP L3
402 PCI1510_VR_EN_L D4
VR_EN* U26
L8 VR_PORT PCI1510GGU VCCD0* N13 CBUS_VCCD0_L
BGA
VCCD1* L12 CBUS_VCCD1_L
39 37 26 24 12 9 PCI_AD<0> N8 AD0
39 37 26 24 12 9 PCI_AD<1>
39 37 26 24 12 9 PCI_AD<2>
M7
L7
AD1
AD2
VPPD0
VPPD1
K9
M11
CBUS_VPPD0
CBUS_VPPD1
PC CARD/CARDBUS CONNECTOR
39 37 26 24 12 9 PCI_AD<3> N6 AD3 L13
CRITICAL
K4 AD4 CD1*/CCD1* CBUS_DET_1_L 17 39
39 37 26 24 12 9 PCI_AD<4>
CD2*/CCD2* B5 CBUS_DET_2_L 17 39
J9
39 37 26 24 12 9 PCI_AD<5> M6 AD5 F12
QT500806-L111
IORD*/CAD13 CBUS_IORD_L 17 M-ST-SM1
39 37 26 24 12 9 PCI_AD<6>
L6 AD6
C 39 37 26 24 12 9 PCI_AD<7>
39 37 26 24 12 9 PCI_AD<8>
N5
N4
AD7
AD8
IOWR*/CAD15
OE*/CAD11
C11
G10
CBUS_IOWR_L
CBUS_OE_L
17
17
84 81
C
CE1*/CC/BE0* H13 CBUS_CE1_L 17
2 1 CBUS_DATA<3> 17
39 37 26 24 12 9 PCI_AD<9> M2 AD9 4 3
M5
VS1*/CVS1 B2 CBUS_VS1 17 39 17 CBUS_DET_1_L CBUS_DATA<4> 17
39 37 26 24 12 9 PCI_AD<10> AD10 VS2*/CVS2 A9 CBUS_VS2 17 17 CBUS_DATA<11>
6 5 CBUS_DATA<5> 17
39 37 26 24 12 9 PCI_AD<11> L4 AD11 WE*/CGNT* D13 CBUS_WE_L 17 17 CBUS_DATA<12> 8 7 CBUS_DATA<6> 17
N3
39 37 26 24 12 9 PCI_AD<12> AD12 RDY/IREQ*/CINT* A6 CBUS_READY 17 17 CBUS_DATA<13>
10 9
K5
39 37 26 24 12 9 PCI_AD<13> AD13 RESET/CRST* D8 CBUS_RESET_L 17
12 11 CBUS_DATA<7> 17
39 37 26 24 12 9 PCI_AD<14> L5 AD14 REG*/CC/BE3* A8 CBUS_REG_L 17 17 CBUS_DATA<14> 14 13 CBUS_CE1_L 17
M4
39 37 26 24 12 9 PCI_AD<15> AD15 BVD1/CSTSCHG/STSCHG*/RI* C6 CBUS_BVD1_L 17 17 CBUS_DATA<15>
16 15 CBUS_ADDR<10> 17
39 37 26 24 12 9 PCI_AD<16> J4 AD16 BVD2/SPKR*/CAUDIO D6 CBUS_BVD2_L 17 17 CBUS_CE2_L
18 17 CBUS_OE_L 17
H1
39 37 26 24 12 9 PCI_AD<17> AD17 INTEGRATED PULL-UP WP/IOIS16*/CCLKRUN* A5 CBUS_WP_L 17 17 CBUS_VS1 20 19
H3
39 37 26 24 12 9 PCI_AD<18> AD18 CE2/CAD10* G13 CBUS_CE2_L 17 22 21 CBUS_ADDR<11> 17
PCI_AD<19> H2 AD19 INPACK/CREQ* B8 CBUS_INPACK_L 17 17 CBUS_IORD_L
24 23 CBUS_ADDR<9> 17
G2
39 37 26 24 12 9 PCI_AD<20> AD20 WAIT/CSERR* B6 CBUS_WAIT_L 17 17 CBUS_IOWR_L
26 25 CBUS_ADDR<8> 17
G4
39 37 26 24 12 PCI_AD<21> AD21 17 CBUS_ADDR<17>
28 27 CBUS_ADDR<13> 17
39 37 26 24 12 PCI_AD<22> F1 AD22 A0/CAD26 C7 CBUS_ADDR<0> 17
30 29
17 CBUS_ADDR<18>
C3 A1/CAD25 D7 CBUS_ADDR<1>
39 37 26 24 12 PCI_AD<23> AD23 17
32 31 CBUS_ADDR<14> 17
F3 A2/CAD24 B7 CBUS_ADDR<2>
39 37 26 24 12 9 PCI_AD<24> AD24 17
17 CBUS_ADDR<19>
34 33 CBUS_WE_L 17
39 37 26 24 12 9 PCI_AD<25> E2 AD25 A3/CAD23 D10 CBUS_ADDR<3> 17
36 35
17 CBUS_ADDR<20> CBUS_READY 17
39 37 26 24 12 9 PCI_AD<26> F4 A4/CAD22 B12 CBUS_ADDR<4>
AD26 17
17 CBUS_ADDR<21>
38 37 +VCC_CBUS_SW 17 38
B1 A5/CAD21 C8 CBUS_ADDR<5> TI REFERENCE SCHEMATIC DID NOT HAVE BULK ON +VCC_CBUS_SW
39 37 26 24 12 9 PCI_AD<27> AD27 17
38 17 +VCC_CBUS_SW 40 39
D2 A6/CAD20 C9 CBUS_ADDR<6>
39 37 26 24 12 9 PCI_AD<28> AD28 17
42 41 +VPP_CBUS_SW 17 38
E4 A7/CAD18 A12 CBUS_ADDR<7>
39 37 26 24 12 9 PCI_AD<29> AD29 17
38 17 +VPP_CBUS_SW 44 43 CBUS_ADDR<16>
39 37 26 24 12 9 PCI_AD<30> D3 AD30 A8/CC/BE1* E11 CBUS_ADDR<8> 17
1 C783 1 C776 17 CBUS_ADDR<22>
46 45 CBUS_ADDR<15>
17
R7671 39 37 26 24 12 9 PCI_AD<31> E3
AD31 A9/CAD14 F11 CBUS_ADDR<9> 17
2.2UF 2.2UF 17
20% 20% 17 CBUS_ADDR<23>
48 47 CBUS_ADDR<12> 17
22 A10/CAD9 G11 CBUS_ADDR<10> 17 2 10V
CERM 2 10V
CERM
5% 39 37 26 24 12 PCI_CBE<0> K6 C/BE0* 17 CBUS_ADDR<24>
50 49
B 1/16W
MF
402 2
39 37 26 24 12 PCI_CBE<1> M3
J2
C/BE1*
A11/CAD12 G12
A12/CC/BE2* D9
CBUS_ADDR<11>
CBUS_ADDR<12>
17
17
805 805
52
54
51
53
CBUS_ADDR<7> 17 B
39 37 26 24 12 PCI_CBE<2> C/BE2* 17 CBUS_ADDR<25> CBUS_ADDR<6> 17
A1 A13/CPAR E12 CBUS_ADDR<13> 17
56 55
39 37 26 24 12 PCI_CBE<3> C/BE3* A14/CPERR* D12 CBUS_ADDR<14> 17
17 CBUS_VS2 CBUS_ADDR<5> 17
58 57
39 37 26 24 12 PCI_PAR N1 PAR A15/CIRDY* C10 CBUS_ADDR<15> 17
R750 17 CBUS_RESET_L CBUS_ADDR<4> 17
K1
47 17 CBUS_WAIT_L
60 59
39 37 26 24 12 PCI_IRDY_L IRDY A16/CCLK B13 CBUS_ADDR_16_UF 1 2 CBUS_ADDR<16> 17
62 61 CBUS_ADDR<3> 17
17 CBUS_PCI_SERR_L L2 SERR A17/CAD16 F10 CBUS_ADDR<17> 17 5%
1/16W 17 CBUS_INPACK_L 64 63 CBUS_ADDR<2> 17
CBUS_PCI_IDSEL F2 IDSEL A18/RSVD E13 CBUS_ADDR<18> 17 MF
402 17 CBUS_REG_L
66 65 CBUS_ADDR<1> 17
17 CBUS_PCI_PERR_L K3 PERR A19/CBLOCK* A13 CBUS_ADDR<19> 17
68 67
17 CBUS_BVD2_L CBUS_ADDR<0> 17
39 37 26 24 12 PCI_FRAME_L J1 FRAME A20/CSTOP* E10 CBUS_ADDR<20> 17
17 CBUS_BVD1_L
70 69
39 37 26 24 12 PCI_STOP_L L1 STOP A21/CDEVSEL* D11 CBUS_ADDR<21> 17
NO STUFF 72 71 CBUS_DATA<0> 17
39 37 26 24 12 PCI_TRDY_L J3 TRDY A22/CTRDY* C12 CBUS_ADDR<22> 17
74 73
R764 39 37 26 24 12 PCI_DEVSEL_L K2 DEVSEL A23/CFRAME* A10 CBUS_ADDR<23> 17
17 CBUS_DATA<8> CBUS_DATA<1> 17
47 17 CBUS_DATA<9>
76 75 CBUS_DATA<2> 17
30 27 26 23 IO_RESET_L 1 2 CBUS_PCI_RESET_L G3 PRST A24/CAD17 B10 CBUS_ADDR<24> 17
78 77
17 CBUS_DATA<10> CBUS_WP_L 17
5%
1/16W
12 CBUS_PCI_REQ_L C2 REQ A25/CAD19 B9 CBUS_ADDR<25> 17
80 79
39 17 CBUS_DET_2_L
MF 12 CBUS_PCI_GNT_L C1 GNT
402
G1
D0/CAD27 A4 CBUS_DATA<0> 17
36 12 CLK33M_CBUS PCLK C4 83 82
D1/CAD29 CBUS_DATA<1> 17
D2/RSVD A3
R766 CBUS_DATA<2> 17
RP39 39 30 26 24 20 18 17 14 MAIN_RESET_L 1
47 2
NC M9 SPKROUT D3/CAD0 K11 CBUS_DATA<3> 17
10K NC M8 RI_OUT/PME D4/CAD1 K12 CBUS_DATA<4> 17
5% 5%
1/32W SUSPEND
25V 1/16W
MF
17 CBUS_SUSPEND_PU N10 D5/CAD3 J13 CBUS_DATA<5> 17
402 D6/CAD5 J10 CBUS_DATA<6> 17

5 6 CBUS_MFUNC1_PD 14 CBUS_INT_L K7 MFUNC0 H12
17
N9 D7/CAD7 CBUS_DATA<7> 17
10 4 CBUS_MFUNC2_PD 17 CBUS_MFUNC1_PD MFUNC1
17
D8/CAD28 C5 CBUS_DATA<8> 17
A
7
3
CBUS_MFUNC3_PD
CBUS_MFUNC4_PD
17
17
17 CBUS_MFUNC2_PD
17 CBUS_MFUNC3_PD
L9
K10
MFUNC2
MFUNC3
D9/CAD30
D10/CAD31
B4
B3
CBUS_DATA<9>
CBUS_DATA<10>
17
CARDBUS
9
8
CBUS_MFUNC5_PD
CBUS_MFUNC6_PD
17
17 CBUS_MFUNC4_PD
17 CBUS_MFUNC5_PD
M10
N12
MFUNC4
MFUNC5
D11/CAD2 M12 CBUS_DATA<11>
17
17
A
17
D12/CAD4 J11 CBUS_DATA<12> 17
2 17 CBUS_MFUNC6_PD L10 MFUNC6
D13/CAD6 K13 CBUS_DATA<13> 17 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1 J12 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
D14/RSVD CBUS_DATA<14> 17 AGREES TO THE FOLLOWING
L11 GRST H11
SM D15/CAD8 CBUS_DATA<15> 17 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
GND II NOT TO REPRODUCE OR COPY IT
A2 A11 D1 F13 H4 K8 M13 N2 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE COMPUTER INC.

D 051-6459 A
SCALE SHT OF
NONE 17 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_5_HEAD

TABLE_5_ITEM
338S0133 1 IC,ATI,M10,NO HEATSPREADER U44 CRITICAL ?

27M OSC
38 21 19 18 12 +3V_GPU
(PLACE THE OSCILLATOR AND R1015 AND R1077
U44 +3V_SLEEP CLOSE TO ATI PIN AJ29)
RAGE_MOBILITY
38 21 19 18 16 15 12 +1_5V_AGP M10-CSP64
B26 64MB A17
L4
BGA FERR-EMI-100-OHM
OMIT A26 (2 OF 6) B16
1 2 38 +3V_ATI_OSC_SLEEP
D U44
CRITICAL
R1191 1
R127
B25
A25
A16
B14
SM D
RAGE_MOBILITY 47 10K C22 A14 C77 1 1 C78
5% 5% 0.1uF 4.7uF
M10-CSP64 1/16W 1/16W D21 B13 20% 20%
64MB MF MF 10V 6.3V
402 2 C21 A13 CERM 2 2 CERM
37 12 AGP_AD<31>
AB30 AD31 BGA AD_STB0 N29 AGP_AD_STB<0> 2 402 1
NO STUFF
CRITICAL 14 402 805
37 12 AGP_AD<30>
AB27 AD30 (1 OF 6)
AD_STB1 W29 AGP_AD_STB<1>
12 37
R159 D20 D13 R1881 VCC
12 37 20K C20 C13
100K (PLACE R1085 CLOSE TO OSC)
37 12 AGP_AD<29>
AA29 AD29 AD_STBB0 M28 AGP_AD_STB_L<0> 5% 5%
12 AGP_AD<28>
AB28 AD28 AD_STBB1 Y29 AGP_AD_STB_L<1>
12 37
1/16W
MF D22 D12 1/16W
MF
G2 GPU_SS
37
37 12 AGP_AD<27>
AA30 AD27 AGP_BUSYB AG28 AGP_BUSY_L
12 37
2 402 C23 C12 402 2 27.0000M R200
12
D23 D10 1
OSC
SM-1 8
0
37 12 AGP_AD<26>
AA27 AD26 AGPREF K30 INT_AGP_VREF 12 38
ATI_OSC_OE OE OUT ATI_CLK27M_OSC 1 2 ATI_CLK27M_OSC_SS 18
Y30 AD25 K29 A27 C10 5%
37 12 AGP_AD<25> AGPTEST GPU_AGP_TEST 1/16W
B27 GND
37 12 AGP_AD<24>
AA28 AD24 AGP8X_DETB U25 AGP8X_DET_PU OMIT D9
R1891 MF
402
W30 AD23 7 287
37 12 AGP_AD<23>
W27 AD22
1 C62 1 C63 H2 C9 1%
37 12 AGP_AD<22> SUS_STAT AJ28 AGP_SUS_STAT_L_PU 0.1uF 0.01uF H1 B12 1/16W
MF
V30 AD21 20% 20% 402 2
37 12 AGP_AD<21> 10V J2 A12
16V
V28 AD20 ST0 AF30 AGP_ST<0> 12
2 CERM 2 CERM
37 12 AGP_AD<20> 402 J1 B11 ATI_CLK27M_IN 19
V29 AD19 ST1 AF28 AGP_ST<1> 12
402
37 12 AGP_AD<19> K4 A11
ST2 AE29 AGP_ST<2> 1
37 12 AGP_AD<18>
V27 AD18 12
(PLACE C1002 CLOSE TO AGPREF PIN) K3 B9 R195
37 12 AGP_AD<17>
U30 AD17 SBA7 AC28 AGP_SBA<7> 12 37 L4 A9
162
1%
37 12 AGP_AD<16>
U28 AD16 SBA6 AB29 AGP_SBA<6> 12 37 M3 B8 1/16W
38 21 19 18 12 +3V_GPU MF
37 12 AGP_AD<15>
R27 AD15 SBA5 AC27 AGP_SBA<5> 12 37 L3 A8 402 2
37 12 AGP_AD<14>
R29 AD14 SBA4 AC30 AGP_SBA<4> 12 37 M4 VSS VSS C7
37 12 AGP_AD<13>
P28 AD13 SBA3 AD27 AGP_SBA<3> 12 37 N2 D7
1
37 12 AGP_AD<12>
P30 AD12 SBA2 AD30 AGP_SBA<2> 12 37
R172 N1 C6
P27 AD11 AE28 20K
37 12 AGP_AD<11> SBA1 AGP_SBA<1> 12 37 5% N4 D6
P29 AD10 AD29 1/16W
37 12 AGP_AD<10> SBA0 AGP_SBA<0> 12 37 MF N3 C4
37 12 AGP_AD<9>
N28 AD9 RBFB AE30 AGP_RBF_L 2 402 G30 D4
C 37 12 AGP_AD<8>
N30 AD8
M30 AD7 STP_AGPB AG29 AGP_STP_L
12 37
G28 C3 C
37 12 AGP_AD<7> B30 D3
M27 AD6 SB_STB AC29 AGP_SB_STB 12 37
37 12 AGP_AD<6>
M29 AD5 SB_STBS AD28 AGP_SB_STB_L 12 37
R158 D26 A5
37 12 AGP_AD<5> 0 D16 B5
L28 AD4 RSTB_MSK AD24 ATI_RSTB_MSK 1 2
37 12 AGP_AD<4> B15 A4
38 21 19 18 12 +3V_GPU 5%
37 12 AGP_AD<3>
L30 AD3 1/16W D11 B4 S0=1;S1=M => -1.5% DOWN-SPREAD
L27 AD2 DBI_LO Y25 ATI_DBI_LO_PU MF
37 12 AGP_AD<2> 402 B10 A2
MAIN_RESET_L IS TOGGLED FOR SLEEP R54 1
37 12 AGP_AD<1>
L29 AD1 DBI_HI Y27 ATI_DBI_HI_PU 38
19
OMIT D5 B2
SPREAD SPECTRUM SUPPORT
R53 10K
5% 37 12 AGP_AD<0>
K28 AD0
16
12
15
+1_5V_AGP
M2 B3 A1
1
47 2 1/16W 18
U44
24 20 17 14 MAIN_RESET_L 21 P3
39 30 26 MF W28 CBEB3 RAGE_MOBILITY G3 B1 +3V_SLEEP GPU_SS
5% 402 2 37 12 AGP_CBE<3>
A21
1/16W
MF 37 12 AGP_CBE<2>
U29 CBEB2 M10-CSP64
64MB
E1 E4 L3
402 R30 CBEB1
B19 U1 E3 FERR-EMI-100-OHM
37 12 AGP_CBE<1> BGA M15
37 12 AGP_CBE<0>
N27 CBEB0 R1261 1
R138 (6 OF 6)
N15
V3 F3 1 2 38 +3V_ATI_SS
47K 47K AB1 F4 SM
AG30 PCICLK 5% 5% P15 GPU_SS GPU_SS
36 12 CLK66M_GPU_AGP 1/16W 1/16W AC3 H3
21 19 18 12
38
+3V_GPU
37 12 AGP_FRAME_L
U27 FRAMEB MF
402 2
MF
2 402 VSS
R15 J30 H4
1 C70 1 C71
T30 IRDYB T15 10uF 0.1uF
37 12 AGP_IRDY_L J29 J3 20% 20%
1
R43 37 12 AGP_TRDY_L
T28 TRDYB T12 H30 J4 2 6.3V
CERM
10V
2 CERM
1K T27 STOPB T13 805 402
1% 37 12 AGP_STOP_L H29 C1 GPU_SS
1/16W NO STUFF GPU_SS 7 CRITICAL
MF 37 12 AGP_DEVSEL_L
T29 DEVSELB T14 F30 C2
2 402 37 12 AGP_PAR
R28 PAR W16 F29
R1731 1
R181 VDD
D1 0 0 U47
37 12 AGP_REQ_L
AF29 REQB V16 E30 D2 5% 5%
AF27 GNTB U16
1/16W
MF
1/16W
MF
CY25811
37 12 AGP_GNT_L E29 F1 SOI
1 402 2 2 402 18 ATI_CLK27M_OSC_SS
R44 14 AGP_INT_L AH29 INTAB T16 J28 F2
1 XIN/CLKIN
38 21 18
1K +GPU_MEM AGP_ATI_RESET_L AH30 RSTB R16 NC 8 XOUT SSCLK 5 ATI_SSCLK_UF
1% J27 G1
1/16W AE27 WBF R17 GPU_SS
MF 12 AGP_WBF_L H28 G2 1
R201
B 2 402
1
R45 AGP_ATI_VREFG AK3 VREFG
R18
R19
H27
F28
R1
R2
NC 6
3
FRSEL
33
5%
B
1K AGP_ATI_VREF D8 VREF CY25811_S1 S1 1/16W
F27 MF
1% A10 T1 CY25811_S0 4 S0
1/16W C19 U6 2 402
MF C5 E28 T2 VSS ATI_SSCLK_IN 19
PLACE VERF VOLTAGE DIVIDER 2 402 P2 AE15 E27 V1 2
CLOSE TO ATI M10 VREF PIN A3
B18 VDDCI F18 D30 V2
G4
P4 P25 NO STUFF NO STUFF
1
R46 1 C11 1 C37 E2 D29 VSS VSS W1
1 1
1K 0.1uF 10uF
A19
U2 C30 W2 R37 R38
1% 20% 20% R3 C29 T3
0 0
1/16W 10V 6.3V V4 5% 5%
MF 2 CERM 2 CERM A18 A30 T4 1/16W 1/16W
2 402 402 805 AB2 MF MF
R4 A29 U3 402 2 2 402
AC4
D19 A28 U4
P1 VSS VSS B23
K2 B28 W3
G29 D28 W4
A23 39 38 19 GPU_VCORE
G27
K1 L2 C28 Y3
B29
B22
60-OHM-EMI D27 Y4
38 21 20 19 +1_8V_GPU
C26 1 2 C27 Y1
L2 38 GPU_VCORE_VDDCI
C16 SM D25 Y2
A22
A15 C25 AA1
C11
L1 1 C64 1 C67 D24 AA2
0.01uF 10uF
ATI_MEMIO_LO ATI_MEMIO_HI D+ AC10 GPU_THERM_DP 20%
16V
20% C24 AC1
R55 1 1
R104 2 CERM 2 6.3V
D- AC11 GPU_THERM_DM 402
CERM
805 D18 AC2
4.7K 4.7K +GPU_MEM 18 21 38
5% 5% E8 C18 AD1
1/16W 1/16W TEST_YCLK
MF MF J6 (PULL-UP to GPU_MEM_IO) AD2
402 2 2 402 TEST_MLCK D17
FOR 2.5 VDDR1
MEMVMODE0=1.8V
MEMVMODE1=GND
ATI_MEMVMODE0 B7 MEMVMODE0 MEMTEST C8 ATI_MEMTEST
1 C65 1 C68 C17
AA3
AA4
M10 AGP INTERFACE
A FOR 1.8 VDDR1
MEMVMODE0=GND
ATI_MEMVMODE1 B6 MEMVMODE1 PLLTEST AC22 NC
20%
16V
0.01uF 0.01uF
20%
D15
C15
AB3
A
MEMVMODE1=1.8V
ATI_MEMIO_HI
1 1
ATI_MEMIO_LO 1
R118 2 CERM 2 16V
CERM AB4
R70 R105 45.3 402 402 D14
AD3 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
4.7K 4.7K 1% C14 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
5% 5% 1/16W AD4 AGREES TO THE FOLLOWING
1/16W 1/16W MF B17
MF MF 2 402 AE3 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
402 2 2 402 1 C66 1 C69 AE4 II NOT TO REPRODUCE OR COPY IT
0.01uF 0.01uF III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
20% 20%
16V
2 CERM 2 16V
CERM
402 402 SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.

D 051-6459 A
SCALE SHT OF
NONE 18 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TMDS TERMINATION 38 21 19 18 16 15 12 +1_5V_AGP
L24
TERMINATION NETWORK SHOULD BE CONNECTED AS SHOWN U44 Q77 FERR-220-OHM F12 G7
CMF LINE SHOULD BE ROUTED AS 4MIL SURFACE
TRACE SO THAT IT MAY BE CUT BETWEEN CAPS
RAGE_MOBILITY
M10-CSP64
SI3446DV 1 2 (500mA) L6
U44 G8
1 TSOP 38 +1_5V_GPU_VDD15 RAGE_MOBILITY
64MB 0805 T6 M10-CSP64 G9
BGA 2
AB6 64MB G10
37 20 GPU_DVOD<0>
(3 OF 6)
AJ5 ZV_LCDDATA0 ROMCSB AE5 NC 5 1 C222 1 C256 1 C299 1 C305 1 C328 F17 VDD15
BGA G11
GPU_DVOD<1> AK5 ZV_LCDDATA1 6 3 GPU_CORE_OK
0.01uF 0.01uF 0.01uF 0.01uF 10uF (5 OF 6)
37 20 19 21 20% 20% 20% 20% 20%
AG6 ZV_LCDDATA2 R AK28 22 GPU_R 16V
2 CERM 2 16V 16V
2 CERM 2 16V 2 6.3V
G25 G12
37 20 GPU_DVOD<2> 4
CERM CERM CERM
R25 G13
+GPU_VDD15_UF 19 38 402 402 402 402 805
37 20 GPU_DVOD<3> AH6 ZV_LCDDATA3 G AK27 22 GPU_G
AB25 G14
37 20 GPU_DVOD<4> AJ6 ZV_LCDDATA4 OMIT
AK6 ZV_LCDDATA5 B AK26 22 GPU_B 1 C166 AJ3
G15
37 20 GPU_DVOD<5>
1 1 1 1000pF OMIT G16
37 20 GPU_DVOD<6> AG7 ZV_LCDDATA6 R240 R246 R249 10% 1 C232 1 C269 1 C300 1 C306 AF25
D 37 20 GPU_DVOD<7> AH7 ZV_LCDDATA7

AJ7 ZV_LCDDATA8
VSYNC AG27
V2SYNC AG25 NC
ATI_VSYNC 22
1%
75
1/16W
1%
75
1/16W
1%
75
1/16W
25V
2 X7R
402
0.01uF
20%
0.01uF
20%
0.01uF
20%
0.01uF
20%
AG4
AH4
G17
G18
D
GPU_DVOD<8> 16V
37 20
MF MF MF 2 CERM 2 16V
CERM
16V
2 CERM 2 16V
CERM G19
37 20 GPU_DVOD<9> AK7 ZV_LCDDATA9 HSYNC AG26 ATI_HSYNC 22 2 402 2 402 2 402 402 402 402 402 AF5
G20
37 20 GPU_DVOD<10> AG8 ZV_LCDDATA10 H2SYNC AG24 NC F6
G21
37 20 GPU_DVOD<11> AH8 ZV_LCDDATA11 G6
RSET AK25 G22
NC AJ8 ZV_LCDDATA12
NC AK8 ZV_LCDDATA13
R2SET AJ24
ATI_RSET
ATI_R2SET 39 38 19 18 GPU_VCORE GPU VCORE - 1.2V (PUT ALL CAPs BELOW ATI ASIC)
H6
P6
G23
G24
38 21 20 18 +1_8V_GPU 18 12 +3V_GPU
38 21 19 NC AG9 ZV_LCDDATA14 1 1 AD26
EXT_TMDS INT_TMDS
NC AH9 ZV_LCDDATA15
R256 R257 V6
H7
Y_G AK23 715 499 C167 C219 C252 C270 C301 C307 C329 C332 H8
R2281 R2341 NC AJ9 ZV_LCDDATA16
22 GPU_Y
1% 1%
1
10uF
1
10uF
1
0.22uF
1
0.22uF
1
0.22uF
1
0.22uF
1
0.22uF
1
0.22uF
W6
10K 10K C_R AK24 22 GPU_C 1/16W 1/16W H23
5% 5% NC AK9 ZV_LCDDATA17 MF MF 20% 20% 20% 20% 20% 20% 20% 20% AC6
1/16W 1/16W COMP_B AK22 22 GPU_COMP 402 2 2 402 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
H24
MF MF NC AG10 ZV_LCDDATA18 805 805 402 402 402 402 402 402
AD6
J7
402 2 402 2 1 1 1
NC AH10 ZV_LCDDATA19 R245 R248 R254 AE6
J24
ZV_LCDDATA20_PU AJ10 ZV_LCDDATA20 75 75 75 F7
1% 1% 1% K7
NC AK10 ZV_LCDDATA21 DIGON AE13 22 FP_PWR_EN 1/16W 1/16W 1/16W F10
NC AG11 ZV_LCDDATA22 BLON AF13 22 INV_ON_PWM
MF
2 402
MF
2 402
MF
2 402
1 C186 1 C220 1 C253 1 C271 1 C302 1 C311 1 C330 1 C333 AE10
K24
0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF L7
NC AH11 ZV_LCDDATA23 20% 20% 20% 20% 20% 20% 20% 20% F11
HPD1 AF11 GPU_HPD 22 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM AE11
L24
AJ4 ZV_LCDCNTL0 +3V_GPU 12 18 19 21 402 402 402 402 402 402 402 402 M7
37 20 GPU_DVO_VSYNC 38 F13 VDDC
37 20 GPU_DVO_HSYNC
AK4 ZV_LCDCNTL1 1 M24
20 GPU_DVOD_DE
AH5 ZV_LCDCNTL2 R711 F14
N7
10K AE14
AG5 ZV_LCDCNTL3 5% N24
36 20 GPU_DVO_CLKP
1/16W
MF R2471 R2531 1 C187 1 C221 1 C254 1 C282 1 C303 1 C326 1 C331 1 C338 AF14
P7
AJ2 GPIO0 10K 10K 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF W26
19 ATI_AGP_FBSKEW<0> 2 402 5% 5% 20% 20% 20% 20% 20% 20% 20% 20% P24
19 ATI_AGP_FBSKEW<1>
AK2 GPIO1 AUXWIN AJ27 GPU_AUXWIN 1/16W 1/16W 2 6.3V 2 6.3V 2 6.3V 2 6.3V
CERM 2 6.3V 2 6.3V 2 6.3V 2 6.3V AF15
MF MF CERM CERM CERM 402 CERM CERM CERM CERM R7
AK1 GPIO2 402 2 402 2 402 402 402 402 402 402 402 AE17
19 ATI_X1CLK_SKEW<0>
R24
19 ATI_X1CLK_SKEW<1>
AH3 GPIO3 AC25
AH2 GPIO4 DDC1DATA AH28 GPU_DVI_DDC_DATA 22
AE18
T7
C 19 ATI_BUS_CFG<0>
19 ATI_BUS_CFG<1>
AJ1 GPIO5 DDC1CLK AH27 GPU_DVI_DDC_CLK 22
38 21 19 18 12 +3V_GPU F23
T24
U7
C
19 ATI_BUS_CFG<2>
AF4 GPIO6 DDC2DATA AE12 LVDS_DDC_DATA 22 39
F24
(NO ICT TEST)
U24
ATI_GPIO7_SPN AH1 GPIO7 DDC2CLK AF12 LVDS_DDC_CLK 22 39
AE24
M10 Power Shut down Sequencing NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF V7
AG3 GPIO8 1 1 1 1 1 1 1 F25
ATI_GPIO8_PD
(NO ICT TEST)
AF3 GPIO9 DDC3DATA AH26 SI_DDC_DATA 20
R258 R260 R262 R265 R269 R271 R273 M25
V24
ATI_GPIO9_SPN +2_5V_SLEEP 10K 10K 10K 10K 10K 10K 10K
38 21 19 18 12 +3V_GPU
(NO ICT TEST)
AG2 GPIO10 DDC3CLK AH25 SI_DDC_CLK 20 5% 5% 5% 5% 5% 5% 5% N25
W7
ATI_GPIO10_SPN 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W VSS W24
NO STUFF (NO ICT TEST)
AF2 GPIO11 MF MF MF MF MF MF MF
2 402 1 ATI_GPIO11_SPN TXOUT_U0N AH18 LVDS_U0N
DP6 2 402 2 402 2 402 2 402 2 402 2 402 2 402
W25
MF R223 (NO ICT TEST)
AG1 GPIO12 TXOUT_U0P AG18
22 37 39
V25
Y7
1/16W
5%
10K ATI_GPIO12_SPN
(NO ICT TEST)
AF1 GPIO13
LVDS_U0P 22 37 39 XW21 BAS16TW
SOT-363
XW24 (GPIO0) ATI_AGP_FBSKEW<0> 19 Y24
1K 5%
1/16W
ATI_GPIO13_SPN TXOUT_U1N AH19 LVDS_U1N 22 37 39
SM SM (GPIO1) ATI_AGP_FBSKEW<1> 19 AA7
R221
1
MF
402 2 22 HPD_PWR_SNS_EN
AE2 GPIO14 TXOUT_U1P AG19 LVDS_U1P 38 21
22 37
39
+1_8V_ATI_PVDD 1 2 38 1 6 +2_5V_SLEEP_NECK1 1 2 (GPIO2) ATI_X1CLK_SKEW<0> 19 AA24
19 GPU_VCORE_CNTL_L AE1 GPIO15 TXOUT_U2N AH20 LVDS_U2N 22 37 39 (GPIO3)
+1_8V_PVDD_NECK ATI_X1CLK_SKEW<1> 19 AB7
38
18 ATI_SSCLK_IN
M1 GPIO16 TXOUT_U2P AG20 LVDS_U2P (GPIO4)
22 37 39
DP6 ATI_BUS_CFG<0> 19 AB24
TXOUT_U3N AH22 LVDS_U3N_TP (NO ICT TEST)
XW20 BAS16TW +1_5V_AGP_NECK 38 (GPIO5) ATI_BUS_CFG<1> 19 AC7
AJ13 TX0M SOT-363
20 ATI_TMDS_DN<0> TXOUT_U3P AG22 LVDS_U3P_TP (NO ICT TEST) SM (GPIO6) ATI_BUS_CFG<2> 19 AC8
AK13 TX0P GPU_VCORE 2 5
20 ATI_TMDS_DP<0> TXCLK_UN AH21 CLKLVDS_UN 39 38 19 18 1 2
AJ14 TX1M TXCLK_UP AG21
22 37 39
XW23 1
NO STUFF
1
NO STUFF
1
NO STUFF
1
NO STUFF
1
NO STUFF
1
NO STUFF
1
NO STUFF AC23
20 ATI_TMDS_DN<1> CLKLVDS_UP 22 37 39
38 GPU_VCORE_NECK
SM R259 R261 R263 R266 R270 R272 R274 AC24
20 ATI_TMDS_DP<1>
AK14 TX1P TXOUT_L0N AK16 LVDS_L0N 22 37 39 DP6 1 2 +1_5V_AGP
38
12 15 16
18 19 21
10K
5%
10K
5%
10K
5%
10K
5%
10K
5%
10K
5% 5%
10K AD7
20 ATI_TMDS_DN<2>
AJ15 TX2M TXOUT_L0P AJ16 LVDS_L0P 22 37 39 XW22
SM
BAS16TW
SOT-363
1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF AD8
20 ATI_TMDS_DP<2>
AK15 TX2P TXOUT_L1N AK17 LVDS_L1N 22 37 39
38 19 +GPU_VDD15_UF 1 2 3 4 2 402 2 402 2 402 2 402 2 402 2 402 2 402 AD9
20 ATI_TMDS_CLKN
AJ12 TXCM TXOUT_L1P AJ17 LVDS_L1P 22 37 39
AD10
20 ATI_TMDS_CLKP
AK12 TXCP TXOUT_L2N AK18 LVDS_L2N 22 37 39
38 +GPU_VDD15_NECK AD11
TXOUT_L2P AJ18 LVDS_L2P 22 37 39
AD12
18 ATI_CLK27M_IN
AJ29 XTALIN TXOUT_L3N AK20 LVDS_L3N_TP (NO ICT TEST)
AD13
2
R229
1K
NC
1 ATI_TESTEN AH24
AJ30 XTALOUT
TESTEN
TXOUT_L3P AJ20
TXCLK_LN AK19
TXCLK_LP AJ19
LVDS_L3P_TP
CLKLVDS_LN
CLKLVDS_LP
(NO ICT TEST)
22 37 39
22 37 39
GPU VCORE SUPPLY AD14
AD15
B 5%
1/16W NC AJ26 SSIN SSOUT AJ25 NC
+PBUS
AD16
AD17
B
MF
402 AD18
B24 VSS VSS A20 AD19
B20 VSS VSS B21 AD20
A24 VSS
1
1
R430 1
R339 C762 1 C766 1
WHEN VCORE_CNTL HIGH => 1.2V AD21
R389 1 576K 4.7UF 4.7UF
20% 1.2V = 0.8V * (1 + R332 / (R331//R333)) AD22
1M 5% 1% 20% 25V AD23
5% 1/16W 25V CERM 2
1/16W
MF
MF 1/16W
MF
CERM 2
1206 1206 WHEN VCORE_CNTL LOW => 1.0V
2 603 2 402 1.0V = 0.8V * (1 + R332 / R333)
2 402 Q51
SI7860DP
1778_VCC SO-8-PWRPK CRITICAL
38
CRITICAL R3521
NO STUFF NO STUFF GPU_VCORE 18 19 38 39
4.99K
+5V_MAIN 1%
1 C473 38 1778_VIN 1
3
1 1 1/16W
R388 R341 4.7UF
4.7uF D5
SM
MF
402 2
0 63.4K 20%
1
5% 1% 10V +5V_MAIN MBR0540 38 GPU_VCORE_SW 39 38 19 1778_VFB
1/16W 1/16W 2 CERM GPU_PWRMSR
1 R3161
MF
2 402
MF
2 402
1206
1778_GND
C494 1 R416
2
L30 1
R451
R306 100K
1778_SHDN_L_D3COLD 19
38
2.2
38 2.1UH-11A 18.2K
1778_BST_RC
100K 0.1uF 1 2 SM 1 C708 1
C721 1%
5%
1/16W
5%
1/16W DP1 DP1 20%
25V 22uF 330UF 1/16W
MF MF BAS16TW BAS16TW CERM 2 5% 2 20% 20%
MF
402 2 1 603 1/16W 10V +5V_MAIN 2 402
402 2 SOT-363
6 1
SOT-363
2 5
R3901 R236 9 11 10 MF
603 D24 2 CERM
1210
2 6.3V
POLY HIGH_VCORE_DIV
GPU_PWRMSR
R3511
38 21 19 18 16 15 12 +1_5V_AGP
GPU_VCORE_PWR_SEQ SLEEP_L_LS5 27 33 34 35 0 100K EXT INT VIN
VCC VCC
SMB SMD GPU_PWRMSR20K
5% B340LB
5% 1/16W U16 C514 1 1 C902 1
R804 1%
3 1/16W
MF MF
LTC1778 0.1uF 1
C719 1 C720 1 1
R307 0.1UF
1/16W
1.82K 402 MF
R2941 DP1 402 2 2 402 SSOP 20%
25V 330UF 330UF 100K 20% 1% 2
10K
5%
GPU_VCORE_SEQ_L 1 Q6 BAS16TW 1778_SHDN_L 1 RUN/SS ION 7 38 1778_ION CERM 2
603
20%
6.3V 2
20%
6.3V 2
POLY
5%
1/16W
10V
2 CERM 1/16W
MF
1/16W 2N3904 SOT-363 CRITICAL POLY SMD
MF 402
2 402
MF SM 3 4 38 1778_ITH 5 ITH B00ST 16 38 1778_BST SMD 2 402
A 402 2 3 2
DCDC_EN 29 32 33 34 39
TG 15 38 1778_TG
HIGH_VCORE
M10 CORE PWR/LVDS/TMDS A
1 3 VRNG GPU_VCORE_CNTL
1 Q5 R340 38 1778_VRNG
SW 14
CRITICAL GPU_PWRMSR 3 NOTICE OF PROPRIETARY PROPERTY
GPU_VCORE_SEQ
2N3904
20K
1% 38 1778_FCB 4 FCB Q48 R410 D
Q80
SI7892DP 10K THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
R2031 SM 1/16W
MF BG 12 38 1778_BG 19 GPU_VCORE_CNTL_L 1 2 VCORE_CNTL_RC 6 2N7002DW PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
2 SO-8-PWRPK SOT-363 AGREES TO THE FOLLOWING
33K 402 2 NO STUFF 5
5% 38 1778_ITH_RC
1 C451 1R311
21
19 GPU_CORE_OK 2 PGOOD
VFB 8 1778_VFB 19
5%
1/16W
D
Q80 G S
1/16W 1
R332 38 39
1 C882 MF 2N7002DW
MF 220pF 1 C483 SGND PGND 402
2 SOT-363 4 II NOT TO REPRODUCE OR COPY IT
402 2 5% 0 0 0.0022UF G S
C448 1 25V
2 CERM 5% 5% 0.1uF 6 13 10% GPU_PWRMSR III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
470pF
10%
402
1/16W
MF
1/16W
MF
20%
10V
2 CERM OMIT
50V
2 CERM C515 1 1
2 402 2 402
402 0.1uF SIZE DRAWING NUMBER REV.
50V
CERM 2 402 XW2 20%
38
402
19 1778_GND 1
SM
2
10V
CERM 2
402 APPLE COMPUTER INC.
D 051-6459 A
SCALE SHT OF
NONE 19 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+3V_SLEEP
1
R41
0 2 +3V_GPU_SI 20
SIL1162 DVI TRANSMITTER
5%
1/16W
D
MF
603 D
EXT_TMDS
RP58
SI_TMDS_CLKN
10
2 3 TMDS_CLKN
20 +3V_GPU_SI 20 20 22 37
EXT_TMDS 5%
EXT_TMDS 1/16W
L14 SM1
400-OHM-EMI RP58
1 2 1
10 4
38 +3V_SI_AVCC 20 SI_TMDS_CLKP TMDS_CLKP 20 22 37
SM-1 5%
EXT_TMDS EXT_TMDS EXT_TMDS 1/16W EXT_TMDS
1 C130 1 C132 1 C165 SM1
RP59
10UF 100PF 100PF
20% 5%
50V 5% SI_TMDS_DP<0> 1
10 4 TMDS_DP<0>
2 6.3V
CERM
2 CERM 50V
2 CERM 20 20 22 37 39
805 402 402 TMDS_CLK_CMF

EXT_TMDS 5%
EXT_TMDS 1/16W
C 400-OHM-EMI
L13 EXT_TMDS
L15
+3V_GPU_SI 20
RP59
10
SM1
C
1 2 +3V_SI_PLLVCC 400-OHM-EMI 20
SI_TMDS_DN<0> 2 3 TMDS_DN<0>
20 22 37 39
R205 R218
38
TMDS_CLKP 1
49.9 2 1
49.9 2 TMDS_CLKN
SM-1 EXT_TMDS EXT_TMDS EXT_TMDS 38 +3V_SI_VCC 1 2 5% EXT_TMDS 37 22 20 20 22 37
EXT_TMDS 1/16W
1 C14
1 C129 1 C131 1 C133 EXT_TMDS EXT_TMDS EXT_TMDS
SM-1 SM1
RP60 1%
1/16W
1%
1/16W
10UF 100PF 100PF 10 MF MF
10UF 20% 5% 5% 1 C218 1 C233 1 C255 20 SI_TMDS_DP<1> 2 3 TMDS_DP<1>
20 22 37 39
402 402
20% 2 6.3V 2 50V 2 50V 100PF 100PF 10UF
6.3V
2 CERM
CERM
805
CERM
402
CERM
402 5%
50V
5%
50V
20%
6.3V
5%
1/16W
C80 1 1 C88
805 2 CERM 2 CERM 2 CERM EXT_TMDS SM1
470PF 470PF
402 402 805 RP60 10%
50V
10%
50V
10 CERM 2 2 CERM
SI_TMDS_DN<1> 1 4 TMDS_DN<1> 402 402
20 20 22 37 39
5% EXT_TMDS
1/16W
SM1
RP61
SI_TMDS_DP<2> 10 TMDS_D0_CMF
20
1 4 TMDS_DP<2> 20 22 37 39
EXT_TMDS
RP61
5%
1/16W R211 R219
SM1 1
49.9 2 1
49.9 2
EXT_TMDS EXT_TMDS 10 39 37 22 20 TMDS_DP<0> TMDS_DN<0> 20 22 37 39
SI_TMDS_DN<2> 2 3 TMDS_DN<2>
1 1
R222 R224 20 20 22 37 39 1%
1/16W
1%
1/16W
NO STUFF EXT_TMDS EXT_TMDS EXT_TMDS 330 4.99K 5%
1/16W
MF
402
MF
402
1 1 1 1 5% 1%
R66 R99 R202 R212 1/16W
MF
1/16W
MF
SM1
C81 1 1 C89
10K 10K 10K 10K 2 402 2 402
5% 5% 5% 5% 470PF 470PF
28
PVCC1 46
PVCC2 40
34
22
1/16W 1/16W 1/16W 1/16W 10% 10%

50V 50V
VCC 3
MF MF MF MF INT_TMDS
2 402 2 402 2 402 2 402 CERM 2 2 CERM
AVCC
AVCC
VCC
402 402
EXT_TMDS RP57
ATI_TMDS_CLKN 10
R237 19
1 4 TMDS_CLKN 20 22 37
1
0 2 19 SI_DDC_CLK 27 SCL/DK1 MSEN 48 SI_MSEN 5% TMDS_D1_CMF
26 INT_TMDS 1/16W
SI_DDC_DATA SDA/DK0 R210 R220
B 30 26 24 18 17 14 MAIN_RESET_L
5%
1/16W
NO STUFF MF
19
SI_A2 24 CTL3/A2 RP57

10
SM1
TMDS_DP<1> 1
49.9 2 1
49.9 2
TMDS_DN<1> 20
B
402 SI_RST 25 ISEL/RST* ATI_TMDS_CLKP 2 3 TMDS_CLKP
39 37 22 20 22 37 39
39
R235 19 20 22 37
1% 1%
0 47 5% 1/16W 1/16W
1 2 SI_PD PD* 1/16W INT_TMDS MF MF
SM1 402 402
5%
1/16W
SI_EDGE 44 EDGE/HTPLG TXC+ 33 SI_TMDS_CLKP 20 RP27
MF TXC- 32 SI_TMDS_CLKN 20 ATI_TMDS_DN<0> 10 C82 1 1 C102
402 37 19 GPU_DVOD<0> 18 D0 U5 19
1 4 TMDS_DN<0> 20 22 37 39
470PF 470PF
37 19 GPU_DVOD<1> 17 D1 SIL1162 TX0+ 36 SI_TMDS_DP<0> 20 5% 10%
50V
10%
50V
INT_TMDS 1/16W
37 19 GPU_DVOD<2> 16 D2 TSSOP TX0- 35 SI_TMDS_DN<0> 20 SM1 CERM 2 2 CERM
GPU_DVOD<3> 15 D3
RP27 402 402
37 19
TX1+ 39 SI_TMDS_DP<1> 20 ATI_TMDS_DP<0>
10
37 19 GPU_DVOD<4> 14 D4 19
2 3 TMDS_DP<0> 20 22 37 39
EXT_TMDS TX1- 38 SI_TMDS_DN<1> 20
37 19 GPU_DVOD<5> 13 D5 5%
1/16W INT_TMDS
GPU_DVOD<6> 10 TX2+ 42 SI_TMDS_DP<2> TMDS_D2_CMF
37 19 D6 20 SM1
RP32
GPU_DVOD<7> 9 TX2- 41 SI_TMDS_DN<2> +1_8V_GPU R204 R214
37 19 D7 20
18 19 21 38
ATI_TMDS_DP<1> 10
GPU_DVOD<8> 8 D8 CRITICAL 19
1 4 TMDS_DP<1> 20 22 37 39 49.9 2 49.9 2
37 19
39 37 22 20 TMDS_DP<2> 1 1 TMDS_DN<2> 20 22 37 39
37 19 GPU_DVOD<9> 7 D9 5%
1/16W 1% 1%
6 EXT_TMDS INT_TMDS SM1 1/16W 1/16W
GPU_DVOD<10> D10
37 19
GPU_DVOD<11> 5
1
R231 RP32 MF
402
MF
402
37 19 D11
1K ATI_TMDS_DN<1>
10
2 3 TMDS_DN<1>
19 GPU_DVOD_DE 19 DE 1%
1/16W
19 20 22 37 39
C79 1 1 C87
37 19 GPU_DVO_HSYNC 20 HSYNC MF 5% INT_TMDS 470PF 470PF
EXT_SWING 30 EXT_SWING
2 402
1/16W 10%
50V
10%
50V
37 19 GPU_DVO_VSYNC 21 VSYNC SM1
RP28 CERM 2 2 CERM
36 19 GPU_DVO_CLKP 12 IDCK+ VREF 2 20 SI_VREF ATI_TMDS_DP<2> 1
10 4
402 402
19 TMDS_DP<2> 20 22 37 39
20 SI_VREF 11 IDCK- EXT_TMDS
EXT_TMDS 1 INT_TMDS
R232
THRML
5%
1 C284 RP28 1/16W
PGND
PGND
AGND
AGND
AGND
1K SM1
PAD
GND
GND
GND
NO STUFF EXT_TMDS NO STUFF 0.1UF 1%

ATI_TMDS_DN<2>
10
20% 1/16W 19
2 3 TMDS_DN<2> 20 22 37 39
1 10V MF
R88 1
R110 1
R233 2 CERM
2 402
A
29
45
31
43
37
1
23
4
5%
49
5%
10K
1/16W
10K
5%
1/16W
5%
10K
1/16W
402
1/16W
SM1
A
MF MF MF
2 402 2 402 2 402 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
APPLE COMPUTER INC.

D 051-6459 A
SCALE SHT OF
NONE 20 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U55 U54 INT_TMDS INT_TMDS
38 21 +2_5V_GPU MM1571J (100mA MAX)
SOT-25A
L65 GPU PLL - 1.8V 38 21 +2_5V_GPU CRITICAL MM1571J
SOT-25A
L69
FERR-220-OHM FERR-220-OHM
CRITICAL (Total PVDD = 66mA)
1 VIN VOUT 5 38 21 19 +1_8V_ATI_PVDD 1 2 38 +1_8V_GPU_PLL (21mA) 1 VIN VOUT 5+1_8V_ATI_TPVDD 1 2
+1_8V_GPU_TP_PLL 21
0402 INT_TMDS 0402
21 19 GPU_CORE_OK 3 CONT NOISE 4 ATI_PVDD_BYP 1 C438 1 C865 1 C716 21
19 GPU_CORE_OK 3 CONT NOISE 4 ATI_TPVDD_BYP 1 C881
1 C380 10uF 0.1uF 0.01uF 1 C879 10UF
1 C889 GND 1 C379 10uF
20% 20% 20%
16V 1UF GND INT_TMDS 20%
1UF 2 0.01uF 20% 2 6.3V
CERM
10V
2 CERM 2 CERM 10%
6.3V
2 1 C880 2 6.3V
CERM
10% 20% 6.3V 805 402 402 2 CERM 805
21 +2_5V_GPU 6.3V
2 CERM
16V
2 CERM 2 CERM 603 0.01UF
38
805 10% INT_TMDS
603 402 16V
L58 38 21 20 19 18 +1_8V_GPU 2 CERM
FERR-220-OHM 402
1 2 (140mA) +2_5V_GPU_A2VDD
L66
21 38 FERR-220-OHM
D 0402
1 2 38 +1_8V_GPU_AVDD (AVDD+VDDDI=75mA)
AK29 PVDD
AF23 AVDD0
PVSS AK30
AVSSQ AF22
D
1 C360 1 C364 1 C374 0402 AF24 AVDD1 38 21 18 +GPU_MEM
10uF 0.01uF 0.01uF A2VSSQ AJ22
20%
6.3V
20%
16V
20%
16V
1 C415 1 C437 1 C870 +2_5V_GPU_A2VDD AE21 A2VDD0 AVSSN0 AE22
2 CERM 2 CERM 2 CERM 10uF 0.01uF 0.01uF 38 21
805 402 402 20%

6.3V
20%
16V
20%
16V
AF21 A2VDD1 AVSSN1 AE23 L67
2 CERM 2 CERM 2 CERM AJ23 A2VDDQ
FERR-220-OHM
38 21 +1_8V_GPU_AVDDQ
805 402 402 A2VSSN0 AE19 1 2
38
20 38 21 +1_8V_GPU_VDDDI AH23 VDD1DI A2VSSN1 AE20 0805
18 +1_8V_GPU
19
21 38 21 19 18 16 15 12 +1_5V_AGP
AF20 VDD2DI
L55 VSS1DI AG23
FERR-220-OHM 38 21 +GPU_MCLK
F19 VDDRH0 VSS2DI AF19
L59 AGP 4X I/O - 1.5V
1
0402
2 (2mA) +1_8V_GPU_AVDDQ 21 38 FERR-10-OHM-500MA N6 VDDRH1
VSSRH0 F20 MEMORY I/O
1 2 38 +1_5V_AGP_GPU (20mA) K25 VSSRH1 M6
1 C339 1 C363 SM L25
F5 (1200mA) 38 GPU_MEM_IO_FLT
10uF 0.01uF 1 C381 1 C420 1 C446 1 C543 1 C871 T25
20% 20% G5
6.3V
2 CERM
16V
2 CERM 0.1uF 0.1uF 0.1uF 0.1uF 10uF Y28
805 402
20%
10V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM
20%
6.3V
2 CERM K27
H5 1 C872 1 C875 1 C850 1 C855 1 C860
J5 10uF 0.1uF 0.1uF 0.1uF 0.1uF
402 402 402 402 805 AA25 20% 20% 20% 20% 20%
38 K5 6.3V
2 CERM
10V
2 CERM
10V
2 CERM
10V
2 CERM
10V
2 CERM
20
18 +1_8V_GPU
K26
19 L5 805 402 402 402 402
21 L26
L56 M26
M5
FERR-220-OHM N5
1 2 (AVDD+VDDDI=75mA) +1_8V_GPU_VDDDI
1 C382 1 C421 1 C447 1 C671 N26
P5
21 38
0.01uF 0.01uF 0.01uF 0.01uF P26 1 C873 1 C876 1 C851 1 C856 1 C861
0402 20% 20% 20% 20% R5
16V
2 CERM
16V
2 CERM
16V
2 CERM
16V
2 CERM R26 VDDP 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
T5 20% 20% 20% 20% 20%
1 C358 1 C361 1 C372 402 402 402 402 T26
U5
10V
2 CERM
10V
2 CERM
10V
2 CERM
10V
2 CERM
10V
2 CERM
10uF 0.01uF 0.01uF 38 21 18 +GPU_MEM U26 402 402 402 402 402
20% 20% 20% V5
6.3V 16V 16V
2 CERM 2 CERM 2 CERM V26
W5
C 805 402 402
L63 MEMORY CORE - 2.5V
Y26
AA26
Y5 C
38
FERR-220-OHM AA5 1 C874 1 C847 1 C852 1 C857 1 C862
18 +GPU_MEM AB26 VDDR1
21 1 2 38 +GPU_MEMCORE (1800mA) AB5 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF
AC26 20% 20% 20% 20% 20%
0805 AC5 10V 10V 10V 10V 16V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
L57 1 C383 1 C425 1 C866 1 C672 1 C715 AD5 402 402 402 402 402
FERR-220-OHM OMIT
0.1uF 0.1uF 0.1uF 0.1uF 10uF G26
1 2 20% 20% 20% 20% 20%
0402
+GPU_MCLK 21 38 10V
2 CERM
10V
2 CERM
10V
2 CERM
10V
2 CERM
6.3V
2 CERM U44 K6
402 402 402 402 805 E5 RAGE_MOBILITY R6
1 C359 1 C362 1 C373 E6
M10-CSP64 Y6
10uF 0.01uF 0.01uF 64MB
20% 20% 20% E12 BGA AA6
6.3V 16V 16V (4 OF 6)
2 CERM 2 CERM 2 CERM E13 F8
805 402 402
1 C408 1 C426 1 C450 1 C701 E18 VDDM F9 EXT_TMDS +1_8V_GPU 18 19 20 21 38
0.01uF 0.01uF 0.01uF 0.01uF E19 F15
+1_5V_SLEEP +1_8V_SLEEP 20% 20% 20% 20% L16
2 16V
CERM
16V
2 CERM 2 16V
CERM
16V
2 CERM E20 F16 FERR-10-OHM-500MA
402 402 402 402 E26 F21
+1_8V_DVO_F 2 1
F26 F22 SM
19 +1_8V_ATI_PVDD
1
R722 R2841 38 21
E7
H25 1 C304 1 C327 1 C647
0 0 38 21 18 +GPU_MEM
J25 10uF 0.1uF 0.1uF INT_TMDS
5%
5% 1/10W L61 H26 20% 20% 20% 1
1/10W
FF
2 805
FF
805 2
FERR-220-OHM LVDS PLL - 1.8V E9
J26 2 6.3V
CERM
805
2 10V
CERM
402
2 10V
CERM
402
R268
0
1 2 38 +1_8V_GPU_PNLPLL (40mA) E10 AF6 5%
1/16W
+1_5V_AGP 12 +1_8V_GPU 18 19 20 21 38 0402 E11 AE7 MF
15 16 18 19 21 38
EXT_TMDS 2 603
E14 VDDR4 AF7
1.5V 1.8V 1 C409
10uF
20%
1 C428
0.01uF
20%
1 C867
0.01uF
20%
1
R279
0
E15
E16 VDDR1
AE8
AF8 FERR-10-OHM-500MA
L68 +3V_GPU 12 18 19 21
38
6.3V 16V 16V 5%

2 CERM 2 CERM 2 CERM 1/16W
+1_8V_SLEEP +2_5V_SLEEP E17 AE9 38 +3V_GPU_FLT 2 1
805 402 402 MF
2 603
B ATI_MEMIO_HI
E21
E22
AF9
AF10
SM
B
ATI_MEMIO_LO
1 1
R728 L62 E23 VDDR3 AD25
1 C722 1 C848 1 C853 1 C858 1 C863
R729 38 21 19 +1_8V_ATI_PVDD 21 +1_8V_GPU_TP_PLL
1.8V 0
5% 5%
0
1/4W
2.5V FERR-220-OHM
1 2
MEMORY PLL - 1.8V E24
E25
AE25
AE26
10uF
20%
2 6.3V
CERM
0.1uF
20%
10V
2 CERM
20%
2 10V
0.1uF
CERM
0.1uF
20%
10V
2 CERM
0.1uF
20%
2 10V
CERM
1/4W
FF FF
38 +1_8V_GPU_MEMPLL 1 C877 1 C878 AF26
805 402 402 402 402
1210 2 2 1210 0402 10uF 0.01uF
+GPU_MEM 18
1 C411 1 C429 20%
6.3V
2 CERM
20%
16V
2 CERM
21 38
10uF 0.01uF
20% 805 402
6.3V 20% AK21 LPVDD LPVSS AJ21
2 CERM
805
16V
2 CERM AK11 TPVDD TPVSS AJ11
1 C725 1 C849 1 C854 1 C859
38 21 +2_5V_GPU 402 0.1uF 0.1uF 0.1uF 0.1uF
(20mA) A7 MPVDD MPVSS A6 20% 20% 20% 20%
2 10V
CERM
10V
2 CERM 2 10V
CERM
10V
2 CERM
L64 AE16 LVDDR_18 LVSSR0 AH16 402 402 402 402
FERR-10-OHM-500MA LVDS - 2.5V AF16 LVDDR_18 LVSSR1 AG17
1 2 38 +2_5V_GPU_PNLIO (350mA) AG16 LVDDR_25 LVSSR2 AH17 EXT_TMDS
SM AF17 LVDDR_25 AF18 +1_8V_GPU 18
LVSSR3 R255 19 20 21 38
1 C412 1 C434 1 C868 AG12 TXVDDR0 0

DVOVMODE AH12 ATI_DVODMODE 1 2
10uF 0.01uF 0.01uF AG13 TXVDDR1 INT_TMDS
20% 20% 20% TXVSSR1 AH13 1
5%
6.3V
2 CERM
16V
2 CERM
16V
2 CERM AG14 TXVDDR2 TXVSSR2 AH14 R251 1/16W
MF
805 402 402
AG15 TXVDDR3 0 402
+1_8V_GPU TXVSSR3 AH15 5%
+2_5V_SLEEP
38 21 20 19 18
1/16W
MF 3.3V IO SUPPLY
2 402 (Max Current varies, depends on usage)
L60 LVDS/TMDS - 1.8V

+3V_SLEEP FERR-220-OHM
1
R721 1 2 38 +1_8V_GPU_PNLIO (180mA) M10 SHUT DOWN POWER SEQUENCING +3V_SLEEP
5%
0 0402 M10 POWER
A 1
R299 1 C413 1 C435 1 C864 1 C704 +2_5V_SLEEP OMIT OMIT
1/10W
FF
2 805 5%
0 10uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20% XW27
DP7
BAS16TW XW30 NOTICE OF PROPRIETARY PROPERTY
A
6.3V 10V 10V 10V SM SOT-363 SM
1/10W 2 CERM 2 CERM 2 CERM 2 CERM
+2_5V_GPU 21 38
FF 805 402 402 402 1 38 2 +2_5V_SLEEP_NECK2 3 4 +3V_SLEEP_NECK 1 2 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
2.5V +3V_GPU 12 18 19 21 38
+1_8V_SLEEP
XW28
OMIT
DP7
BAS16TW
3.3V 1 C414
0.1uF
20%
1 C436
0.01uF
20%
1 C869
0.01uF
20%
1
SM
2 38 +1_8V_SLEEP_NECK
SOT-363
2 5
10V 16V 16V
2 CERM 2 CERM 2 CERM SIZE DRAWING NUMBER REV.
402 402 402 OMIT
GPU POWER SOURCES - 1.5V, 1.8V, 2.5V & 3.3V
+1_5V_SLEEP
XW29
DP7
BAS16TW APPLE COMPUTER INC.
D 051-6459 A
SM SOT-363
SCALE SHT OF
1 2 38 +1_5V_SLEEP_NECK 1 6
NONE 21 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Power key detect path when
system is shutdown or asleep..
ANALOG FILTERING PLACE CLOSE TO CONNECTOR DDC_CLK is isolated from
NV17M DURING SHUTDOWN. WHEN
CRITICAL
FL2
LCFILTER
SM-220MHZ
EXTERNAL VIDEO (DVI) INTERFACE power key on remote device
is pressed, 5V will be driven
into DDC_CLK. Since host rails
will be low, TP0610 will turn
on, driving SOFT_PWR_ON_L low.
DVI POWER SWITCH
1 2 As host rails rise, TP0610
19 GPU_B VGA_B 22 39 will turn off, as will remote
DVI DDC CURRENT LIMIT device path into DDC_CLK.
SOFT_PWR_ON_L
Isolation will be disabled as well. 23 30 34
3 4 (55mA requirement per DVI spec) DVI_TURN_ON_BASE
1 C685 Q40
3.3PF TP0610 3
FL1 0.25% +5V_SLEEP
F1 L23 SM R690 R691
LCFILTER 2 50V 400-OHM-EMI +5V_DDC_SLEEP 680 10K
CRITICAL
SM-220MHZ
CERM
402 0.5AMP-13.2V
22 38 39
Isolation required for DVI power switch

39 22 DVI_DDC_CLK_UF 2
S D
3 DVI_TURN_ON 2 1 DVI_TRUN_ON_ILIM 1 2 1 Q42
1 2 38 +5V_DDC_SLEEP_UF 1 2 5% 5% 2N3904
1 2 1/16W 1/16W SM
19 GPU_G VGA_G 22 39
SM
SM-1 D21
SM
3V LEVEL SHIFTERS G MF
402 R688 1 MF
402
2
D 3 4
CRITICAL
J14
1 2 DDC_CLK_ISO
+3V_SLEEP
1
330
5%
1/16W
Pulldown prevents
3904 from turning
D
1 C676 QH1112 +5V_DDC_SLEEP
MF
402 2
on when DVI monitor
has active, self-
FL3 3.3PF F-RT-TH MBR0530 1
R655
39 38 22
powered DDC clock
CRITICAL 0.25% 36 pullup.
LCFILTER 50V
2 CERM 4.7K
33 31
SM-220MHZ
402 R6611 5%
1/16W
1
R662 Power key detect path
when system is running.
HPD normally driven to
19 GPU_R
1 2 VGA_R 22 39
4.7K MF 10K 3.3V. When power key +3V_SLEEP
5% 2 402 5 5%
17 1 1/16W Q38 1/16W on remote device pressed,
HPD will be driven to 5V.
3 4 1 C684 22 TMDS_CONN_DN<0>
9
TMDS_CONN_DN<2> 22 MF
402 2 R670 2N7002DW G MF
2 402
COMPARATOR ENABLED BY NV17MAP
GPIO.
3.3PF TMDS_CONN_DN<1> 22
100
SOT-363
0.25% 18 2 3 D S 4
50V 22 TMDS_CONN_DP<0> TMDS_CONN_DP<2> 22 1 2 DVI_DDC_CLK GPU_DVI_DDC_CLK 19
+3V_MAIN 2 CERM
402 10 TMDS_CONN_DP<1> 22 5% 1 C696
19 3
1/16W
MF 1
R671 R6801 0.1UF
11
1 C706 402
10K
68.1K
1%
20%
10V
2 CERM
CRITICAL 100pF 2 5% 1/16W
5 (TMDS_DN<5>) NC 20 4 NC (TMDS_DN<4>) 5%
50V
2 CERM
Q38 1/16W
MF
MF
402 2
402
74AHC1G32 12 2N7002DW G
19 ATI_HSYNC 1 SM R718 21 5
NC (TMDS_DN<3>) 402 R649 SOT-363 2 402
4
33 (TMDS_DP<5>) NC NC (TMDS_DP<4>) 100
DVI_DDC_DATA 6 D S 1
2
U56 VGA_HSYNC_BUF 1 2 VGA_HSYNC 22 39
13 NC (TMDS_DP<3>)
1 2 GPU_DVI_DDC_DATA 19 HPD_4V_REF
4
2 U46 HPD_PWR_SW
32 5%
1/16W 22 6 39
22 DVI_DDC_CLK_UF
5%
1/16W
LMC7211
1 SM
3
MF
402 14 (+5V_DDC SLEEP) 1 C669
MF
402 R694 R663 CRITICAL
1 3 4 HPD_ON
23 7 100pF 100K D S
39 37 22 TMDS_CONN_CLKP 39 DVI_DDC_DATA_UF 5 5% 10K Q41
15
5%
50V
2 CERM
Q35 1/16W
MF
39 22 DVI_HPD_UF 1 2 DVI_HPD_DIV 3
G 2N7002DW 1
R703
VGA VSYNC BUFFERS 2N7002DW G
39 37 22 TMDS_CONN_CLKN
24 8 VGA_VSYNC 22 39
402 R650 SOT-363 2 402
1%
1/16W
5
Q45
SOT-363
330
CRITICAL 16 39 100 3 D S 4
MF +PBUS 5 5%
1/16W
22 DVI_HPD_UF 1 2 DVI_HPD GPU_HPD 19 402 TP0610 MF
5 1
1
74AHC1G32
R714 VGA_B C3 C1 VGA_R
5%
1/16W R686 1 R681 2
SM
3
2 402 HPD_BASE
ATI_VSYNC SM 39 22 22 39
1 C710 10K 100K COMP_ENABLE 3
19
4 VGA_VSYNC_BUF 1
33 2 VGA_VSYNC
C5B C5A
0.01UF
1 C1
MF
402 1% 1% S D R700
2
U57 22 39
VGA_HSYNC C4 C2 VGA_G 20% 100pF 1/16W
MF
1/16W
MF 1 HPD_ON_RC 1
20K 2 1 Q44
32 5%
1/16W
39 22 22 39
50V
2 CERM 5%
50V
2 CERM
402 2 402 2 R696 G
5% 2N3904
MF 603 100K
C 3 402
34 32
402 5%
1/16W
MF
1
R704 1
1/16W
MF
402
2
SM
C
35 402 2 100K
NOTE: Pulldown for DVI_HPD provided by DVI power switch interface 5%
COMP_DISABLE 1/16W
NOTE: DVI_HPD SHARES Q68 WITH ALS 6
MF
402 2 1
TMDS FILTERING PLACE CLOSE TO CONNECTOR BECAUSE OF BOARD REAL ESTATE NEED PULL-DOWN BECAUSE THIS C703 1 R705
CHGND5
SIGNAL IS TRISTATED INITIALLY
D Q41 47UF 68K
20% 5%
CRITICAL CRITICAL 1 1
R1 2N7002DW 6.3V 1/16W
R706 CERM 2
L72
90-OHM-200MA
SM
SYM_VER-1
L21
165-OHM
SM
SYM_VER-1
5%
1/16W
MF
402 2
0 5%
0
1/16W
MF
2 402
CHGND1
LCD INTERFACE 19 HPD_PWR_SNS_EN
R2131
100K
2 G S
1
SOT-363
1210
MF
2 402
1 4 37 20 TMDS_CLKP 1 4 TMDS_CONN_CLKP 22 37 39
PLACE NEAR C5A & C5B 5%
39 37 20 TMDS_DN<0> TMDS_CONN_DN<0> 22 PLACE NEAR 3, 11 & 19
LVDS INTERFACE 1/16W
MF
402 2
39 37 20 TMDS_DP<0>
2
CRITICAL
3 TMDS_CONN_DP<0> 22
37 20 TMDS_CLKN 2
CRITICAL
3 TMDS_CONN_CLKN 22 37 39
100K pull-ups are for
no-panel case (development)
Panel has 2K pull-ups
C416
0.001uF
1
CHGND4
INVERTER INTERFACE
L73 L74 20% CRITICAL +PBUS
50V
90-OHM-200MA 90-OHM-200MA CERM 2
SM
SYM_VER-1
SM
SYM_VER-1 +3V_SLEEP
402 J6
G-501973
39 37 20 TMDS_DN<1>
1 4 TMDS_CONN_DN<1> 22 39 37 20 TMDS_DN<2>
1 4 TMDS_CONN_DN<2> 22
F-RT-SM
34 L33
FERR-1K-OHM-EMI
39
2 1 38 +12_8V_INV
39 37 20 TMDS_DP<1>
2 3 TMDS_CONN_DP<1> 22 39 37 20 TMDS_DP<2>
2 3 TMDS_CONN_DP<2> 22
1
R3421 R3201 38 +3V_LCD 2
+5V_MAIN
Q7
SM
100K 100K 3
+5V_INV_UF_SW 38
FDG6324L
S-VIDEO/COMP OUT INTERFACE 5%
1/16W
MF
402 2
5%
1/16W
MF
402 2
(LVDS DDC POWER)
NC
4
5
1
SC70-6
3
L32
400-OHM-EMI CRITICAL
Place GND shorts at 39 19 LVDS_DDC_CLK

6 R317 4 S2 D2 2 1 2 1 C746 J7
B graphics controller 39 19 LVDS_DDC_DATA
7
8
100K
5%
1/16W
SM-1
20%
0.001UF 5
SM-2MT
B
XW12 L26 NO STUFF 39 37 19 LVDS_L0N
MF G2 1 C440 2 50V
CERM
FERR-10-OHM-500MA LVDS_L0P 9 402 2 6 10UF 402
SM
C449 1 C452 1 39 37 19
10 FP_PWR_EN_L
20% 1
1 2 38 GPU_TV_GND1 1 2 TV_GND1 38 39
0.001uF 0.001uF 2 6.3V
CERM 2
SM 20% 20% 39 37 19 LVDS_L1N 11 6 805 39
50V 50V +5V_INV_SW 3
CERM 2
38
CERM 2 402 39 37 19 LVDS_L1P 12
D1 4
C712 1 402
13
Q7
0.01UF
20% CHGND4 LVDS_L2N 14 FDG6324L
1 C749
39 37 19
5 G1 0.001UF 6
L25 50V
CERM 2 39 37 19 LVDS_L2P 15 22 19 FP_PWR_EN
S1
SC70-6
L31 20%
50V
3.3UH 603
16 400-OHM-EMI 2 CERM
1 2 1 402
19 GPU_Y CLKLVDS_LN 17 1 39 2 BRIGHT_PWM
39 37 19
0603 18 SM-1
39 37 19 CLKLVDS_LP +3V_PMU
CRITICAL TV_C 19
C702 1 C707 1
J15
39
20
1 C739
560PF 560PF MINIDIN
39 37 19 LVDS_U0N
0.001UF
10% 10% 21 20%
50V
CERM 2
L29 50V
CERM 2
RT-TH
MH1177
39 37 19 LVDS_U0P
50V
2 CERM
402
3.3UH 402 22
C552 1 402
1 2 4 3 39 37 19 LVDS_U1N 23 0.1UF
19 GPU_C TV_Y 39
24 20%
0603 2 1 39 37 19 LVDS_U1P 10V
CERM 2
C718
560PF
1
C724 1
5 TV_COMP 39 LCD POWER SWITCHES 39 37 19 LVDS_U2N
25
26 19 INV_ON_PWM
402
1
14
74LVC32
TSSOP
CHGND2
560PF 8 9 3 BRIGHT_PWM_UF
10%
50V 10% +3V_MAIN 39 37 19 LVDS_U2P 27
U24
CERM 2 L27 50V
CERM 2
10 11 28 2 32 INVERTER EXPECTS ACTIVE HIGH SIGNAL
402 3.3UH 402 29
+3V_LCD_SW 39 37 19 CLKLVDS_UN 7
38
19 GPU_COMP 1 2 30
CLKLVDS_UP
CHGND1 1 C484 39 37 19
C714
0603
C713
R400
100K
2200pF
L6 33 VIDEO CONNECTORS
A 560PF
10%
1
560PF
10%
1 5%
1/16W
MF
1
5%
2 4
3 6
FERR-250-OHM
1 2
C500
0.001uF
SHARES LOGIC WITH KB RESET SIGNALS (PG 28)
A
50V L28 50V 2 402 50V
XW13 CERM 2 CERM 2 2 1
SM 402 FERR-10-OHM-500MA 402 R391 CERM
603
5 SM R724 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
100K 2 2 C474 1 20% 1
0 2
1 2 38 GPU_TV_GND2 1 2 TV_GND2 1 LCD_PWREN_L 50V AGREES TO THE FOLLOWING
38 39
1 0.001uF CERM CHGND4
5%
SM LCD_DIGON_L 5% TSOP 20% 402 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1/16W 50V 1/16W
MF SI3443DV CERM 2 MF II NOT TO REPRODUCE OR COPY IT
C717 1
3
402
Q11 402 402
0.01UF
20%
50V D Q8 CHGND4
C744 SIZE DRAWING NUMBER REV.
Place GND shorts at CERM 2 2N7002 0.01uF
graphics controller
603
22 19 FP_PWR_EN 1 G S
SM 1 2
APPLE COMPUTER INC.

D 051-6459 A
20%
50V SCALE SHT OF
CHGND1
2 CERM
603 CHGND2 NONE 22 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_5_HEAD

TABLE_5_ITEM BOOT BANGER E2PROM
+3V_MAIN 341S1194 1 IC,LMU,P84 U52 CRITICAL ?
+3V_MAIN
MLB - ALS SENSOR 1 C673

0.1UF
LMU +3V_MAIN
BBANG BBANG
1
20%
2 10V
R533 1 C638
10K
CRITICAL
CERM
402 30 27 26 17 IO_RESET_L
1 B4
1 C663
0.1UF
5%
1/16W
MF
VCC
U32
8 0.1UF
20%
2 10V
CERM
SLEEP LED
R550 20% 2 402 16KX8_M24128B
402
VDD
D MLB_ALS_OP_COMP 4
V+
6 MAX4236EUTT
SOT23-6 R619
1K
47
5%
1/16W
U52
2 10V
CERM
402 EEPROM_ADDR 1 E0
SOI
SDA 5 INT_I2C_DATA0 11 13 23 39 +5V_MAIN D
R606 1 MLB_ALS_OUT_FB 1 2 MLB_ALS_OUT ST72264G2H1 2 E1 SCL 6 INT_I2C_CLK0
1K
U40 1%
23 MF
2 402 256KX8 3 E2 BBANG
11 13 23 39
MLB_PHOTODIODE 1 2 MLB_ALS_OP_IN 3 5 1/16W BGA CRITICAL

V- 7
1% 2
MF
402 23 ST7_ICP_SEL_PD B5 TEST PA7/TDO E4 ST7_SENSOR4_SCK_PD 23
WC* EEPROM_WP_PD
OMIT
1/16W SHDN_L ST7_RESET_L A3 RESET* PA6/SDAI F5 INT_I2C_DATA0
VSS 1
BBANG
MF
402
11 13 23 39
4 R532 R7731
CRITICAL
ST7_OSC1 C4 OSC1 XIN PA5/RDI F6 ST7_SENSOR4_SDA_PD 23 10K 2.2K R772 1
ST7_OSC2 B3 OSC2 XOUT PA4/SCLI E6 INT_I2C_CLK0 11 13 23 39
5%
1/16W 5% 100
1
1 1/16W 5%
PD1 R605 1 C670 R617 PA3 C6 JTAG_CPU_TDI 5 39
MF
2 402
MF
402 2
1/16W
MF
BS520 5.1M 0.01UF 1
120K 2 1 C637 PA2 D4 JTAG_CPU_TRST_L 5 39 402 2
5% 20%
TH 1/16W 16V
2 CERM 1 0.1UF PA1/ICCDATA A6 ST7_SENSOR5_SCK_PU SLEEP_LED_L SLEEP_LED_I
MF
2 402 402
5%
1/16W R568 20%
10V NC C1
PA0/ICCCLK A5
23
0 2 CERM ST7_SENSOR5_SDA_PU 23
Q74
2
MF C2
1 1 NC
R615 R618 402
CRITICAL
5%
1/16W
402
NC D1 R777 2N3906
SM
2
15K 1K MF PB7/SS* A2 4.7K 2
1% 1% C675 2 402 NC E5
SLEEP 25 30 33 35 39
SLEEP_LED_SW_L 1 1
1/16W
MF
1/16W
MF 0.22UF Y4 NC D6 NC
PB6/SCK A1 ST7_PB6_PD 23
5%
402 2 2 402 1 2 8.000M PB5/MISO B1 SUTRO_ALS_GAIN_SW 24 39 +3V_MAIN 1/16W
1 2 ST7_XTAL_IN NC D5 MF
PB4/MOSI B2 BBANG_HRESET_L 23 39 402 3
GAIN_SETTING2 20% C5 6
6.3V 8X4.5MM-SM NC
PB3/OCMP2_A C3 PMU_CPU_HRESET_L 23 30 SLEEP_LED_UF
6
CERM
402 C654 1 1 C648 NC B6
PB2/ICAP2_A D2 BBANG_JTAG_TCK
D Q75
27PF 27PF 23
5 2N7002DW
5% 5% LOAD CAPACITANCE = 16PF PB1/OCMP1_A E1 ST7_KBD_LED_OUT SOT-363 1
D Q35 50V
CERM 2
50V
2 CERM
PB0/ICAP1_A F1 MLB_ALS_GAIN_SW
23
RP52 23 ST7_SLEEP_LED_H 2 G S
2N7002DW 402 402 23
10K
SOT-363
23 MLB_ALS_GAIN_SW
2 G S 5%
1/16W +3V_PMU 1
R776
1 L52
PC5/EXTCLK_A/AIN5 F2 SUTRO_ALS_OUT 24 39 SM1 400-OHM-EMI
1 4
10K SM-1
PC4/OCMP2_B/AIN4 E2 PMU_LID_CLOSED_L 23 30 5%
TABLE_ALT_HEAD
(PMU_PWM) 1/16W
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: PC3/ICAP2_B/AIN3 F3 PMU_SLEEP_LED MF NOTE: KEEP L39 CLOSE TO C781
PART NUMBER 2 402 2
PC2/MCO/AIN2 E3 MLB_ALS_OUT 23
1
197S0008 197S0040 Y4 ALT FOR SIWARD
TABLE_ALT_ITEM
PC1/OCMP1_B/AIN1 F4 ST7_SLEEP_LED_H 23
R598
100K
C PC0/ICAP1_B/AINO D3 JTAG_CPU_TMS 5 39
3
5%
1/16W
MF
SLEEP_LED 25 39
C
VSS 2 402 C828 1
+3V_PMU A4 1 C655 1 C636 Q75 D
470pF
0.1UF 0.1UF 2N7002DW 10%
SOT-363 50V
20% 20% S G 5 PMU_SLEEP_LED_L 30 CERM 2
10V 2 10V
R587 2 CERM CERM 603
+5V_SLEEP
SPIDEY FLEX
L47
CRITICAL
39 38 +3V_HALL_EFFECT
1 C660
2
22
5%
1/16W
MF
1
402 402
4
BOOT BANGING SIGNAL DEFINITION
1/ BBANG_HRESET_L (OPEN COLLECTOR OUTPUT - 10K PULLUP ON MLB)
400-OHM-EMI J24 0.001UF 402 2/ PMU_HRESET_L (3V INPUT INTO LMU)
40FLH-SM1-TB 20%
50V 3/ BBANG_JTAG_TCK (REGULAR OUTPUT)
2 1 39 38 +5V_TPAD_SLEEP F-RT-SM 2 CERM
SM-1
41 402 KEYBOARD PULLUPS 4/ JTAG_CPU_TMS (OPEN COLLECTOR OUTPUT - 470OHM PULLUP ON MLB)
5/ JTAG_CPU_TDI (OPEN COLLECTOR OUTPUT - 470OHM PULLUP ON MLB)
39 30 KBD_Y<7>
1 6/ JTAG_CPU_TRST_L (OPEN COLLECTOR OUTPUT - 470OHM PULLUP ON MLB)
1 C814 2
+3V_PMU
0.001UF 39 30 KBD_Y<6>
R771
20% 3 100K 2
2 50V
CERM 4 39 30 23 KBD_ID 1
402 39 30 KBD_Y<5> MAXBUS_SLEEP
5% 38 34 23 16 15 8 7 5 +3V_MAIN
39 30 KBD_Y<4>
5 1/16W
MF
6 BBANG
39 30 KBD_Y<3>
39 30 KBD_Y<2>
7
402
RP43 R62 1 LMU PULL-DOWNS

39 30 KBD_Y<1>
8 10K 10K
+3V_MAIN
9
5% 5%
1/16W
RP53
39 30 KBD_Y<0> 1/32W
25V MF 10K
10 402 2 ST7_SENSOR5_SDA_PU 1 8
Q73 39 30 23 KBD_X<9>
5 SN74AUC1G08
23
2N3906 2 39 30 23 KBD_X<8>
11 39 30 23 KBD_X<6> 3 5 PULL-UP FOR I2C (IN-CIRCUIT PROGRAMMING) 5%
SM
39 30 23 KBD_X<7>
12 KBD_X<7> 7 10
BBANG_TCK_EN 1
A
SC70-5
RP53 1/16W
SM1
1 39 30 23
4 10K
30 NUMLOCK_LED_L
39 30 23 KBD_X<6>
13 39 30 23 KBD_X<8> 4
2
U4 Y JTAG_CPU_TCK 5 39
23 ST7_SENSOR5_SCK_PU 2 7
23 BBANG_JTAG_TCK B BBANG
39 30 23 KBD_X<5>
14 39 30 23 KBD_X<9> 6 5%
B 3 R770
200 39 30 23 KBD_X<4>
15
16
39 30 23 KBD_X<2> 1
2
3
INPUTS ARE 3V TOLERANT
1/16W
SM1
RP52
2
10K
7
B
NUMLOCK_LED 2 1 39 KBD_NUMLOCK_LED 39 30 23 KBD_X<4> 23 ST7_SENSOR4_SDA_PD
5% 17 39 30 23 KBD_X<3> 9 5%
1/16W
MF 39 30 23 KBD_X<3>
18 39 30 23 KBD_X<5> 8 RP52 1/16W
SM1
402
19 38 34 23 16 15 8 7 5 MAXBUS_SLEEP 10K
39 30 23 KBD_X<2> ST7_SENSOR4_SCK_PD 1 8
SM 23
39 30 23 KBD_X<1>
20 +3V_SLEEP
5%
+3V_MAIN
39 30 23 KBD_X<0>
21
RP42 1/16W
SM1
RP53
22 10K 10K
39 30 23 KBD_SHIFT_L 3 6
Q33 23
5% NO_BBANG 23 ST7_PB6_PD
2N3906 2 1/32W
25V
BBANG BBANG R6 5%
SM
1
39 30 23 KBD_OPTION_L
24
R39 1
R40 1
1
0 2 RP53 1/16W
SM1
30 CAPSLOCK_LED_L
39 30 23 KBD_COMMAND_L
25 39 30 23 KBD_FUNCTION_L 1 5 10K 10K 10K
5% 5% 5% 23 ST7_ICP_SEL_PD 4 5
39 30 23 KBD_CONTROL_L
26 39 30 23 KBD_CONTROL_L 2 10 1/16W 1/16W 1/16W
3 R582 39 30 23 KBD_FUNCTION_L
27 39 30 23 KBD_SHIFT_L 8 MF
402 2
MF
402 2
MF
402
5%
1/16W
2
200 1 28 9 SM1
CAPSLOCK_LED 39 KBD_CAPSLOCK_LED 39 30 23 KBD_COMMAND_L 5 SN74AUC1G08
1 SC70-5
5%
1/16W
L46 39 30 23 KBD_ID
29 NC 6 30 23 PMU_CPU_HRESET_L A
MF 400-OHM-EMI 30 39 30 23 KBD_OPTION_L 3 U2 Y
4 CPU_HRESET_L 5 7 39
402 BBANG_HRESET_L 2
34 30 22 SOFT_PWR_ON_L
2 1 39 25 PWR_BUTTON_L 31 39 30 23 KBD_X<1> 7 39 23 B BBANG
SM-1 39 38 23 KBD_LED2_OUT 32 39 30 23 KBD_X<0> 4 3 INPUTS ARE 3V TOLERANT
39 38 23 KBD_LED1_OUT 33
SM
L49 34
400-OHM-EMI 35
30 23 PMU_LID_CLOSED_L 2 1 39 LID_CLOSED_L 36
SM-1 37
L11 39 TPAD_F_RXD 38 KB LED DRIVER R581

400-OHM-EMI
1 2
39
40
17.4K2
1 ST7_KBD_LED_OUT 23
LMU/BOOTBANGER/SPIDEY
TPAD_RXD TPAD_F_TXD
A 30
SM-1
39
CRITICAL
U35
1%
1/16W
A
L48 42
MAX1916
MF
402
400-OHM-EMI SOT23-6
6 LED1 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
39 38 23 KBD_LED1_OUT SET 3 KBD_LED_SET
R552 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
TPAD_TXD 1 2 AGREES TO THE FOLLOWING
30
39 38 23 KBD_LED2_OUT 5 LED2 2.2K 2
SM-1 EN 1 KBD_LED_EN 1
C656 1 1 C815 1 C816 NC 4 LED3
5%
0.001UF 0.001UF GND 1/16W 1 II NOT TO REPRODUCE OR COPY IT

0.001UF 20% 20%
2 MF R534
20% 50V 402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
50V 2 50V
CERM
2 CERM 10K
CERM 2 402 402 5%
402 1/16W SIZE DRAWING NUMBER REV.
MF
2 402
APPLE COMPUTER INC.
D 051-6459 A
SCALE SHT OF
NONE 23 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
HARD DRIVE INTERFACE (UATA100)
+3V_SLEEP
EIDE SERIES TERMINATION WIRELESS INTERFACE +5V_HD_SLEEP 33 38

PLACE SERIES R CLOSE TO INTERPID
PLACE TERMINATORS NEAR INTREPID +3V_SLEEP
3V_HD_LOGIC 5V_HD_LOGIC
CRITICAL RP2 R6021 1

R601
33 0 0
RP50 J20 UIDE_DATA<11> 4 5 HD_DATA<11>
5%
1/16W
5%
1/16W CRITICAL
33 37 13 24 37
MF MF
37 13 EIDE_DATA<8> 1 8 EIDE_OPTICAL_DATA<8> 24 37 39 QT510806-L111 RP9 5% 402 2 2 402 J13 D
D RP13
33
5%
1/16W
F-ST-SM1
84 81 37 13 UIDE_DATA<3> 2
33
7
1/16W
SM1
HD_DATA<3> 24 37
1
M-ST-SM1
50
SM1 HD_RESET_L
37 13 EIDE_DATA<10> 1 8 EIDE_OPTICAL_DATA<10> 24 37 39 5%
1/16W
RP9 37 24
2 49
5% RP13 39 30 26 20 18 17 14 MAIN_RESET_L 2 1 SM1 1
33 8
1/16W UIDE_DATA<1> HD_DATA<1> 3 48
SM1 33 39 RF_DISABLE_L_SPN 4 3 CLK33M_AIRPORT 12 36 39
37 13 24 37
37 24 HD_DATA<7> HD_DATA<8> 24 37
EIDE_DATA<9> 2 7 EIDE_OPTICAL_DATA<9> 24
37 13 37 39
39 12 AIRPORT_PCI_REQ_L 6 5 RP9 5%
1/16W 37 24 HD_DATA<6> 4 47 HD_DATA<9> 24 37
RP49 5%
8 7 AIRPORT_PCI_GNT_L
PCI_AD<18> 9 12 17 24 26 37 39 33 SM1 5 46
1/16W 12 39 UIDE_DATA<2> 3 6 HD_DATA<2>
33 SM1
PCI_AD<31> 10 9 AIRPORT_PME_L_TP
37 13 24 37
37 24 HD_DATA<5> 6 45 HD_DATA<10> 24 37
37 13 EIDE_DATA<11> 3 6 EIDE_OPTICAL_DATA<11> 24 37 39
39 37 26 17 12 9
12 11
5%
1/16W
RP2 37 24 HD_DATA<4> 7 44 HD_DATA<11> 24 37
5% RP13 AIRPORT_PCI_INT_L 14 39 2
R745 SM1 1
33 8 8
1/16W UIDE_DATA<0> HD_DATA<0> 43
33 PCI_AD<29> 14 13 PCI_AD<30> 37 13 24 37
SM1
39 37 26 17 12 9 9 12 17 26 37 39 22
39 37 26 17 12 9 PCI_AD<27> 16 15 5%
1/16W
RP9 5%
1/16W
37 24 HD_DATA<3> 9 42 HD_DATA<12> 24 37
RP10 5% PCI_AD<25> 18 17 PCI_AD<28> MF 33 SM1 37 24 HD_DATA<2> 10 41 HD_DATA<13> 24 37

1/16W 39 37 26 17 12 9 9 12 17 26 37 39 UIDE_DATA<7> 4 5 HD_DATA<7>
1 402
37 13
33 SM1 20 19 PCI_AD<26>
24 37
11 40
22 21
9 12 17 26 37 39
5%
1/16W
RP2 HD_DATA<1> 12 39 HD_DATA<14>
5% RP50 39 37 26 17 12 PCI_CBE<3> PCI_AD<24> 9 12 17 26 37 39 33 37 24 24 37
1/16W
33 24 23 39 AIRPORT_IDSEL R81 37 13 UIDE_DATA<5>
SM1 3 6 HD_DATA<5> 24 37 37 24 HD_DATA<0> 13 38 HD_DATA<15> 24 37
EIDE_DATA<13>
SM1 3 6 EIDE_OPTICAL_DATA<13> 10K 14 37
37 13 24 37 39
39 37 26 17 12 PCI_AD<23> 26 25 5%
1/16W
RP2 5%
1/16W 15 36
RP10 5% 39 37 26 17 12 PCI_AD<21> 28 27 PCI_AD<22> 12 17 26 37 39 MF 33 SM1 37 13 HD_DMARQ HD_DIOW_L 24 37
1/16W 402 2 37 13 UIDE_DATA<4> 2 7 HD_DATA<4> 24 37 16 35
33 SM1 39 37 26 17 12 9 PCI_AD<19> 30 29 PCI_AD<20> 9 12 17 26 37 39
37 24 HD_DIOR_L HD_IOCHRDY 24 37
32 31 PCI_PAR 12 17 26 37 39
5%
1/16W
RP3 17 34
5% RP10 SM1 1
33 8 HD_DMACK_L 18 33 HD_INTRQ
1/16W PCI_AD<17> 34 33 PCI_AD<18> UIDE_DATA<6> HD_DATA<6> 37 24 13 37
SM1 33 39 37 26 17 12 9 9 12 17 24 26 37 39 37 13 24 37
HD_ADDR<1> 19 32 HD_ADDR<2>
37 13 EIDE_DATA<2> 7 2 EIDE_OPTICAL_DATA<2> 24 37 39 36 35 PCI_AD<16> 9 12 17 26 37 39 RP3 5%
1/16W
37 24
20 31
24 37
RP50 5% 39 37 26 17 12 PCI_CBE<2> 38 37 33 SM1

1/16W 37 13 UIDE_DATA<8> 2 7 HD_DATA<8> 24 37 21 30
33 SM1 39 37 26 17 12 PCI_IRDY_L 40 39 PCI_FRAME_L 12 17 26 37 39
37 24 HD_ADDR<0> HD_CS1_L 24 37
42 41 PCI_TRDY_L 12 17 26 37 39
5%
1/16W
RP4 37 24 HD_CS0_L 22 29
5% RP50 SM1 33 23 28
1/16W AIRPORT_CLKRUN_L 44 43 PCI_STOP_L UIDE_DATA<9> 4 5 HD_DATA<9>
SM1 7
33 2
39 12 17 26 37 39 37 13 24 37
24 27
EIDE_DATA<0> EIDE_OPTICAL_DATA<0> 46 45 PCI_DEVSEL_L
37 13 24 37 39
48 47
12 17 26 37 39
RP3 5%
1/16W 38 +HD_LOGIC_SLEEP 25 26
RP10 5% PCI_CBE<1> 33
C 33
1/16W
SM1
39 37 26 17 12
39 37 26 17 12 9 PCI_AD<14> 50 49 PCI_AD<15> 9 12 17 26 37 39
37 13 UIDE_DATA<10> 3 6
SM1
HD_DATA<10> 24 37 C
37 13 EIDE_DATA<3> 5 4 EIDE_OPTICAL_DATA<3> 24 37 39 52 51 PCI_AD<13> 9 12 17 26 37 39
5%
1/16W
RP4 R6031 1
R101
5% RP13 PCI_AD<12> 54 53 PCI_AD<11> SM1 33
1/16W 39 37 26 17 12 9 9 12 17 26 37 39
37 13 UIDE_DATA<14> 2 7 HD_DATA<14> 24 37 20K 10K
SM1 33 PCI_AD<10> 56 55 5% 5%
39 37 26 17 12 9
58 57
RP4 5%
1/16W
1/16W
MF
1/16W
MF
RP49 5% 39 12 9 ROM_RW_L PCI_AD<9> 9 12 17 26 37 39 33 402 2
1/16W 60 59 UIDE_ADDR<0> 3 6 SM1
HD_ADDR<0> 2 402
33 SM1 39 37 26 17 12 9 PCI_AD<8> PCI_CBE<0> 12 17 26 37 39
37 13 24 37
39 37 26 17 12 9 PCI_AD<7> 62 61 ROM_OE_L 9 12 39
5%
1/16W
RP5
5% RP49 64 63 PCI_AD<6> SM1 33
1/16W 9 12 17 26 37 39
37 13 UIDE_CS0_L 2 7 HD_CS0_L 24 37
SM1 33 PCI_AD<5> 66 65
EIDE_DATA<4> 7 2 EIDE_OPTICAL_DATA<4> 39 37 26 17 12 9
37 13 24 37 39
39 9 ROM_ONBOARD_CS_L 68 67 PCI_AD<4> 9 12 17 26 37 39
RP5 5%
1/16W
RP49 5% 33 SM1
1/16W PCI_AD<3> 70 69 PCI_AD<2> UIDE_ADDR<1> 1 8 HD_ADDR<1>
37 13 EIDE_DATA<5> 5
33
4
SM1
EIDE_OPTICAL_DATA<5> 24 37 39
39 37 26 17 12 9
72 71 PCI_AD<0>
9 12 17 26 37 39
9 12 17 26 37 39
37 13
5% RP5
24 37
ANY SEQUENCING REQUIREMENT BETWEEN
1/16W
5%
1/16W
RP11 39 37 26 17 12 9 PCI_AD<1> 74 73
UIDE_DATA<15>
SM1 4
33
5 HD_DATA<15>
+5V_HD_SLEEP AND +3V_SLEEP?
SM1 33 39 12 9 ROM_CS_L 76 75 NC
37 13 24 37
37 13 EIDE_CS0_L 3 6 EIDE_OPTICAL_CS0_L 24 37 39
NC 78 77 NC
RP3 5%
1/16W
RP11 5% R7301 33 SM1
1/16W NC 80 79 37 13 UIDE_DATA<13> 4 5 HD_DATA<13> 24 37
33 SM1 10K
37 13 EIDE_ADDR<1> 1
5%
1/16W
8
RP11
33
EIDE_OPTICAL_ADDR<1> 24 37 39 5%
1/16W
MF
402 2
83 82
37 13 UIDE_DATA<12>
5%
1/16W
SM1 1
RP4
33
8 HD_DATA<12> 24 37
BLUETOOTH/LEFT-SIDE USB
SM1 4 5
EIDE_ADDR<2> EIDE_OPTICAL_ADDR<2>
37 13 24 37 39
RP5 5%
1/16W CRITICAL
RP11 5%
1/16W 3
33 6
SM1
33 SM1 37 13 UIDE_ADDR<2> HD_ADDR<2> 24 37
+5V_MAIN +3V_MAIN J3
37 13 EIDE_ADDR<0> 2 7 EIDE_OPTICAL_ADDR<0> 24 37 39 5% 54550-1490
5%
1/16W
SM1 R75 F-RT-SM
15
1 1/16W 33
R36 SM1 37 13 UIDE_CS1_L 2 1 HD_CS1_L 24 37
10K
5%
1/16W
OPTICAL DRIVE INTERFACE (EIDE) 5%
1/16W
MF
1
2
B MF
2 402
+5V_SLEEP
402 39 37 14 BT_USB_DP
39 37 14 BT_USB_DM
3 B
4
5
NO STUFF NO STUFF
PLACE PULLUP RESISTORS CLOSE TO INTREPID 39 37 26 LEFT_USB_DP 6
R31 1 1 1
39 37 26 LEFT_USB_DM 7
1
33 2 R452 R442 R411 +3V_SLEEP 8
37 13 EIDE_CS1_L EIDE_OPTICAL_CS1_L 24 37 39
100K 10K 10K 39 26 NEC_LEFT_USB_PWREN
9
5% 5% CRITICAL 5% 5%
1/16W
MF R116 1/16W
MF J10 1/16W
MF
1/16W
MF 39 23 SUTRO_ALS_OUT
10
402
1
82 2
402 2 M-ST-SM1 2 402 2 402 39 26 NEC_LEFT_USB_OVERCURRENT
11
37 13 EIDE_DMARQ EIDE_OPTICAL_DMA_RQ 24 37 39
1 50 39 23 SUTRO_ALS_GAIN_SW
12
5% NC EIDE_OPTICAL_RST_L 24 37 39
R95 1/16W
MF 2 49
R631
1
R612 13
37 13 EIDE_DMACK_L 1
22 2
402
EIDE_OPTICAL_DMAACK_L EIDE_OPTICAL_DATA<8> 3 48 EIDE_OPTICAL_DATA<7> 10K 10K R941 14
24 37 39 39 37 24 24 37 39
5% 5% 10K
5% EIDE_OPTICAL_DATA<9> 4 47 EIDE_OPTICAL_DATA<6> 1/16W 1/16W 5% 1 1
1/16W
MF R30
39 37 24
EIDE_OPTICAL_DATA<10> 5 46 EIDE_OPTICAL_DATA<5>
24 37 39
MF
402 2
MF
2 402
1/16W
MF
R71 R64 16
402 22
39 37 24 24 37 39
402 2 15K 15K
37 13 EIDE_RD_L 1 2 EIDE_OPTICAL_RD_L 24 37 39 39 37 24 EIDE_OPTICAL_DATA<11> 6 45 EIDE_OPTICAL_DATA<4> 24 37 39
5% 5%
1/16W 1/16W
5% 7 44 R74 MF MF
R32 1/16W
8 43
33 2 402 2 402
MF 39 37 24 EIDE_OPTICAL_DATA<12> EIDE_OPTICAL_DATA<3> 24 37 39 37 13 UIDE_RST_L 1 2 HD_RESET_L 24 37
1
22 2
402
9 42
37 13 EIDE_WR_L EIDE_OPTICAL_WR_L 24 37 39 39 37 24 EIDE_OPTICAL_DATA<13> EIDE_OPTICAL_DATA<2> 24 37 39 5%
5% 39 37 24 EIDE_OPTICAL_DATA<14> 10 41 EIDE_OPTICAL_DATA<1> 24 37 39
1/16W
MF R613
1/16W
R76 11 40
402
1
22 2
MF 39 37 24 EIDE_OPTICAL_DATA<15> EIDE_OPTICAL_DATA<0> 24 37 39 37 13 UIDE_DMACK_L HD_DMACK_L 24 37
402
1
82 2 12 39
37 13 EIDE_IOCHRDY EIDE_OPTICAL_IOCHRDY 24 37 39 5%
5% 39 37 24 EIDE_OPTICAL_DMA_RQ 13 38 EIDE_OPTICAL_WR_L 24 37 39
R35 1/16W
MF
R81 1/16W
MF EIDE_OPTICAL_RD_L 14 37 EIDE_OPTICAL_IOCHRDY UIDE_DIOR_L 1
22 2
402
HD_DIOR_L
39 37 24 24 37 39 37 13 24 37
1
82 2
402
15 36
37 13 EIDE_INT EIDE_OPTICAL_INT 24 37 39 39 37 24 EIDE_OPTICAL_DMAACK_L EIDE_OPTICAL_INT 24 37 39 5%
5%
1/16W
R69
16 35 EIDE_OPTICAL_ADDR<1> 24 37 39
1/16W
MF
402
R68
22
INTERNAL I/O CONNECTORS
A 37 13 EIDE_RST_L
MF
402
1
33 2 EIDE_OPTICAL_RST_L 24 37 39
39 37 24
39 37 24
EIDE_OPTICAL_ADDR<2>
EIDE_OPTICAL_CS1_L
17
18
34
33
EIDE_OPTICAL_ADDR<0>
EIDE_OPTICAL_CS0_L
24 37 39
24 37 39
37 13 UIDE_DIOW_L 1
5%
2 HD_DIOW_L 24 37

A
1/16W
5% 19 32 MF
1/16W
MF R4411 20 31 1
R458 R93 402 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
402
21 30
82 AGREES TO THE FOLLOWING
20K 10K 37 13 UIDE_IOCHRDY 1 2 HD_IOCHRDY 24 37
5% 22 29 5% I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1/16W NC NC 1/16W 5%
MF MF 1/16W II NOT TO REPRODUCE OR COPY IT
23 28
402 2
24 27
2 402 1 C86 MF
402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
10PF
25 26 5%
50V SIZE DRAWING NUMBER REV.
2 CERM
402
APPLE COMPUTER INC.

D 051-6459 A
SCALE SHT OF
IOCHRDY - UATA100 REQUIRES PULL-UP TO 3.3V NONE 24 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+5V_MAIN
OMIT SERIAL DEBUG INTERFACE
L77
39 14 SND_SYNC
FERR-220-OHM
1 2
SOUND BOARD (SOUSAPHONE)
SND_SYNC_F 25
2
RP44 +5V_MAIN
0402 NO STUFF AUDIO - SNAPPER 100K
5%
1 C895 1/16W
OMIT 20%
0.01UF SND - INTREPID 7
SM1
L80 16V SERIAL_DEBUG
36 14
39
SND_CLKOUT
FERR-220-OHM
1
0402
2
2 CERM
402
SND_CLKOUT_F
NO STUFF
25
+3V_MAIN
+5V_MAIN
39 25 SND_AMP_MUTE
6
SUPPORTS BOTH THE LAST DASH AND Q52 SOFT MODEM
MODEM M-ST-5087
CRITICAL
J16
1 C899 Q26 D SM
D OMIT
20%
0.01UF 2N7002DW
SOT-363
2 +5V_MAIN +3V_MAIN
39 14 COMM_TXD_L 1 10 COMM_DTR_L 14 39 D
L81 2 16V
CERM
S G SND_AMP_MUTE_L 14
39 14 COMM_TRXC 2 9 COMM_RTS_L 14 39
FERR-220-OHM 402 CRITICAL 3 8
1 5
1 2 4 7
39 14 INT_AUDIO_TO_SND INT_AUDIO_TO_SND_F 25
J12 AMP_CONTROL 25 RP44 NO STUFF NO STUFF
39 14 COMM_GPIO_L
5 6
COMM_RXD 14 39
0402 NO STUFF QT510306-L111 1
1 C896 F-ST-SM1
3
100K
5%
1 C767 1 C513 R405 1 C478 1 C469
OMIT 0.01UF 25 INT_AUDIO_TO_SND_F 1 2 SND_TO_AUDIO_F 25 1/16W 10UF 0.1UF 10K 0.1UF 10UF
20% 5% 20%
L82 20%
2 16V
3 4 SND_HP_SENSE_L 14 39
Q26 D
4
SM1 20%
6.3V 10V
2 CERM 1/16W 10V
2 CERM
20%
6.3V
FERR-220-OHM CERM 6
2N7002DW 2 CERM
402
MF
402
2 CERM
402 39 25 14 INT_I2C_CLK2 5 SND_LIN_SENSE_L 14 39 SOT-363
5
805 2 402 805
S G INT_PU_RESET_L 13 30
39 14 SND_TO_AUDIO 1 2 SND_TO_AUDIO_F 25 25 SND_SCLK_F 7 8
0402 NO STUFF 9 10 CRITICAL
SND_AMP_MUTE_F 25 4
1 C897 25 SND_CLKOUT_F 11 12 SLEEP 23 30 33 35 39
J8
OMIT 0.01UF QT510166-L010
14
L76 20%
16V
2 CERM
25 SND_SYNC_F 13
15 16 1
F-ST-SM1
2
DEBUG POWER BUTTON
FERR-220-OHM 39 25 14 INT_I2C_DATA2 SND_HW_RESET_L_F 25 39 14 MOD_DTO MOD_SYNC 14 39
402 +3V_MAIN
39 23 SLEEP_LED 17 18 39 14 MOD_CLKOUT 3 4 INT_MOD_DTI 14 39
25
1
SND_AMP_MUTE 2 SND_AMP_MUTE_F 25 NO STUFF
39 NO STUFF 19 20 5 6 MOD_BITCLK 14 39
0402
1 C898 21 22 SND_HP_MUTE_INV 25 39 1 39 14 COMM_RESET_L 7 8 R527
0.01UF 24 9 10 0
OMIT 20%
16V
23
25 26
RP44 1
R689 39 14 COMM_SHUTDOWN
11 12
MODEM_USB_DM 14 37 39
39 23 PWR_BUTTON_L 1 2
L78 2 CERM 100K 100K 39 25 14 INT_I2C_CLK2 MODEM_USB_DP 14 37 39 5%
402 5% 1/16W
FERR-220-OHM 27 28
1/16W
5%
1/16W 39 25 14 INT_I2C_DATA2 13 14 COMM_RING_DET_L 14 30 39 MF
29 30 SM1 MF 15 16 603
1
SND_HW_RESET_L 2 SND_HW_RESET_L_F 8
14
39
25
2 402
0402
1
NO STUFF
C900 XW9
SM 39 25 SND_HP_MUTE_INV
OMIT 0.01UF 1 2 38 SND_AGND
20%
L79 16V
2 CERM 6
FERR-220-OHM 402
39
14 SND_SCLK
1 2 SND_SCLK_F 25
Q31 D
+5V_SLEEP
2N7002DW
C
36
0402
1
NO STUFF
C901
SOT-363
S G 2 SND_HP_MUTE
+3V_MAIN
FAN CONTROLLER DEBUG JUMPERS C
0.01UF R814
20% 1 3 10 NO STUFF
2 16V
CERM
1 2 ADT7460_VCC
402 Q31 D
5% R537
2N7002DW 1/16W 1 C904 +5V_SLEEP 0
SOT-363 MF PMU_NMI_BUTTON_L 1 2
S G 5 SND_HP_MUTE_L 14 402 1UF 1 1 30
20%
10V
R293 R295 5%
TABLE_11_HEAD
4 6 2 CERM 10K 10K 1/16W

PART # QTY DEVICE PACKAGE DESCRIPTION VALUE VOLT. WATT. TOL. REFERENCE DESIGNATOR(S) BOM OPTION 5% 5% MF
603 1/16W 1/16W 603
116S1000 7 RES RES-402-V2 RESISTOR 0 1/16W 5%
TABLE_11_HEAD
AMP_CONTROL
RP44 MF MF
L77,L80,L81,L82,L76,L78,L79 25
100K 2 402 2 402
5%
1/16W 1 NO STUFF
SM1
C711 1 1 R692 1
R695 FANL_PWM 25
PLACE XW9 CLOSE TO 5V SWITCHER (U27) 3
0.1UF
R42 5%
10K 10K 39 R553
20% 10K 1/16W 5% 6 0
PLACE CAPS AS CLOSE TO THERMISTORS AS POSSIBLE CAPS FOR EMI EXPERIMENTATION ONLY 10V
CERM 2
3 5%
1/16W MF 1/16W
MF
30 PMU_RESET_BUTTON_L1 2
402 VCC MF 2 402 2 402

D
Q78 FANR_PWM 25 39
5%
1/16W
PLACE IN BETWEEN 3/5/1.5/2.5V PWR SUPPLY U3 2 402 2N7002DW
SOT-363 MF
2 3 603
25 SUPPLY_M_DP
MAIN1
FAN INTERFACE 5 ADT7460_VCORE_MON
39 14 13 INT_I2C_DATA1
39 14 13 INT_I2C_CLK1
14
16
1
+2.5V/ QSOP
SMBALERT#
SDA
SCL
ADT7460
PWM1/ 15
XTO
TACH1 6
PWM2/ 5
ADT7460_FAN1_PWM
FANL_TACH
ADT7460_FAN2_PWM
G
25 39
S
5 G
D
S
Q78
2N7002DW
SOT-363
3 SMBALERT#
1 C681 37 25 THERM1_DP 13 D1+ TACH2 7 FANR_TACH 25 4
0.001UF 1 Q66 CRITICAL
20% KEEP STUFFING RESISTORS CLOSE TO ADT7460 CONTROLLER 37 25 THERM1_DM
12 D1- PWM3/ 8 ADT7460_ADR_EN_L
2 50V 2N3904
CERM
402
2
SM
R719 37 25 THERM2_DP
11 D2+
ADR ENABLE#
TACH3 4 NC
RIGHT FAN (GPU)
25 SUPPLY_M_DM 0 37 25 THERM2_DM
10 D2-
25 CPU_M_DP 1 2 THERM1_DP 25 37 TACH4/ 9 ADT7460_THERM
5% NO STUFF NO STUFF ADR SELECT/ 25
+5V_SLEEP
1/16W THERM#
B R725 MF
402
1 C690 1 C905 B
1
0 2 NO STUFF 0.001UF 0.001UF GND
25 CPU_M_DM THERM1_DM 25 37 20% NO STUFF 20%
PLACE CLOSE TO CPU 50V
2 CERM 50V
2 CERM 2
MAIN2
5%
1/16W
1 C688 402
1 C846 402
1
R623 CRITICAL
MF
402
R713 0.001UF
20%
0.001UF
20% 10K J2
1
0 2 50V 50V 5% SM-2MT
CPU_M_DP 25 SUPPLY_M_DP THERM2_DP 25 37 2 CERM 2 CERM 1/16W
25
402 402 MF 4
5%
3 1/16W 2 402
1 C668 R716 MF
402
0.001UF 0 1
20%
1 Q39 25 SUPPLY_M_DM 1 2 THERM2_DM 25 37
39 38 FANR_GND 2
50V
2 CERM 2N3904 5%
SM 1/16W FANR_TACH 3
25 CPU_M_DM
402 2 MF
402 LEFT FAN (CPU) 25
1
2
5
6
5
THERM ISOLATION +5V_SLEEP
SI3446DV
PLACE CLOSE
Q36
TO CONNECTOR
TSOP
+3V_MAIN
PLACE UNDERNEATH UPPER RAM 1 C135
+3V_PMU_AVCC
CRITICAL 4.7UF
30 38 20%
ALTERNATE1 J4 10V
2 CERM
1
R679 SM-2MT 1206
4
1 1
37 25 THERM1_A_DP
KEEP STUFFING RESISTORS CLOSE TO ADT7460 CONTROLLER R811 R812 10K
5%
4
NO STUFF 3 100K 100K 1/16W FANR_PWM

NO STUFF 5% 5% MF 39 25
NO STUFF 1/16W 1/16W 1
1 C678 1 Q47 MF MF 402 2
0.001UF R723 2 402 2 402 2
20% 2N3904 0 FANL_TACH 3
2 50V
CERM SM
37 25 THERM1_A_DP 1 2 THERM1_DP 25 37
THERM_L_OC 30
39 25
402 2
5% 39 38 FANL_GND
NO STUFF 3 5
37 25 THERM1_A_DM 1/16W
R726 MF FAN/MODEM/SOUND/SLEEP LED/DEBUG
402 D
Q87
A 37 25 THERM1_A_DM 1
0 2 THERM1_DM 25 37
1
R813 2N7002DW
SOT-363 A
1
2
5
6
100K THERM_INV 5 G S NOTICE OF PROPRIETARY PROPERTY
5%
PLACE CLOSE TO BATTERY CHARGER/VCORE 1/16W NO STUFF 5% PLACE CLOSE
SI3446DV
MF 1/16W TO CONNECTOR
ALTERNATE2 402 R710 MF
2 402
6 4 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
C134
Q37
0 1 C903 1 AGREES TO THE FOLLOWING
TSOP
37 25 THERM2_A_DP 1 2 THERM2_DP 25 37 D
Q87 0.1UF 4.7UF I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
37 25 THERM2_A_DP 5% 2N7002DW 20% 20%
NO STUFF 1/16W
2 SOT-363 10V
2 CERM 2 10V
CERM II NOT TO REPRODUCE OR COPY IT
MF 25 ADT7460_THERM G S
NO STUFF 3 NO STUFF 1206
1 C651 R717 402 402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
0
4
1
20%
0.001UF 1 Q62 37 25 THERM2_A_DM 1 2 THERM2_DM 25 37 SIZE DRAWING NUMBER REV.
2N3904
50V
2 CERM
402 2
SM
5%
1/16W
MF
402
39 25 FANL_PWM
APPLE COMPUTER INC.

D 051-6459 A
37 25 THERM2_A_DM SCALE SHT OF
NONE 25 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+3V_NEC_VDD 26 38
NEC_USB NEC_USB NEC_USB NEC_USB TABLE_ALT_HEAD
1 C841 1 C837 1 C843 1 C836 PART NUMBER ALTERNATE FOR

PART NUMBER
BOM OPTION REF DES COMMENTS:
0.1uF 0.1uF 0.1uF 0.1uF
20% 20% 20% 20% NEC_USB TABLE_ALT_ITEM
10V 10V 10V 10V

2 CERM 2 CERM 2 CERM 2 CERM +3V_MAIN 197S0608 197S0038 NEC_USB Y5 ALT FOR SIWARD
402 402 402 402 L54
FERR-EMI-100-OHM
NEC_USB NEC_USB NEC_USB NEC_USB
1 2
1 C840 1 C829 1 C834 1 C838 SM
38 NEC_AVDD
0.1uF 0.1uF 0.1uF 0.1uF NEC_USB NEC_USB NEC_USB

20% 20% 20% 20%
10V
2 CERM
10V
2 CERM
10V
2 CERM
10V
2 CERM
1 C839 1 C844 C667
402 402 402 402 NEC_USB 0.1uF 0.1uF 10uF Y7 LOAD CAPACITANCE IS 16PF
1 20% 20% 20%
R796 10V
2 CERM
10V
2 CERM
6.3V
D 1
NEC_USB
C842
NEC_USB
C845 1
NEC_USB
C830 1
NEC_USB
C833 0
5%
1/16W
402 402
CERM
805 CRITICAL
NEC_USB
D
0.1uF 10uF 0.1uF 0.1uF
20%
10V
20%
6.3V
20%
10V
20% MF
2 603
Y5
2 CERM CERM 2 CERM 2 10V
CERM 30.0000M +3V_MAIN
402 805 402 402 1 2 NEC_XT2_R
38 8X4.5MM-SM NEC_USB NEC_USB
26 +3V_NEC_VDD
1 C649 1 C657 1R590 7 NEC_USB 8 NEC_USB
27PF 27PF 100
P12
A13
A12
L13
J13
H13
F13
D13
G12
N10
N12
RP45 RP45
H3
M4
C8
P2
P3
A3
E2
N8
H4
D7
5% 5% 5%
2 50V
CERM 2 50V
CERM 1/16W 10K 10K
M5 402 402 MF
39 37 24 17 12 9 PCI_AD<0> AD0 5% 5%
2 402 1/16W 1/16W
VDD_PCI
VDD
AVDD
39 37 24 17 12 9 PCI_AD<1>
P5 AD1 XT1/SCLK L9 36 NEC_XT1 NEC_USB SM1 SM1
N5 P8 2 1
39 37 24 17 12 9 PCI_AD<2> AD2 XT2 36 NEC_XT2
39 37 24 17 12 9 PCI_AD<3>
P4
AD3 R795 NEC_USB
39 37 24 17 12 9 PCI_AD<4>
N4
AD4 Low/Full/High Speed (External) RSDM1 M14 37 NEC_USB_RSDM1 1 2 NEC_USB_DAM 26 37
R591
M3 CRITICAL 15K
39 37 24 17 12 9 PCI_AD<5> AD5 DM1 M13 (NEC_USB_DAM) 1% 402 26 NEC_OCI<1> 1 2 NEC_LEFT_USB_OVERCURRENT 24 39
N3 NEC_USB 36
39 37 24 17 12 9 PCI_AD<6> AD6 DP1 L14 (NEC_USB_DAP) NEC_USB 5%
39 37 24 17 12 9 PCI_AD<7>
M1
AD7 U39 RSDP1 K13 37 NEC_USB_RSDP1 NEC_USB_DAP 26 37
1/16W
MF
402
NEC_USB
SERR_L AND PERR_L 39 37 24 17 12 9 PCI_AD<8>
L2
AD8 NEC_UPD720101_USB2 R792 R600
HAS DEDICATED PULL-UP 39 37 24 17 12 9 PCI_AD<9>
L1
AD9 FBGA RSDM2 K14 37 NEC_USB_RSDM2
1
15K 2
1 2 26 NEC_OCI<2> NEC_RIGHT_USB_OVERCURRENT 32 39
FOR BOTH CBUS AND USB2 39 37 24 17 12 9 PCI_AD<10>
K2 DM2 K12 (NEC_USB_DBM)
AD10 5%
+3V_MAIN 1%
39 37 24 17 12 9 PCI_AD<11>
L3
AD11 DP2 J14 (NEC_USB_DBP) 36 402 1/16W
Low/Full/High Speed (External) NEC_USB MF
39 37 24 17 12 9 PCI_AD<12>
K1 AD12 RSDP2 J12 37 NEC_USB_RSDP2 402
NEC_USB NEC_USB
39 37 24 17 12 9 PCI_AD<13>
K3
AD13
39 37 24 17 12 9 PCI_AD<14>
J2
AD14 RSDM3 H11 RSDM3_TP
R791 1 C661 1 C665
NEC_USB 1 2 NEC_USB_DBM 26 37
0.1uF 0.1uF
39 37 24 17 12 9 PCI_AD<15>
J1 DM3 G11 20% 20%
6 1 AD15 10V 10V
R783 39 37 24 17 12 9 PCI_AD<16>
F2
AD16 DP3 G13
1%
36 402 2 CERM 2 CERM
RP52 10K
39 37 24 17 12 9 PCI_AD<17>
E3 RSDP3 G14 RSDP3_TP
NEC_USB 402 402
10K 5% AD17
C 5%
1/16W
1/16W
MF
2 402
39 37 24 17 12 9 PCI_AD<18>
E1
D3
AD18
F12 RSDM4_TP
NEC_USB_DBP 26 37
C
3
SM1 39 37 24 17 12 9 PCI_AD<19>
D1
AD19 RSDM4
F14
R790
39 37 24 17 12 9 PCI_AD<20> AD20 DM4 1 2
39 37 24 17 12 PCI_AD<21>
D2 DP4 E12
NEC_PCI_SERR_L
AD21 1% 402
26
39 37 24 17 12 PCI_AD<22>
C2 RSDP4 E14 RSDP4_TP 36
AD22
26 NEC_PCI_PERR_L C1 NEC_USB
39 37 24 17 12 PCI_AD<23> AD23
B4 E13 RSDM5_TP +3V_MAIN
39 37 24 17 12 9 PCI_AD<24> AD24 RSDM5
9 PCI_AD<25>
A4 DM5 D14
39 37 24 17 12 AD25
39 37 24 17 12 9 PCI_AD<26>
B5 DP5 C13
AD26
(PCI_AD<27>) C4 C14 RSDP5_TP NEC_USB
39 37 24 17 12 9 PCI_AD<27> AD27 RSDP5
39 37 24 17 12 9 PCI_AD<28>
A5
AD28 R794 INTREPID_USB INTREPID_USB 5 NEC_USB 6 NEC_USB NEC_USB
C5 9.09K2
39 37 24 17 12 9 PCI_AD<29> AD29 RREF P11 NEC_RREF 1 NEC_AVSS_F
39 37 24 17 12 9 PCI_AD<30>
B6 1%
26
1
R56 1
R531 RP45 RP45 2R586
AD30 10K 10K 10K
A6
1/16W 10K 10K 5% 5% 5%
39 37 24 17 12 9 PCI_AD<31> AD31 MF 5% 5%
402 1/16W 1/16W 1/16W 1/16W 1/16W
Tie to GND at ball N11 MF MF SM1 SM1 MF
M2 2 402 2 402 4 3 1 402
39 37 24 17 12 PCI_CBE<0> CBE0
NEC_USB
R7841 39 37 24 17 12 PCI_CBE<1>
J3
F1
CBE1 LEFT PORT OCI1 B12
B11
NEC_OCI<1> 26
22 39 37 24 17 12 PCI_CBE<2> CBE2 RIGHT PORT OCI2 NEC_OCI<2> 26

NEC_USB
5% C3 B10 NEC_USB
1/16W 39 37 24 17 12 PCI_CBE<3> CBE3 OCI3 NEC_OCI<3>
1
MF
402 2 OCI4 A10 NEC_OCI<4>
1
R789 R793
J4 B9 1.5K 1.5K
39 37 24 17 12 PCI_PAR PAR OCI5 NEC_OCI<5> 5%
5% 1/16W
39 37 24 17 12 PCI_FRAME_L
F3 1/16W
FRAME MF MF
39 37 24 17 12 PCI_IRDY_L
F4 PPON1 C1239 24 NEC_LEFT_USB_PWREN 2 402 2 402
IRDY OUT
39 37 24 17 12 PCI_TRDY_L
G1 OUT PPON2 A11 32 NEC_RIGHT_USB_PWREN
TRDY 39
39 37 24 17 12 PCI_STOP_L
G3 OUT PPON3 C11 NEC_PPON3_TP
STOP NEED PULL-UP RESISTORS IN CASE USB 1.0 IS USED FOR PORT POWER
NEC_IDSEL B3 OUT PPON4 C10 NEC_PPON4_TP
IDSEL
B NEC_USB
39 37 24 17 12 PCI_DEVSEL_L
12 USB2_PCI_REQ_L
G2
C6
DEVSEL
REQ
OUT PPON5 A9
P6
NEC_PPON5_TP
B
RP55 12 USB2_PCI_GNT_L
D6
GNT
NC1
M6
NEC_NC1_TP
47 H2 NC2 NEC_NC2_TP
26 NEC_PCI_PERR_L PERR
5%
26 NEC_PCI_SERR_L
H1
30 27 23 17 IO_RESET_L
1 8 NEC_IO_RESET_L 26
SERR OD NEC_USB
26 NEC_PCI_INTA_L
C7
2 7 INTA OD
30 14 PMU_PME_L
3 6
NEC_PME_L 26
26 NEC_PCI_INTB_L
B7
INTB OD
R84
30 24 20 18 17 14 MAIN_RESET_L NEC_MAIN_RESET_L 26
1
0 2
39 A7 37 26 NEC_USB_DAM LEFT_USB_DM 24 37 39
4 5 26 NEC_PCI_INTC_L INTC OD
A8 M8 5% INTREPID_USB
1/16W 36 12 CLK33M_USB2 PCLK IPD NTEST1 NTEST1_TP 1/16W
SM1 MF
402
R96
B8 M7 1
0 2
26 NEC_IO_RESET_L VBBRST IPD SMC SMC_TP 26 14 USB_D1M
NEC_CRUN_L N6
CRUN NEC_USB
5%
1/16W
PLACE NEAR J3
NEC_USB 26 NEC_PME_L
D9 PME OD MF
R5511 26 NEC_MAIN_RESET_L
C9
VCCRST IPD TEB N7 TEB_TP
R83 402
Series Rpaks required to 39 0
facilitate NAND-tree testing
4.7K NEC_SMI_L_TP L6
SMI OD IPD AMC P7 NEC_AMC_TP 37 26 NEC_USB_DAP 1 2 LEFT_USB_DP 24 37 39
5%
1/16W
MF
402 2 NEC_USB L8 TEST_TP
5%
1/16W
MF
INTREPID_USB SUTRO CONNECTOR
RP54 IPD TEST 39 402 R78
47
L7
LEGC 1
0 2
26 14 USB_D1P
5%
5%
14 USB2_PCI_INT_L 1 8 NEC_PCI_INTA_L 26 NANDTEST M10 NEC_NANDTESTEN_TP 1/16W
MF
2 7 NEC_PCI_INTB_L SRCLK M9 SRCLK_TP 39 402
AVSS(R)
26
NEC_USB
3 6 NEC_PCI_INTC_L 26 SRDTA N9 NEC_NANDTESTOUT_TP
4 5 NEC_LEGC IPDSRMOD P9 SRMOD_TP 39
R545
VSS 1
0 2
1/16W 37 26 NEC_USB_DBM RIGHT_USB_DM 32 37 39
AVSS
SM1 NEC_USB 5% INTREPID_USB
USB 2.0
P10
N14
H14
B14
N13
B13
M11
L12
H12
D12
J11
F11
N11
P13
M12
1/16W
B1
N1
A2
B2
N2
G4
D8
R286 MF
402
R554
0 0
A 26 NEC_AVSS_F
1
5%
2 26 14 USB_D2M 1
5%
2
PLACE NEAR J12 NOTICE OF PROPRIETARY PROPERTY
A
1/16W NEC_USB 1/16W
MF MF
INTREPID USB CONSTRAINTS 603 R540 402 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
0 2
37 26 NEC_USB_DBP RIGHT_USB_DP 32 37 39
USB_DAM USB_DA 5 MIL SPACING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
USB_DAP USB_DA 5 MIL SPACING
14
14
5%
1/16W
MF
INTREPID_USB BUBBA CONNECTOR II NOT TO REPRODUCE OR COPY IT
USB_DCM USB_DC 5 MIL SPACING 14
402 R530 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
USB_DCP 1
0 2
USB_DC 5 MIL SPACING 14 26 14 USB_D2P
USB_D1M USB_D1 5 MIL SPACING 14 26 5%
1/16W
USB_D1P USB_D1 5 MIL SPACING 14 26 MF
402
APPLE COMPUTER INC.
D 051-6459 A
USB_D2M USB_D2 5 MIL SPACING 14 26
SCALE SHT OF
USB_D2P USB_D2 5 MIL SPACING 14 26
NONE 26 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+3V_MAIN
Ethernet routing priority:
1. Decoupling caps
2. TX SERIES TERMINATION - LOCATE NEAR LINK
3. RX SERIES TERMINATION - LOCATE NEAR PHY
C442 1
10uF LTC3405_SW 38
NO STUFF 20% All differential signals should be close,
6.3V
1 CERM 2
R333 805
4
VIN
parallel, matched lengths, with minimum
0 CRITICAL via count, and short if possible
5%
1/16W U14 L5
MF
402 2
LTC3405
SOT23-6
3.3uH Must maintain 50-ohms trace impedance on all
1 3 1 2 MDI pairs and all RJ45 pairs
3405_MODE
RUN CRITICAL SW +1_0V_MARVELL 38
D 6 MODE VFB 5
1
R334 C471 1
SM1
1
R361
Sandwich each RJ54 pair between chassis grounds D
GND 665K 49.9K
R319 1
2 1% 22pF 1%
1/16W 5% 1/16W
0
5%
MF
50V
CERM 2 MF 1 C486
1/16W 2 402 R2A 402 2 402 10uF
MF R2B 20%
3405_VFB 6.3V
402 2 2 CERM
805
1
VOUT = 0.8V*(1+R2EQV/R1) R362
PLACE ALL SERIES RES CLOSE TO PHY 182K
R370 R2EQV = R2A||R2B 1%
1/16W
MF
CLKENET_LINK_TX 1
0 2 2 402
36 13 36 CLKENET_PHY_TX
R1
5%
1/16W
MF R353 4
TX_CLK CTRL10 51 NC
CLKENET_LINK_RX
402
1
0 2 36 CLKENET_PHY_RX
36 13
5% 2 1
RX_CLK
R344 1/16W
MF 6
0 402 PLACE CLOSE TO
36 13 CLKENET_LINK_GBE_REF 1 2 36 CLKENET_PHY_GBE_REF 22
125CLK
10 1 C492 1 C511 1 C517 1 C502 1 C465 1 C475 +2_5V_MAIN ETHERNET CONNECTOR
5% 15 0.1UF 0.01UF 0.1UF 0.01UF 0.1UF 0.01UF
1/16W 20% 20% 20% 20% 20% 20% NO STUFF
MF DVDD 57 2 10V
CERM
16V
2 CERM 2 10V
CERM 2 16V
CERM
10V
2 CERM 2 16V
CERM
402
37 13 ENET_PHY_TXD<0>
11
TXD0
CRITICAL 62 402 402 402 402 402 402
1
R438
12 U49 67 R465 0
TXD1 PLACE CAPS (IN ORDER) ON PINS 1, 6, 10/15, 57/62, 67/71, 85
1 2
14 71 0
TXD2 88E1111 5% 5%
1/10W
13 ENET_PHY_TXD<3>
16 85 1/16W
37 TXD3 BCC MF FF
805
17 2 603
TXD4
18 5 38 27 +2_5V_MARVELL
TXD5 CHGND1
19 21
TXD6
C 37 13 ENET_PHY_TXD<7>
20
TXD7
VDDO 88
96
1 C464
0.1UF
1 C472
0.01UF
1 C453
0.1UF
1 C503
0.01UF
1 C501
0.1UF
1 C496
10uF
C
20% 20% 20% 20% 20% 20%
9 10V 16V 10V 16V 10V 6.3V
37 13 ENET_PHY_TX_EN TX_EN 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
37 13 ENET_PHY_TX_ER
7
TX_ER 52 402 402 402 402 402 805 1 C488 1 C466 1 C506 1 C520
66 0.1UF 0.1UF 0.1UF 0.1UF
VDDOH PLACE CAPS (IN ORDER) ON PINS 5, 21/26, 48/52, 66/72, 88, 96
20%
10V
20%
10V
20%
10V
20%
10V
36 13 CLKENET_PHY_GTX
8 72 2 CERM 2 CERM 2 CERM 2 CERM
GTX_CLK 402 402 402 402
26
L34
VDDOX 38 +2_5V_MARVELL_AVDD FERR-EMI-600-OHM PLACE CAPS AT TRANSFORMER PINS 1, 4, 7 & 10 CRITICAL
95 48
RXD0 2 1
92
RXD1 SM
J17
93 32 RJ45
37 13 ENET_LINK_RXD<2> RXD2
91 35
1 C497 1 C504 1 C487 1 C476 1 C754 12 39 37 13 RJ45_DP<0>
11 RT-TH
RXD3 0.1UF 0.01UF 0.1UF 0.01UF 10uF 9
90 36 20% 20% 20% 20% 20%
RXD4 AVDD 10V
2 CERM
16V
2 CERM
10V
2 CERM
16V
2 CERM
6.3V
2 CERM
89 40 10 15 RJ45_C0_PD
RXD5 402 402 402 402 805
13 ENET_LINK_RXD<6>
87 45 1
38 27 +2_5V_MARVELL
37 RXD6
86 78 PLACE CAPS (IN ORDER) ON PINS 32/35, 36/40, 45 & 78 11 39 37 14 RJ45_DN<0> 2
RXD7
9 39 37 16 RJ45_DP<1> 3
37 13 ENET_RX_DV
94 29 MDI_P<0> 4
RX_DV MDI0+ 37
37 13 ENET_RX_ER
3 31 MDI_M<0> 7 18 RJ45_C1_PD 5
RX_ER MDI0- 37
33 MDI_P<1> 6
MDI1+ 37
R371 1 R3451 R3541 37 13 ENET_CRS

84
CRS MDI1- 34 37 MDI_M<1> 8 39 37 17 RJ45_DN<1> 7
10K 10K 1.5K 83 39 6 39 37 19 8
5% 5% 37 13 ENET_COL COL MDI2+ 37 MDI_P<2> RJ45_DP<2>
5% 1/16W 1/16W
1/16W 41 MDI_M<2>
MF MF
402 2
MF
402 2
MDI2- 37
402 2 37 13 ENET_MDC
25 42 MDI_P<3> 4 21 RJ45_C2_PD
MDC MDI3+ 37
10
24 43
R343 37 13 ENET_MDIO
MDIO MDI3- 37 MDI_M<3>
5
12
1K 39 37 20 RJ45_DN<2>
14 INT_ENET_RST_L 1 2
B 5%
1/16W
D1 14 ENET_ENERGY_DET 23 INT-/
LED_LINK10
LED_LINK100
76
74
LED_LINK10
LED_LINK100
R346
49.9
1
R372
49.9
1
R404
49.9
1
R413
49.9
1 3 39 37 22 RJ45_DP<3>
CHGND1
Short shielded RJ-45
B
MF INT+ 73 NC 1% 1% 1% 1% 1 24
402 1N914 LED_LINK1000 1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
RJ45_C3_PD
30 26 23 17 IO_RESET_L
3 1 ENET_RST_L 28 70 NC
RESET LED_DUPLEX 402 2 402 2 402 2 402 2
69 LED_RX_SPN 2 39 37 23 RJ45_DN<3>
SOT23
LED_RX SM
27 68 NC 1 1 1 1
ENET_COMA
COMA LED_TX R355 R381 R406 R428 XFR-ENET-1000BT
49.9 49.9 49.9 49.9 T1
1% 1% 1% 1%
6 C755 1
CONFIG0 65 (000) 1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF CRITICAL
2.2uF 82 64 1 1 1 1
D
Q15 20%
10V
NC S_IN+ CONFIG1 (000) 2 402 2 402 2 402 2 402 R735 R733 R382 R347
2N7002DW CERM 2 NC 81
S_IN- CONFIG2 63 (111) 75 75 75 75
AC_IN 2 G S
SOT-363 3 805 61 SEE CONFIG TABLES MDI0_PD MDI1_PD MDI2_PD MDI3_PD 5% 5% 5% 5%
31 30 29 CONFIG3 (110)
(BELOW)
1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
77 60
1
D
Q15 NC S_OUT+ CONFIG4 (111) 1 C454 1 C477 1 C493 1 C505 2 402 2 402 2 402 2 402
2N7002DW NC 75
S_OUT- CONFIG5 59 (101) 0.01UF 0.01UF 0.01UF 0.01UF
SOT-363 ENET_CTAP_CHGND 38
SLEEP_L_LS5 5 G S 58 20% 20% 20% 20%
35 34 33 19 CONFIG6 (000) 16V
2 CERM
16V
2 CERM
16V
2 CERM
16V
2 CERM
NC 79
4 S_CLK+ 402 402 402 402 1 C457
NC 80 44 JTAG_ENET_TDI
S_CLK- TDI 13
100pF
50 JTAG_ASIC_TDO_TP PLACE RESISTORS CLOSE TO PHY 10%
TDO 39 3KV
2 CERM
PLACES PHY IN "COMA" MODE WHEN ENET_HSDACP 37 49 JTAG_ASIC_TCK
HSDAC+ TCK 13 39 1808
ASLEEP ON BATTERY (SAVES POWER) ENET_HSDACM 38 46 JTAG_ASIC_TMS
HSDAC- TMS 13 39
47 JTAG_ASIC_TRST_L CHGND1
TRST 13 39
36 CLK25M_ENET_XIN
36 CLK25M_ENET_XOUT
55
54
XTAL1
XTAL2
RSET 30 ENET_RSET
MARVELL 88E1111
NO STUFF 56 NC
SEL_OSC CONFIG DEFINITIONS
R435 ENET_VSSC 53
VSSC SEL_2.5V 13
20K
1 2
GND PIN BIT[2:0] CONFIG INPUTS
10/100/1000 ETHERNET
A PUT CRYSTAL CIRCUIT CLOSE TO PHY 5%
1/16W
1
NO STUFF NO STUFF 97 VDDO 111 PIN BIT[2] BIT[1] BIT[0] A
MF
402 R427 R3931 R4031 1
R335 1
R380
LED_LINK10 110 CONFIG<0> PHYADR[2] PHYADR[1] PHYADR[0] NOTICE OF PROPRIETARY PROPERTY
0 LED_LINK100 101 CONFIG<1> ENA_PAUSE PHYADR[4] PHYADR[3]
5% 49.9 49.9 10K 4.99K THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
CRITICAL 1/16W 1% 1% 5% 1% LED_LINK1000 100 CONFIG<2> ANEG[3] ANEG[2] ANEG[1] PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
MF 1/16W 1/16W 1/16W 1/16W AGREES TO THE FOLLOWING
Y3 2 402 MF
402 2
MF
402 2
MF MF LED_DUPLEX 011 CONFIG<3> ANEG[0] ENA_XC DIS_125
25.0000M 2 402 2 402 LED_RX 010
1 2 CLK25M_XTAL_IN CONFIG<4> MODE[2] MODE[1] MODE[0] II NOT TO REPRODUCE OR COPY IT
LED_TX 001 CONFIG<5> DIS_FC DIS_SLEEP MODE[3]
8X4.5MM-SM TABLE_ALT_HEAD III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: VSS 000 CONFIG<6> SEL_BDT INT_POL 75/50 OHM
C555 1 C491 1 PART NUMBER SIZE DRAWING NUMBER REV.
33pF 33pF
051-6459 A
TABLE_ALT_ITEM
5%
50V
CERM 2
5%
50V
CERM 2
197S0703 197S0037 ALTERNATE Y3
TABLE_ALT_ITEM
APPLE COMPUTER INC.

D
402 402 197S0603 197S0037 ALTERNATE Y3 ALT FOR SIWARD SCALE SHT OF
Y3’S LOAD CAPACITANCE IS 20PF NONE 27 44

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LM2594_IN
38
165MA MAX LOAD
D14
SC-59 CRITICAL
38 29 28 +3V_FW
+1_95V_FW_DVDD 28 38
CRITICAL
38 29 28 +FW_PWR_OR
1 U34 L51 1
LM2594
+5V_SLEEP 3 7 SM 4 220uH
VIN FB 1
R447
2 VOUT
8 1 2 L7 1 C577 1 C778 1 C546
SM-3 400-OHM-EMI 10 0.1UF 0.1UF 2.2UF
SM-1 5% 20%
GND ON/OFF 1/16W 20%
10V
20%
10V 2 10V
MF 2 CERM 2 CERM CERM
SDM20E40C +3V_FW_UF 38 805
6 5 2 402 402 402
2
C635 1 2 C818 1 38 +1_95V_FW_DVDD_PORT1 PHY PINS 72,76
10UF D20 100UF

N20P20% 20%
50V SM 10V 2 1 C777 1 C541 +1_95V_FW_PLLVDD 28 38
D CERM 2
2320
1
MBR0540 POLY
SMD-3 2.2UF
20% 20%
0.1UF
1 1
D
2 10V
CERM 2 10V
CERM R759 R556
805 402 3.3 3.3
5% 5%
1/16W 1/16W
MF MF
PHY PIN 64 603 2 2 603
R470
1
1 2 38 +3V_FW_AVDD_PORT2 +1_95V_FW_PLL500VDD
CRITICAL 38
U36 VOUT = 1.22*(1+R2/R1)+ IADJ*R2

5%
1/16W C570 +1_95V_FW_PLL400VDD 38
1UF
PHY PIN 61
LTC1761ES5-BYP MF
IADJ = 30NA AT 25C 603
SOT-23-1 1 2
SYM_VER2
1 OUT 5
IN +1_95V_FW_PLLVDD 28 38
20%
10V
2 C810 1 C628
CERM 1UF 1UF
FWPLL_BYP 3 BYP ADJ 4 R494 603 20%
1 10V
20%
1 1 CERM 2 10V
GND R574 1 2 38 +3V_FW_AVDD_PORT1 603 CERM
603
C641 1 16.2K 5% C591 +1_95V_FW_DVDD 28 38
R485
FW_PLL_ADJ
2.2UF 1 C650 2 1% 1 C645 1/16W

1UF 22
PHY PIN 50
1/16W MF
20% 0.01UF MF 10UF 37 28 FW_PHY_CNTL<0> 1 2 FW_LINK_CNTL<0> 13 37
10V
CERM 2 20% 2 402 20%
6.3V
603 1 2 PHY PIN 25 PHY PIN 28 R547 5%
805 2 16V 2 CERM
1
1 2 1/16W
CERM
402 R2 805 20%
10V
38 +1_95V_FW_DVDD_RX0
R484 MF
402
R557 CERM 5%
1/16W FW_PHY_CNTL<1> 1
22 2 FW_LINK_CNTL<1> 13
603 37 28 37
R575 1
1 2 38 +3V_FW_AVDD_PORT0
MF
603 5%
1
27.4K2 1/16W
5%
1/16W C629 R564 MF
402 R469
PHY PIN 40
1% MF 1UF 1
1 2 1
22 2
1/16W 603 38 +1_95V_FW_DVDD_TX0 36 28 CLKFW_PHY_PCLK CLKFW_LINK_PCLK 13 36
MF 1 2
402 R1 1 C808 5%
1/16W
5%
1/16W
20%
10V 20%
0.1UF 1 C634 MF
603
MF
402
R555 CERM 10V 0.1UF
603 2 CERM 20%
+1_95V_FW_DVDD 1 402 10V
2 CERM
C CRITICAL
28 38 1
5%
2 38 +3V_FW_AVDD
C627 402 C
U37 1 C646 1
R577 1/16W
1UF
PHY PIN 21
MF PHY PIN 38
8
LT1962-ADJ
MSOP
0.01UF
20%
16V
16.2K
1%
603 1 2 DSX STRAP OPTIONS
IN OUT 1 2 CERM 1/16W
402 MF 1 C653
20%
10V 1 C586 1 C540 1 C804 1 C561 1 C539 0 -> BILINGUAL PORT
7 2 402 CERM 10UF 0.1UF 0.1UF 0.1UF 0.1UF
NC NC R2 10UF 603 20% 20% 20%
20% 20%
C642 1
6
ADJ 2 FW_CORE_ADJ 20%
6.3V 2 6.3V 2 10V 2 10V 10V
2 CERM 2 10V
CERM 1 -> A-ONLY PORT
2.2UF
NC NC 2 CERM
1
CERM
805
CERM
402
CERM
402 402 402
20% 1
805 R436
10V
CERM 2
BYP 3 FW_CORE_BYP R576 5%
1K PHY PINS 4,14
805 5 SHDN GND 4 27.4K 1/16W
1% 1 1
1/16W
MF
MF
2 402
R446 R775 PLACE NEAR PHY
0 1K
RX0
2 402 5% 5% SPEC SAID TO USE 10K
31 TX0
R1 1/16W 1/16W 2
MF MF R459
R4371 2 402 2 402 10K
24
39
44
51
57
63
37
65
71
18
69
70
29
30
R4441
6
VOUT = 1.22*(1+R2/R1)+ IADJ*R2 5%
1K 1K 1/16W
IADJ = 30NA AT 25C 5% 5%
1/16W AVDD DVDD DVDD PLL PLL MF 1 C571 C605 1
1/16W FW_PORT1_SEL 1 402 1UF 1UF R5161 1
R509
MF MF
402 2 33 DS0
3.3 1.8 3.3 VDD
1.8
VDD
3.3
R4861 1
R478 20%
10V
20%
10V 56.2 56.2
402 2
CRITICAL 56.2 56.2 2 CERM CERM 2 1% 1%
32 5 1% 1%
DS1 PCLK CLKFW_PHY_PCLK 28 36
1/16W 1/16W
603 603 1/16W 1/16W
36 13 CLKFW_PHY_LCLK 7
LCLK U29 1 FW_PINT 13 37
MF
402 2
MF
2 402
MF
402 2
MF
2 402
PINT
80
TSB81BA3A
13 FW_PHY_LPS
LPS PQFP 79 NC FW_TPA0P (TXD-FWB)
CNA 29 37
(SYM_VER1)
FW_PHY_LREQ 3 FW_TPA0N (TXD-FWB)
37 13
LREQ 9 FW_PHY_CNTL<0> 28 29 37
PWR CLASS = 100 SN0201029PFP CTL0
10 FW_PHY_CNTL<1> 28
37
FW_TPA1P (TXD-FWA)
38 29 28 +FW_PWR_OR FW_PC_PU 66 CTL1 37
29 37
(MAY PROVIDE POWER, OR PC0
MAY REQUIRE UP TO 3W) FW_PC_PD 67 FW_TPA1N (TXD-FWA)
PC1 1MA(MAX) BUS HOLDER EACH 2 FW_LKON 13
29 37
C/LKON
B R7811
402K
(PC0 IS MSB, PC2 IS LSB) 68
PC2
46
B
FW_TPA0P
1% 14 FW_PHY_PD 77 (TXD-FWB) TPA0+
1/16W PD 45 FW_TPA0N FW_TPB0P (RXD-FWB) 29
MF
402 2
(TXD-FWB) TPA0- 37
FW_TPB0N (RXD-FWB) 29
FW_BMODE 74 53 FW_TPA1P 37
BMODE (TXD-FWA) TPA1+ FW_TPB1P
52 FW_TPA1N (RXD-FWA) 29 37
(TXD-FWA) TPA1-
FW_CPS 34 FW_TPB1N (RXD-FWA) 29
CPS 59 NC 37
TPA2+
37 13 FW_LINK_DATA<0>
1 8 37 FW_PHY_DATA<0> 11 58 NC
2 RP38
22 7 37 FW_PHY_DATA<1> 12
D0 TPA2-
5% D1 42 FW_TPB0P
R5101 1
R495
3 1/16W 6 37 FW_PHY_DATA<2> 13 (RXD-FWB) TPB0+
SM1 D2 41 FW_TPB0N 56.2 56.2
4 5 37 FW_PHY_DATA<3> 15 (RXD-FWB) TPB0- 1% 1%
1 8
D3 1/16W 1/16W
37 13 FW_LINK_DATA<4> 37 FW_PHY_DATA<4> 16 49 FW_TPB1P MF MF
2
RP37
22 7 37 FW_PHY_DATA<5> 17
D4 (RXD-FWA) TPB1+
48 FW_TPB1N
402 2 2 402 1 1
3 5% 6 37 FW_PHY_DATA<6> 19
D5 (RXD-FWA) TPB1- R524 R522
1/16W
SM1 D6 56 FW_TPB2_PD FWB_TPB1 56.2 56.2
4 5 37 FW_PHY_DATA<7> 20 TPB2+ 1% 1%
D7 55 1/16W 1/16W
TPB2- 1 MF MF
75 47
R496 2 402 2 402
FW_PHY_RESET_L
RESETZ TPBIAS0 FW_BIAS0
C587 1%
4.99K
TPBIAS1
54 FW_BIAS1 220PF 1/16W
35 60 NC 5% MF FWB_TPB0
FW_INPUT_PD 25V
SE TPBIAS2 R758 CERM 2 402
402
1
47 C614 1
R464 36
SM XI
27 36 FW_XI 1 2
220PF R525
1K XO
26 NC 5%
1/16W +3V_FW
4.99K
5% 28 29 38 5% 1%
1/16W FW_TESTM 78 MF 25V 1/16W
MF TESTM 402 CERM MF
23 FW_R0 402
2 402 R0 2 402
A R4451
FW_VREG_PD 73 VREG_PD
THRML
R1
22 FW_R1
1 C640
FIREWIRE
C538 1
0.22UF 1K R740 1
1
PAD
AGND DGND PLLGND R563
6.34K1
1
R760
100
0.22UF
20%
NO STUFF
A
R546 2
81
21
40
43
50
61
62
4
14
38
64
72
76
25
28
20% 5%
6.3V
CERM 2
1/16W
MF
470
5% 1K
R4711 1%
5%
1/16W
6.3V
2 CERM
4
R7611
402 402 2 1/16W 5% 1K 1/16W MF 402 100K THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
MF
402 2 1/16W
MF
5%
1/16W
MF
402
2 402 VCC
5%
1/16W PLACE NEAR PHY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
MF MF
2 402 402 2 402 2 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
G1 II NOT TO REPRODUCE OR COPY IT
98.304M
CAPACITOR IN CONJUCTION WITH OSC III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
INTERNAL PULLUP PROVIDES 36 FW_OSC 3 SM-A
OE 1 FW_OSC_EN
RESET PULSE WHEN PHY FIRST OUT
RECEIVES POWER CRITICAL SIZE DRAWING NUMBER REV.
GND
D 051-6459 A
28 44
SCALE SHT OF
NONE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PORT POWER SWITCH 38 28 +3V_FW
R751
L39
400-OHM-EMI
+PBUS
1
10K 2 38 +3V_FW_ESD_ILIM 1 2 +3V_FW_ESD 29 38
CRITICAL
5% SM-1
Q67 1/16W
MF
NDS9407 402 1 C784 3 D26 D28
F2 SOI
CRITICAL
0.1UF
1 C786 SOT23 BAV99DW BAV99DW
1.5A-24V D29 20% 0.001UF 1N5227B SOT-363 SOT-363
8 20%
2 1 38 +FW_FUSE 3
7 1
SMB
2
10V
2 CERM 50V
2 CERM 1 D8 5 5
38 +FW_SW 38 28 +FW_PWR_OR 402
2 402
6 3 3
SM
D 1
R752
1
5 B340B
4 4 D
470K
1 C781
0.01UF 1 C792
5%
1/16W 20% 4 C774 1
0.01UF
MF
16V
2 CERM 0.01UF D26 D28 20%
2 402 402 20%
16V BAV99DW BAV99DW 2 16V
+3V_PMU CERM
CERM 2 SOT-363 SOT-363 402
FW_PWR_GATE 402
2 2
F5
R736
100K
1
1
R743
1.5AMP-33V
2 1
1
6 6
1
PORT 0
5% 330K
1/16W
MF
402 2 DP5
5%
1/16W
MF
SM 514S0059
BAS16TW 2 402 1
SOT-363
1 6
FIREWIRE B - BILINGUAL
POWER_UP
FW_PWREN_L L40
FERR-250-OHM
6 SM
D Q25 3 38 +FW_PWR_PORTA
2 3 15
2N7002DW 2 13
33 30 PMU_POWER_UP_L 2 G S
SOT-363 D Q58 11
2N7002DW 1 1 4
SOT-363 FW_TPA0P_CONN 4
RUN_OR_AC 5 G S 37 28 FW_TPA0P
1 SYM_VER-1 TPA
SM AREF 39 38 FW_TPO0R 5
4
FERR-250-OHM
L50 37 28 FW_TPA0N
90-OHM-200MA
L71 FW_TPA0N_CONN 3 TPA(R) OUTPUT
DP5 SM CRITICAL 38 FW_VGND0 6 TPA*
BAS16TW NC 7 VG
SOT-363
8 SC
4 3 38 +FW_VP0
39 34 33 32 19 DCDC_EN 2
2 VP
37 28 FW_TPB0P FW_TPB0P_CONN
BREF 9 TPB
(TPI0R)
C DP5 2 3
1 TPB(R) INPUT C
BAS16TW 37 28 FW_TPB0N FW_TPB0N_CONN
R741 SOT-363 10 TPB*
2
10K 1 2 5
31 30 27 AC_IN AC_IN_FW_CNTL 1 4 12
5% SYM_VER-1 14
1/16W SM
MF 90-OHM-200MA NO STUFF
1
402 R737 L70
CRITICAL C607 1 1 C803
F-RT-SM
1394B-Q41
470K
5% 0.01UF 0.01UF J26
1/16W 20% 20%
MF NO STUFF 16V 16V CRITICAL
2 402 CERM 2 2 CERM
1 402 402
R472 1 C556 1 C528 CHGND1
1M 0.1UF 0.01UF
5% 20% 20%
1/16W 50V
2 CERM 2 16V
MF CERM
805 402
CLEAR OUT ALL PLANES UNDER TRANSFORMERS 2 402
CHGND6
+3V_FW_ESD 2
29 38
CHGND1 R453
0
5%
ENABLES PORT POWER WHEN MACHINE IS D12 D15
1/10W
FF
805
1
BAV99DW BAV99DW AREF NEEDS TO BE ISOLATED FROM
RUNNING OR WHEN ASLEEP ON AC 5
SOT-363 SOT-363
5 ALL LOCAL GROUNDS PER 1394B SPEC
3 3 SO WHEN A BILINGUAL DEVICE
IS PLUGGED TO BETA-ONLY DEVICE,
STATE PMU_POWER_UP_L POWER_UP DCDC_EN AC_IN LTC4210_ON 4 4 THERE’S NO DC PATH BETWEEN
SHUTDOWN C588 1 THEM (TO AVOID GROUND OFFSET ISSUE)
(AC) 1 0 0 1 OFF 0.01UF
20%
1 C606
0.01UF
16V
CERM 2
D12 D15 20% BREF SHOULD BE HARD CONNECTED TO
SLEEP 1 0 1 1 BAV99DW BAV99DW 16V
B (AC) ON 402
2
SOT-363 SOT-363
2
2 CERM
402 LOGIC GROUND FOR SPEED SIGNALING B
RUN 0 1 1 1 AND CONNECTION DETECTION CURRENTS
(AC) ON 6 6
PER 1394B V1.33
SHUTDOWN 1 1 1
(BATT) 0 0 0 OFF
SLEEP 1 0 1 0 OFF
(BATT) (PULL-DOWN RESISTOR) CLEAR OUT ALL PLANES UNDER TRANSFORMERS
FIREWIRE A
RUN 0 1 1 0 ON CRITICAL
(BATT) L43
260-OHM-330MA
SM1
PORT 1
2.99V +3V_PMU +4_6V_BU +3V_PMU FW_TPA1P 3 SYM_VER-2 4
37 28
514-0057
37 28 FW_TPA1N 2 1 CRITICAL
CRITICAL
J23
1394A
L44 F-RT-TH
260-OHM-330MA
SM1 39 37 FW_TPO1P 6
37 28 FW_TPB1N 3 SYM_VER-2 4 TPO
39 37 FW_TPO1N 5
TPO#
37 28 FW_TPB1P
2 1 39 37 FW_TPI1P 4
TPI
39 37 FW_TPI1N 3
TPI#
A 38 FW_VGND1
38 +FW_VP1 1
2
VP
FIREWIRE PORTS
VGND
A
1 C807 1 C805 7 8 9 10
1 0.01UF
R779 20%
16V
0.01UF
20%
0 2 CERM 16V
2 CERM AGREES TO THE FOLLOWING
5% 402
1/10W 402 CHGND6 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
FF
2 805 II NOT TO REPRODUCE OR COPY IT
CHGND6 SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.

D 051-6459 A
SCALE SHT OF
NONE 29 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+3V_PMU +3V_PMU
R505 R535
10K
1
470K 2 30 PMU_EPM 2 1
CHARGE_LED_L 30 31 39
5%
+3V_PMU
R504
5%
1/16W
R778
1/16W
MF R569
MF +3V_PMU_AVCC 25 30 38 402 10K
1
10K 2
402
1
4.7 2
30 25 PMU_RESET_BUTTON_L 2 1
PMU_POWER_UP_L 29 30 33
5%
5% 5% TABLE_5_HEAD
1/16W
1/16W
MF R492 C643 1 C574 1 C835 1 1/16W
MF C827 1 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
R585 MF
402
402
1
10K 2 SOFT_PWR_ON_L 10UF 0.1UF 0.1UF 402
0.1UF
TABLE_5_ITEM
100K 1
22 23 30 34
20% 20% 20% 20% 341S1008 1 IC,PMU,V81B U33 30 PMU_POWERUP_OK 2
5% 6.3V 2 10V 10V 10V
1/16W CERM CERM 2 CERM 2 CERM 2 5%
MF 805 402 402 402 1/16W
D
402
CPU_VCORE_HI_OC/PMU_AP should
MF
402 D
R536 14 60 97 have a pulldown for coming out of
reset. MLB will have a pull-up
100K 2 to +3V_MAIN or +3V_SLEEP, which
1 MAIN_RESET_L 14 17 18 20 24 26 30 39 VCC AVCC will act as our pulldown since R788
5%
both are off during PMU reset.
PMU_BATT1_DET_L_PU 2
470K 1
1/16W CRITICAL 30
RP40 MF
OMIT 44
(PMU_AP)
5%
100K 402
39 23 KBD_Y<0> 86 CPU_VCORE_HI_OC 7 34 1/16W
4 5 P00_D0 P50_WRL_WR
IO_RESET_L 17 23 26 27 30
39 23 KBD_Y<1> 85
P01_D1 U33 P51_WRH_BHE
43
INT_RESET_L 9 13 30
MF
402 R592
5% 42 470K 1
1/16W
SM1
RP40 39 23 KBD_Y<2> 84
P02_D2 M16C62 P52_RD 41
MAIN_RESET_L 14 17 18 20 24 26 30 39 39 31 30 PMU_BATT_DET_L 2
100K 39 23 KBD_Y<3> 83 FLAS NC 5%
3 6 SLEEP P03_D3 P53_BCLK 1/16W
23 25 30 33 35 39
39 23 KBD_Y<4> 82
P04_D4 P54_HLDA
40
PMU_INT_NMI 14 RP41 MF
5% 39 10K 402
RP40 1/16W
SM1 R518 39 23 KBD_Y<5> 81
P05_D5 P55_HOLD 38
PMU_EPM 30
30 25 PMU_NMI_BUTTON_L 2 7
100K 2.2K 2 39 23 KBD_Y<6> 80 INT_PU_RESET_L 13 25 30
1 8 INT_RESET_L 9 13 30 23 NUMLOCK_LED_L 1 P06_D6 P56_ALE 37
5%
5% 5%
39 23 KBD_Y<7> 79
P07_D7 P57_RDY_CLKOUT PMU_CPU_HRESET_L 23
1/16W
SM1 RP41
1/16W RP40 1/16W 36 1
10K 8
SM1 MF PMU_NUMLOCK_LED_L 78 PMU_ACK_L PMU_NMI_L
100K 402 P10_D8 P60_CTS0_RTS0 35
14 30
2 7 INT_SUSPEND_REQ_L 8 30 PMU_CAPSLOCK_LED_L 77 PMU_CLK 14 5%
R513 P11_D9 P61_CLK0 34 1/16W
76 PMU_FROM_INT
R782
5%
1/16W 2.2K 2
31 30
39
CHARGE_LED_L
P12_D10 P62_RXD0 33
14
R768 SM1
SM1 23 CAPSLOCK_LED_L 1 30 29 PMU_POWER_UP_L 75
P13_D11 P63_TXD0 PMU_TO_INT 14 7.15K1
1K 33 32 31 30 PMU_SMB_DATA 2
2 1 PMU_BYTE 30 5% NC 74 PMU_REQ_L 14
1/16W P14_D12 P64_CTS1_RTS1_CTS0_CLKS1 31 1%
5% MF 34 30 23 22 SOFT_PWR_ON_L 73 PMU_LID_CLOSED_L 23 30 1/16W
1/16W
R787 402 P15_D13_INT3 P65_CLK1 30 MF
R769
MF 39 25 14 COMM_RING_DET_L 72 PMU_RESET_BUTTON_L 25 30 402
402 10K P16_D14_INT4 P66_RXD1 29 7.15K1
2 1 PMU_CNVSS 30 14 INT_WATCHDOG_L 71 PMU_NMI_BUTTON_L 25 30 31 30 PMU_SMB_CLK 2
P17_D15_INT5 P67_TXD1
5% 28 1%
1/16W 39 23 KBD_X<0> 70 TPAD_RXD 23 30 1/16W
MF P20_A0_D0 P70_TXD2_SDA_TA0OUT 27 MF +3V_SLEEP
402 39 23 KBD_X<1> 69 TPAD_TXD 23 30 402
P21_A1_D1_D0 P71_RXD2_SCL_TA0IN_TB5IN 26
KBD_X<2> 68 SYSTEM_CLK_EN
39 23
67
P22_A2_D2_D1 P72_CLK2_TA1OUT_V 25
CPU_CLK_EN
14
RP41
39 23 KBD_X<3>
P23_A3_D3_D2 P73_CTS2_RTS2_TA1IN_V 8 10K
C 39 23
39 23
KBD_X<4>
KBD_X<5>
66
65
P24_A4_D4_D3 P74_TA2OUT_W
24
23
PMU_CHARGE_V
PMU_CHRG_BATT_0
31
31
30 PMU_I2C_DATA 4
5%
5
C
P25_A5_D5_D4 P75_TA2IN_W 22
1/16W
KBD_X<6> 64 NC SM1
39 23
63
P26_A6_D6_D5 P76_TA3OUT 21
(CHARGE_I)
RP41
39 23 KBD_X<7>
P27_A7_D7_D6 P77_TA3IN NC 10K
30 PMU_I2C_CLK 3 6
61 20
UNDERVOLTAGE RESET CIRCUIT 39 23
39 23
KBD_X<8>
KBD_X<9> 59
P30_A8_D7
P31_A9
P80_TA4OUT_U
P81_TA4IN_U
19
PMU_SLEEP_LED_L
CPU_SMI_L
23
5
5%
1/16W
SM1
+3V_PMU 58 18
30 27 26 23 17 IO_RESET_L POWER_VALID 30
P32_A10 P82_INT0 17 +5V_SLEEP
57
39 23 KBD_COMMAND_L
P33_A11 P83_INT1 16
PMU_PME_L 14 26 30
R573
39 30 23 KBD_CONTROL_L 56
P34_A12 P84_INT2 INT_PEND_PROC_INT 14
TPAD_RXD 2
10K 1
1 15 30 23
R765 39 30 23 KBD_SHIFT_L 55
P35_A13 P85_NMI 9
PMU_NMI_L 30 Keep crystal subcircuit close to PMU.
5%
1K 39 30 23 KBD_OPTION_L 54
P36_A14 P86_XCOUT CLK32K_PMU_XOUT 1/16W
MF R584
5% 8
1/16W 39 23 KBD_FUNCTION_L 53
P37_A15 P87_XCIN CLK32K_PMU_XIN 402
2
10K 1
MF 30 23 TPAD_TXD
2 402 14 PMU_INT_L 52
P40_A16 P90_TB0IN_CLK3
5
PMU_BATT0_DET_L R593 NO STUFF
5%
34 +3V_PMU_RESET KBD_ID 51 4
PMU_BATT1_DET_L_PU 1
1K 2 PMU_BATT_DET_L R786 1/16W
MF
39 23 30 30 31 39
P41_A17 P91_TB1IN_SIN3 3 10M 402
7 CPU_PLL_STOP_OC 50 NC 5% 1 2
P42_A18 P92_TB2IN_SOUT3 2 1/16W
C812 1 NC 49
P43_A19 P93_DA0_TB3IN NC MF 5% +3V_MAIN
0.1UF 39 35 33 30 25 23 SLEEP 48
P44_CS0 P94_DA1_TB4IN
1
INT_PROC_SLEEP_REQ_L 14
402 1/16W
MF 1
R785 R597
20%
10V
CRITICAL 100 402 100K 1
CERM 2
4 47
P45_CS1 P95_ANEX0_CLK4 PMU_POWERUP_OK 30 0 30 POWER_VALID 2
402 VCC 8 INT_SUSPEND_ACK_L 46
P46_CS2 P96_ANEX1_SOUT4
99
NC R572 5%
1/16W 5%
U51 INT_SUSPEND_REQ_L 45 98
PMU_OOPS 1
1K 2 AC_IN
CRITICAL MF 1/16W
MF R596
30 8
P47_CS3 P97_ADTRG_SIN4 30 27 29 31
2 402 10K
MAX6804 95 5% Y7 30 26 14 PMU_PME_L
402
2 1
SOT143 THERM_L_OC 1/16W CLK32K_PMU_XOUT_UF
25 SM-1
39 30 PMU_KB_RESET_L 3 MR* RSET* 2 P100_AN0 93 MF 5%
P101_AN1 92
PMU_AC_IN 402 1 4 R562 1/16W
MF
GND 30 PMU_BYTE 6
BYTE P102_AN2 PMU_AC_DET 30
2
100K 1 402
91 30 23 PMU_LID_CLOSED_L
CLK10M_PMU_XOUT 11 NC 32.768K
1 XOUT P103_AN3 90 5%
CLK10M_PMU_XIN 13
XIN P104_AN4_KI0 PMU_I2C_CLK 30
1 C832 1 C831 1/16W
B NO STUFF PMU_RESET_L 10
96
RESET P105_AN5_KI1
89
88
PMU_I2C_DATA 30
5%
12PF
50V
5%
12PF
50V
MF
402 B
R595 38 30 25 +3V_PMU_AVCC
VREF P106_AN6_KI2 87
PMU_SMB_CLK 30 31 2 CERM
402
2 CERM
402
1
10M 2
30 PMU_CNVSS 7 CNVSS P107_AN7_KI3 PMU_SMB_DATA 30 31
5% VSS AVSS
1/16W
1
R594 MF
402
0 12 62 94 Y7’S LOAD CAPACITANCE IS 12.5PF
5%
1/16W R583
MF Keep crystal subcircuit close to PMU. 1
10K 2
402 2 CRITICAL +3V_PMU 30 PMU_OOPS
Y6 Y6’S LOAD CAPACITANCE IS 12PF 5%
CLK10M_PMU_XOUT_UF
10.0000M
1 2 TABLE_ALT_HEAD
38 32 +4_85V_RAW A29 DETECT CIRCUIT 1/16W
MF
402
R544
100K 2
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: 30 25 13 INT_PU_RESET_L 1
PART NUMBER 1
8X4.5MM-SM R501 5%
1/16W
100K
TABLE_ALT_ITEM
C666 1 C664 1 197S0704 197S0041 Y6 ALT CRYSTAL SIZE 1%

MF
402
PMU KEYBOARD RESET CIRCUIT 12PF
5%
12PF
5% 197S0604 197S0041 Y6 ALT FOR SIWARD
TABLE_ALT_ITEM 1/16W
MF
1 C558 R5171
50V 50V
2 402 1 0.1UF 100K
CERM 2
402
CERM 2
402
R491 20% 5%
ADAPTER_DET 31 52.3K 2 10V
CERM
1/16W
MF
+3V_PMU 39
1% 402 402 2
1/16W
1 MF
R502 2 402 A29_DETECT 31
100K
34 30 23 22 SOFT_PWR_ON_L13
14
74LVC32
TSSOP
Q11 ADAPTER DETECTION SCHEME 1%
1/16W
MF 3
11 PMU_KB_RESET_IN1 2 402 U27
U24 +3V_PMU
ID VOLT PMU_AC_DET 4
2
LMC7211
D
Q22
39 30 23 KBD_CONTROL_L12 32 CASE ADAPTER PIN VOLT RANGE
SYSTEM STATUS 30
SM
2N7002
SM
A
7
14
74LVC32
1 Q11 (65W)
2.007V-
2.066V
1.65V-
2.31V
RECOGNIZES AS Q11
FULL FUNCTIONS
1
R503
402K
1%
2_34V_REF 3
CRITICAL
1 A29_DET_L 1 G S
2
PMU
4 TSSOP
6 PMU_KB_RESET_L 30 2.558V- 2.31V- RECOGNIZES AS A29
1/16W
MF 5
A
+3V_PMU U24 39
2 A29 (45W) 2 402
5 32 2.661V 2.97V LIMITED FUNCTIONS R476 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
4.7M 2 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
7
14 0.589V- 0.33V- FULL FUNCTIONS AGREES TO THE FOLLOWING
KBD_SHIFT_L 10
74LVC32 3 AIRLINE 0.663V 0.99V NO BATTERY CHARGING
5%
1/16W
MF
TSSOP 1
39 30 23
8 R475 402 II NOT TO REPRODUCE OR COPY IT
U24 PMU_KB_RESET_IN2
3.19V- 2.97V- RECOGNIZES AS HOOPER 127K III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
39 30 23 KBD_OPTION_L 9 32 4 HOOPER 3.28V 3.30V LIMITED FUNCTIONS
1%
1/16W
50MV OF HYSTERSIS
MF SIZE DRAWING NUMBER REV.
7 2 402
APPLE COMPUTER INC.

D 051-6459 A
SCALE SHT OF
NONE 30 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1MSEC INTEGRATION TIME
PLACE U23 NEXT TO R460 BATTERY SWITCH-OVER CIRCUIT
DC POWER INPUT DC INRUSH LIMITER U23 SENSE VOLTAGE DROP ACROSS R460 R742 C771
0.1UF
+BATT
(POWER JACK, ETC. ON SEPARATE BOARD) 1

1K 2 IAC_RC_COMP 1 2
38 +ADAPTER_SW
CRITICAL
1%
1/16W 20% 1 1
J18 Q13 Q16 MF
402
10V
CERM F4 F3
87438-0833 SI4435DY SI4435DY 402
5AMP-125V
M-RT-SM
SOI SOI 1 C572 +3V_PMU
SM-2
5AMP-125V
SM-2
1 CHARGE_LED_L 30 39
0.01UF
8 8 20%
2 +ADAPTER 3 S3 D4 D4 S3 3 +ADAPTER_SENSE 50V
38 32
7 7
38 2 CERM 2 2
3 2 S2 D3 D3 S2 2 603
NO STUFF
D2 6 6
D2
1 C772 +24V_PBUS +PBUS
4
1 C757 R4142 C458 1 1
S1 5 5 S1 1 0.1UF
D
D 5
6
0.1UF
20%
330K
5%
1/16W
0.1UF
20%
50V
GATE
D1 D1
GATE
1
R7471
42.2K
20%
10V
2 CERM
402
PLACE R358 CLOSE TO LTC1625 38 31 +BATT_24V_FUSE
7
50V
2 CERM MF
402 1
CERM 2
805
4 4 R474 8
0.1%
1/16W ROUTE LTC1625_ITH CAREFULLY
CRITICAL 38 +BATT_14V_FUSE
805 47K FF
LTC1625_ITH
8 ADAPTER_DET 30 5% +24V_PBUS 603 2
39
AC_ENABLE_GATE
1/16W
MF V+ U50 DP4 Q24 D4 CRITICAL
2 +3V_PMU
2 402 U23 2 LMC7111 SI4435DY
R396 PLACE CLOSE
TO DC INPUT MAX4172 IAC_FB 4
SOT23-5
BAS16TW
SOT-363 R358 SOI Q76
20K BCKFD_PROT_GATE
TSSOP 150 1 SUD45P03
1% 2 1 2 1 6 1 2 1 1625_COMP 8 G TO-252
1/16W
MF R374 RS+
CRITICAL
RS- CRITICAL
1%
32
3 S3 D4
D3 7 S 3
1 402
470K C592 1 1 7 3 2 S2
1
5%
1/16W 0.1UF
R499 NC 3 NC1 PG NC R466 1/16W
MF
1 D2 6
C468 1 R363 MF 20%
68K 4 6 MAX4172_OUT 1
10K 2
5 ADAPTER_I_REG 402 S1 5
D1
R3952 R3641 0.01UF
20% 5%
10K 1 402
50V
CERM 2
5%
1/16W
MF
NC
NC2
GND
OUT
1% GATE
102K
1%
102K
1%
16V
CERM 2
1/16W
MF
AC_ENABLE_L
805
2 402
1/16W
MF R4901 4
R7461
1/16W 1/16W 402 BCKFD_PROT_EN_L 402 CURRENT_THRESHOLD 47K 47K
MF MF 2 402 5%
402 1 402 2 3
5
R4541 1 C883 1
5%
1/16W 1/16W
MF
2.21K 0.1UF 1 +3V_PMU R739 MF
4
2 U15 D Q10
6
0.1% 10%
50V
R738 1
R734 51.1K 402 2 402 2
BATT_14V_GATE
38 32 1V20_REF LMC7211 1/16W 2 X7R 42.2K
SM
2N7002DW
SOT-363
D
Q21 MF 603 0.1% 82.5K 0.1%
1/16W IF ADAPTER IS OVER 18V, BATT_24V_GATE
1 31 30 29 27 AC_IN 5 G S 2N7002DW 603 2 1/16W
FF
0.1%
1/16W FF ADJUST CURRENT SETTING
CRITICAL SOT-363 2 603
31 30 29 27 AC_IN
2 G S 603 2 FF
2 603
R7441
AC_DIV 3 4 A29_CURRENT_ADJ R7481 OVER_18V_ADJ R5121 10K
5%
1 100K 10K
2 2
5 R394 3 5% 5%
DP4
1/16W
MF
R375 R365 1
1M 2
AC_IN_L 31 1/16W 6
31 AC_IN_L
1/16W
MF 402 2
10K
1%
57.6K
1%
D Q20 MF
402 2 D
Q20
1 C775 402 2
SOT-363
BAS16TW
5% 2N7002DW 1UF
BAS16TW
1/16W 1/16W 1/16W 2N7002DW 20% 1 BATT_24PBUS_EN 5 2 BATT_14PBUS_EN
MF MF 6 SOT-363 R489
4
SOT-363
MF A29_DETECT 5 SOT-363 10V
DP4
402 1 402 1 402 31 30 G S AC_GTR_18V 2 G S 2 CERM
2 158K
Q10 D R383 603
1% 3
2N7002DW 470K 4 1 1/16W
MF
R460
3
SOT-363 5%
S G 2 1/16W
0.0252
6 2 402
D Q21
MF 2N7002DW
C 1 1 402
1
1%
IF A29 ADAPTER USED,
ADJUST CURRENT SETTING
D Q65
2N7002DW
AC_IN_L_RC 5 G S
SOT-363 C
1W
1 1 SOT-363
1 R488 MF
2512 R498 31 1772_ACOK_L 2 G S
C593 1 4
R7541 D9 4.7
5%
4.7
5% 10UF
GREATER THAN 13.5V DETECT 100K 1N914 1/16W 1/16W 1 20%
1% SOT23 MF 1772_CSSP 37 MF 6.3V 2
1/16W 3 402 2 CERM
MF 37 1772_CSSN
2 402 805
402 2 WHEN AC IS IN, P-CHANNEL FETS ARE QUICKLY (DIODE) TURNED OFF
R571 D10 WHEN AC IS NOT PLUGGED, P-CHANNEL FETS ARE ON
33 1N914 1772_BST_ESR
+3V_PMU SWITCHER VOLTAGE CONTROL SWITCHER CURRENT CONTROL 1 C600 C578 1 1 C579 38 1772_LDO 1 2 1 3 RC TIME IS 480K*10UF @ +3V_PMU
1 1UF 0.47UF 0.47UF
PMU SELECTS BETWEEN TWO VOLTAGES CHARGE DISABLED BY PMU OR INPUT VOLTAGE <18V R755 20% 20%
50V
20%
50V
5%
1/8W SOT23
+24V_PBUS
CHARGE THROTTLED BY LOW BATTERY VOLTAGE 12.7K
1% 2 50V
CERM1 CERM 2
1206
2 CERM
1206
R5491 FF
1206
1
R774
1/16W 1210 100K 4.7
MF 5% 5%
1 1 1 402 2 1/16W C624 1 1/16W
R567 R558 R548 27 26 MF
402 2 0.1UF
20%
MF
2 603
27.4K 10K 10K CSSP CSSN 25V
1% 1% 1% 1 DCIN CERM 2
1/16W 1/16W 1/16W 38 1772_DCIN CELLS 16 1772_CELLS
MF
402 2
MF
402 2
MF
U31 LDO 2
603 C608 1 5 6 7 8 1 C547 1 C562 1 C563 1 C557 1 C564
2 402 1772_ACIN 11 ACIN 0.1UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
OD OUTPUT LOW - WHEN AC GREATER THAN 18V 31 1772_ACOK_L 12 ACOK MAX1772 DLOV 22 1772_DLOV
20%
50V CRITICAL
20%
50V
20%
50V
20%
50V
20%
50V
20%
50V
QSOP 38
CERM 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
(+3V_PMU) 13 RFIN BST 25 1772_BST 805

Q63 1812 1812 1812 1812 1812
15 VCTL CRITICAL IRF7805

1772_VCTL DHI 24 1772_DHI 4
SM
1772_ICTL 14 ICTL +BATT_RSNS 38
CRITICAL
1 LX 23 38 1772_LX
R560 1 1
1772_ICHG 10 ICHG DLO 21 1772_DLO
1 2 3
L42 +BATT_24V_FUSE 31 38
4.12K R565 R566 28 IINP 10uH R763

1% 1772_IINP PGND 20 (GND)
1/16W 48.7K 1K 0.05 2
MF
402 2
1%
1/16W
1%
1/16W R5421 7 CCV CSIP 19 37 1772_CSIP
1 2 1
MF MF 1K 1772_CCV SM1 1%
CSIN 18
B R5611
BATTV_HIGH
402 2
BATT_LOW_L
402 2 1%
1/16W
MF
402 2
1772_CCI
1772_CCS
6 CCI
5 CCS BATT 17
37 1772_CSIN
5 6 7 8
2
D30
1W
MF
2512
1 C619
4.7UF
1 C632 1 C617
B
100K C817 1 1 C802 SM 20% 4.7UF 1
C824
5% 6 REF = 4.096V 1 C652 CRITICAL MBRS140T3 25V 20% 4.7UF
1 REF CLS GND 0.1UF 0.1UF 25V 33UF
1/16W
MF D
Q27 R580 6 3 R5261 C622 1 1 C616 4 3 8 9
1UF 20%
25V
20%
Q64 1
2 CERM
1206
2 CERM 20%
2 25V 20%
402 2 5.23K 1K 0.01UF 0.01UF
20%
10V CERM 2 2 25V
CERM
1206 CERM
1206 2 25V
2N7002DW 1% D
Q29 D
Q29 1% 2 CERM IRF7811W ELEC
BATTV_LOW 2 G S
SOT-363 1/16W
MF 2N7002DW 2N7002DW 1/16W
MF
20%
16V
20%
2 16V 603
603 603
NO STUFF
4
SO-8 R543 1
R511 1
C631 1 C633 1
C618 1
SM1
CERM 2 CERM 1 1 4.7UF
2 402
SOT-363 SOT-363 402 2 4.7UF 4.7UF
2 G S 5 G S 402 402 1 C906 5% 5% 20% 20%
25V
3 1
1772_CCV_RC 1772_REF R4871 0.0022UF 1 2 3
1/16W
MF
1/16W
MF
25V
CERM 2 CERM 2
20%
25V
CERM 2
1 4 1 10K XW19 10%
2 50V
603 2 603 2 1206 1206
1206
D
Q27 R497 1%
1/16W
R5591 SM CERM
2N7002DW
SOT-363 1%
1K 1 C621 C630 1 MF
402 2
100K
5%
1 2
402
30 PMU_CHARGE_V
5 G S 1/16W 0.1UF 1UF 1/16W
MF 20% 20% 1772_CLS MF
2 402 2 10V
CERM 10V 402 2
4 +3V_PMU
402 CERM 2
603 R4731
4.12K
1%
1/16W
R5781 +3V_PMU
MF
402 2
100K 6
5% 38 1772_GND
1/16W +BATT
MF
402 2
D
Q30 38 +BATT_VSNS
2N7002DW
CHARGE_DISABLE 2 G S
SOT-363
1 C615 R5881 1
R579 BATTERY 2
3 1
0.1UF
20% 100K
1%
499K
1%
R7491 CONNECTOR L9
10V
2 CERM 1/16W 1/16W
6.34K L53
MF MF 1% CRITICAL FERR-EMI-100-OHM FERR-50-OHM
D
Q30 402 402 2 2 402
1/16W
MF J25 SM
2N7002DW
SOT-363
U38 2
4
402 2
87438-0833
1 2
5 LMC7211
30 PMU_CHRG_BATT_0 G S
BATT_LOW 1
SM BATT_DIV
A29_CLS_ADJ M-RT-SM 1
L10
SM
BATTERY CHARGER
A 4 CRITICAL
3
1V65_REF 3 1
2 39 38 +BATT_POS
FERR-EMI-100-OHM A
D
Q65 3 (BATT_IN_PD) 1 2 PMU_SMB_CLK 30
5 2N7002DW SM
SOT-363 4 39 BATT_CLK THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
R5991 1
R570 1 C658 31 30 A29_DETECT
5 G S
5 39 BATT_DATA
V = CELLS X (4.096 + (0.4096 * V / V )) 100K 100K 0.047uF
BATT VCTL REFIN 1%
1/16W
1%
1/16W 10% 4 6 PMU_BATT_DET_L 30 39 L8 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
For 4.15V cells, VCTL = 0.123 REFIN MF MF 2 16V

CERM 7 39 38 BATT_NEG
FERR-EMI-100-OHM II NOT TO REPRODUCE OR COPY IT
402 2 2 402
For 4.20V cells, VCTL = 0.245 REFIN
402
8 L12 1 2 PMU_SMB_DATA 30
FERR-50-OHM SM
I = (0.2048/R ) * (V / V ) 1 2 SIZE DRAWING NUMBER REV.
CHG _62 ICTL REFIN
SM
APPLE COMPUTER INC.
D 051-6459 A
SCALE SHT OF
NONE 31 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
Q14
FDG6324L
+5V_MAIN SC70-6
3
4 S2 D2 2 1625_EXTVCC 38
1
R426 G2
470K 6
5%
1/16W
MF
402 2
D 1625_ENABLE_L
D
6 CRITICAL
1625_ENABLE 5 G1
D1
S1
Q14
FDG6324L
SC70-6
1 C495
0.1UF
12.8V PBUS SUPPLY +24V_PBUS
20%
1 2 10V
CERM
402
PBUS HOLD-UP CAPS
CONNECT LTC1625 TK PIN AT TOP-SIDE FET
KEEP VIN/TK LOOP SHORT
5 6 7 8
+3V_PMU
1625_INTVCC
C644 1 C787 1 C585 1 C626 1
C750 1 C799 1
38
2.2UF 2.2UF 2.2UF 2.2UF 22uF 22uF
2 20% 20% 20% 20%
R412 NO STUFF 50V
CERM 2
50V
CERM 2
50V
CERM 2
50V
CERM 2
20%
35V 2
20%
35V 2
5%
1 1
R402 Q59 1812 1812 1812 1812
ELEC
SM-1
ELEC
SM-1
1/16W 0 1 IRF7805
R4431 C537 1 MF 5% 1625_TG 4
SM
C801 C569 C604
102K 0.1UF 603 1 1/16W
MF EXTVCC D3 CRITICAL
1 1 1 1
C820 1
C821 1
C819
1% 20%
U18 2.2UF 2.2UF 2.2UF 22uF 22uF 22uF
1/16W 10V 2 402 SM 20% 20% 20% 20% 20% 20%
MF CERM 2 LTC1625 1 2 1625_BST_ESR 2 50V 2 50V 2 50V 2 35V 2 35V 2 35V
402 2
402 38 1625_VIN 16 VIN SSOP BG 10 1 2 3 CERM CERM CERM ELEC ELEC ELEC
1812 1812 1812
2 U21 15 TK CRITICAL TG 13 1
R401
SM-1 SM-1 SM-1
1V20_REF 4 LMC7211 MBR0540 1 C509
38 31
SM D4 2 SYNC VOSENSE 7
5%
2.2
0.22UF
3 11
CRITICAL
1 3 1 1625_RUNSS
5
RUN/SS INTVCC 1/16W
MF
20%
2 25V
L37 +PBUS
3 31 1625_COMP ITH 2 603 CERM 3 CRITICAL
1625_DIV 1N914
SOT23 1625_FCB 4 12 1625_BST
805
FCB BOOST
C R4331
5 R432
1
1M 2 C485 1
8 VPROG SW 14 38 1625_VSW 2 1
C
10K R3792 4700pF SGND PGND 8.0UH-6.8A
1%
1/16W
1%
1/16W C510 1 4.99K 5%
25V 6 9 5 6 7 8
SM1 1 C535 1
R359 C765 1 1
C769
MF MF 1% CERM 2 4.7UF 158K 33UF 33UF 1
C794
402 2 402 0.1UF 1/16W 603 20% 1% 20% 20%
20%
50V
MF
402 1 1 CRITICAL 2 25V
CERM 1/16W 25V 2 2 25V 33UF
CERM 2
805
R392 Q60 1206 MF
2 402
ELEC
SM1
ELEC
SM1
20%
2 25V
0 ELEC
5% IRF7811W SM1
COMP_RC
1 C462 1/16W
MF
1625_BG 4
SO-8 2
470pF D27
10% 2 402 NO STUFF
50V SM
WHEN +24V_PBUS IS BELOW ~13.44V, 2 CERM
1 C554 1 2 3 MBRS140T3
1
C758
C463 1
603 1 C461 C536 1
1
R360 C822 1 33UF
1625 IS SHUT-OFF
4700pF 4.7UF 0.0047UF
10%
1
4.7UF 16.2K 33UF
C793 1 20%
5% OMIT 20%
10V 25V
2 CERM 20% 1% 20%
33UF 2 25V
ELEC
25V 2 CERM 1/16W 25V 2 20% SM1
CERM 2 402 25V 25V 2
603 XW4 1206 CERM 2 MF ELEC ELEC
SM
1206 2 402 SM1 SM1
38 1625_SGND 1 2
1625_VFB
BACKUP BATTERY / USB CONNECTOR

B +5V_MAIN
B
CRITICAL
J11
54550-1490
F-RT-SM
BOOTSTRAP SYSTEM FROM
ADAPTER OR BATTERY
PMU SUPPLY
15
R508 D17
SM +5V_MAIN
38 31 +ADAPTER 1
390 2 38 +ADAPTER_ILIM 1 2
D7
SM 3V_PMU_VTAP
1 NC
5% 1 2
2 +PBUS 1/4W
3
FF MBR0540 6 CRITICAL 6 CRITICAL
1210
4 PLUS5VTAP MBR0520LT VTAP +3V_PMU
DCDC_EN 19 29 33 34 39
+BATT
5 D18 U30 D11 (+4_6V_BU) U25
6 1N914 LP2951 +4_85V_RAW 30 38 SM +4_6V_BU 33 38 LP2951
RIGHT_USB_DM 26 37 39 SOI SOI-3.3V
+24V_PBUS 1 3 38 +ADAPTER_OR_BATT 8 1 1 2 8 1
7 RIGHT_USB_DP 26 37 39
IN OUT IN OUT
2 5 2 5
8 SOT23
2 SENSE ERR 1
R483 SENSE ERR
9 NEC_RIGHT_USB_PWREN 26 39
D19 3
SHUT FDBK 7
R5211 1
MBR0520LT 3
SHUT FDBK 7 1
R468
10
SM
MBR0540 GND 294K
1%
1 C613 5%
1/16W GND 5%
1
1/16W 470pF MF 1/16W
11 NEC_RIGHT_USB_OVERCURRENT 1 4 MF 10%
26 39
402 2
50V
2 CERM 2 603 4 MF
12 2 603
13 NC
1 C625 C599 1 FB_4_85V_BU
603
+4_85V_ESR
3V_PMU_SENSE
0.1UF 0.1UF 38
+3V_PMU_ESR 38
14 20%
50V
2 CERM
20%
10V
1 C553
CERM 2 0.1UF
+PBUS IS BOTH AN INPUT AND OUTPUT TO BUBBA
805 402 R5411 1 C568 20%
16 100K
1% 2.2UF
10V
2 CERM 1 C584
20% 402 10UF
24V IS AN OUTPUT FROM BUBBA 1/16W
MF
10V
2 CERM 20%
6.3V
402 2 805 2 CERM
805
12.8V REGULATOR
A NOTICE OF PROPRIETARY PROPERTY
A
APPLE COMPUTER INC.

D 051-6459 A
SCALE SHT OF
NONE 32 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3.3V/5V MAIN SUPPLY

+24V_PBUS
C516 1 C508 1 C763 1 C770 1 8 7 6 5 5 6 7 8 1 C806 1 C800 1 C779 1 C785

D 2.2UF
20%
50V
2.2UF
20%
50V
2.2UF
20%
50V
2.2UF
20%
50V CRITICAL
2.2UF
20%
2.2UF
20%
2.2UF
20%
2.2UF
20%
D
CERM 2 CERM 2 CERM 2 CERM 2
CRITICAL 2 50V
CERM 2 50V
CERM 2 50V
CERM 2 50V
CERM
38 3707_INTVCC
1812 1812 1812 1812
Q61 Q71 1812 1812 1812 1812
SI4888DY SI4888DY
SOI
4
R4561 1
R477 1 C567 3V_TG 4
SOI
+5V_MAIN 38 5V_RSNS 0 47K 4.7UF 3V_RSNS
+3V_MAIN
CRITICAL 5% 5% 20% CRITICAL 38
R431 1 1/16W 1/16W 2 10V 1

R520
L38 3 2 1 D6
1
1M MF MF
CERM
1206 1M
1
D13 1 2 3
L41
R731 4.7UH SM 5%
402 2 2 402 5% SM
4.7UH R515
1
0.0052 1 2 MBR0540 1/16W
+5V_MAIN
1/16W
MBR0540 1 2
0.0052
1
MF MF
2 402 2 2 402 2
1% IHLP-5050 IHLP-5050 1%
1/4W 1/4W
C759 1 FF
1206
8 7 6 5 5V_BOOST_ESR NC 3V_BOOST_ESR 5 6 7 8 FF
1206
1 C811
C756 1 22UF 2 2 22UF 1
C823
330UF
20%
10V
CERM 2
D22 CRITICAL
1
R457
22 21
EXT INT VIN 3.3
24 10
R482 1 CRITICAL D34 20%
2 10V 330UF
20%
6.3V 2 1210 MBRS140T3
SM
Q52 C545 1
2.2 VCC VCC VOUT 2.2
1 C598 Q72
SM
MBRS140T3
CERM
1210 20%
2 6.3V
TANT 0.22UF 0.22UF POLY
CASE-D4
1 1
1 SI4888DY 4
20%
25V
5%
1/16W U28 5%
1/16W 20%
25V 4
SI4888DY 1 SMD
R378 R369 SOI CERM 2 MF
2 603
LTC3707 MF
603 2
2 CERM SOI R5291 R5391
1 C760 10
5% 5%
10 805 5V_TG 27 TG1 SSOP TG2 16 805 10
5% 5%
10 C826 1
22UF 1/16W 1/16W 5V_BOOST 25 BOOST1 BOOST2 18 3V_BOOST 1/16W 1/16W 22UF
20% MF MF MF MF 20%
10V 3 2 1 5V_SW 26 SW1 17 3V_SW 1 2 3 10V
2 CERM 2 402 2 402
38 SW2 38 402 2 402 2 CERM 2
1210 5V_BG 23 BG1 CRITICAL BG2 19 3V_BG 1210
2 SNS1+ SNS2+ 14
37 5V_SNSP 37 3V_SNSP
37 5V_SNSM 3 SNS1- SNS2- 13 37 3V_SNSM
C532 5V_VOSNS 4 VOSNS1 VOSNS2 12 3V_VOSNS C620

0.001uF 8 0.001uF
1 2
5V_ITH ITH1 ITH2 11 3V_ITH
1 2
5V_RUNSS 1 RUN/ RUN/ 15
SS1 SS2
C R4631 1 C566
20%
50V 7 FCB
3V_RUNSS
1 C611
20%
50V C590 1
1
R507 C
113K
1% 180pF
CERM
402 C583 1 C533 1
3707_FSET 5 FREQSET
PGOOD 28 0.001uF
CERM
402 180pF 1%
63.4K
1/16W 5%
50V
0.001uF 0.047UF 1 C612 20% 5% 1/16W
20% 10% 6 50V 50V
MF 2 CERM 50V 16V STBYMD 0.1UF 2 CERM CERM 2 MF
402 2 402 CERM 2 CERM 2 20% 402 402 2 402
402 402 3707_FCB 10V
SGND PGND 2 CERM
5V_ITH_RC 3V_ITH_RC
3707_STBY 9 20 402
1 1 1 1 1
R462 R481 1 C576 C560 1 R467 C610 1 R519 R514
21.5K 4.99K 270PF 0.01UF 20K 270PF 4.99K 20K
1% 1% 5% 20% 5% 5% 1% 1%
1/16W 1/16W 25V 16V 1/16W 25V 1/16W 1/16W
MF MF 2 CERM CERM 2 MF CERM 2 MF MF
402 2 402 2 402 402 2 402 402 2 402 2 402
5V START TO TURN ON ~12.5MS AFTER DCDC_EN_L
38 3707_SGND
3V START TO TURN ON ~25MS AFTER DCDC_EN_L
DIODE WILL ENSURE DCDC_EN_L IS QUICKLY DISCHARGED DURING SHUT-DOWN 3

3V_5V_OK 35
POWERDOWN DELAY IS AROUND 4MS-15.6MS
R523
D
Q23 2
2N7002DW XW8 1 C534 THIS SIGNAL IS OPEN COLLECTOR TO GND WHEN POWER IS NOT GOOD
1M 5 SOT-363 SM 220PF IS USED TO QUIET NOISE ON PGOOD ONCE INTERNAL OPEN DRAIN IS DISENGAGED
35 33 DCDC_EN_L 1 2 LTC3707_START_RC G S 220PF
5%
5%
+4_6V_BU 1 2 25V
32 38 1/16W
MF
402
4 CERM
402 THERE’S NO 10UF INPUT CAP
1
R506 BECAUSE Q21 IS PLACED AT
470K
5%
1/16W
OUTPUT OF +3V_MAIN SWITCHER
MF D16 1 C609
2 402 3 1 0.01UF
20% +3V_MAIN +3V_SLEEP
DCDC_EN 19 29 32 34 39 16V
1N914 2 CERM
+3V_SLEEP +5V_MAIN
R528 6
SOT23 402
100K 2
PMU_POWER_UP_L 1
B 30 29
5%
35 33 DCDC_EN_L
D
Q23
2N7002DW DCDC_EN TRUTH TABLE 1
NO STUFF SLEEP_L_LS5_NET 35
R538 4 +3V_SLEEP LOADS B

1/16W
MF
3 2 SOT-363 R310 100K 2
402 G S 100K 39 35 33 30 25 23 SLEEP 1 3 6 1) CPU PLL Config Control
NO STUFF 5% 3 NO STUFF
D
Q25 1
PMU_POWER_UP_L SLEEP DCDC_EN DCDC_EN_L State 1/16W
MF
5% 5 2) INTREPID - IIC AND PCI PULL-UPS
2N7002DW 1 C623 0 0 1 0 Run
1
R308 2 402
D Q81 1/16W
MF 2 3) MAP31 - 3V RAIL (IF USING D3COLD)
39 35 33 30 25 23 SLEEP 5 G S
SOT-363 0.01UF 100K 2N7002DW 402
1
20% SOT-363 4) GRAPHIC CHIP SPREAD SPECTRUM CHIP
16V 5% +3V_SLP_OK_L 5 G S TSOP
2 CERM 1 (2.99V) 1 1 0 Sleep 1/16W NO STUFF 5) LVDS DDC PULL-UPS
4 402 MF SI3443DV
1 0 0 1 Shutdown 2 402 6 NO STUFF 4 1
R300 Q28 6) DVI LEVEL SHIFTERS & PULL-UPS & HPD
100K 7) SOUND BOARD
+5V_MAIN +3V_PMU +3V_PMU +4_6V_BU +3V_PMU VOLTAGE
D Q81 5%
C662 2N7002DW 1/16W 8) BOOT BANGER
0.01UF +3V_SLP_ON 2 G S
SOT-363 MF
2 402
C639 9) HARD DRIVE (IF USING 3V LOGIC)
+5V_MAIN 2200pF
1 2 +5V_SLEEP LOADS NO STUFF
3V_SLEEP_PWREN_L 2 1 10) WIRELESS (IF POWERING OFF IN SLEEP)
1 1
20% 1) OPTICAL DRIVE R309 11) PMU - IIC Pull-ups
16V 470K 1
5%
50V 12) PCI PULL-UPS
CERM
402 4
2) DVI
SLEEP LEVEL SHIFTER (3V -> 5V)
5%
1/16W R298 CERM
R589 +5V_HD_SLEEP 24 38
3) TRACKPAD MF 100K 3 NO STUFF
603
100K 2 3 6 4) FANS 2 402 5%
1/16W
33 SLEEP_LS5 1 5V_HD_PWREN +5V_MAIN
5% 5 5) FIREWIRE PHY
MF
2 402
D Q79
1/16W 2N7002DW
MF
402
1 C659 2 1
C825 SLEEP_NET_INV5 G S
SOT-363
10UF 1 100uF
20% TSOP 20%
6.3V
2 CERM
805
SI3443DV 2 10V
POLY R3771 R3501 6 NO STUFF
4
Q32 SMD-3 100K 100K

5%
1/16W
5%
1/16W R296
D
Q79
MF MF 2N7002DW
C700 402 2 402 2 100K 2 SOT-363
39 35 33 30 25 23 SLEEP 1 SLEEP_NET 2 G S
0.1UF
1 2
SLEEP_L_LS5 19 27 34 35
SLEEP_LS5 33 5%
1/16W 1 3.3V/5V REGULATOR
A 20%
10V
SLEEP_L_LS5_EN_L 6 SLEEP_LS5_EN_L 3
MF
402
A
CERM +5V_SLEEP
R697 402 4
R368
D Q9 R367
D Q9
2N7002DW 2N7002DW THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
100K 2 3 6 1
100K 2 2 G
SOT-363
1
100K 2 5 G
SOT-363 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
5V_SLEEP_PWREN 39 35 33 30 25 23 SLEEP S S
5% 5 5% 5% ADDED FOR M10 POWER SEQUENCING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1/16W 1/16W 1 1/16W 4
MF
402
1 C697 2 1
C694 MF
402
MF
402
1 C456 II NOT TO REPRODUCE OR COPY IT
10UF 1 100uF 0.01UF III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
20% TSOP 20% 20%
6.3V 16V
2 CERM SI3443DV 2 10V 2 CERM SIZE DRAWING NUMBER REV.
POLY
805 SMD-3 402
Q43 D 051-6459 A
APPLE COMPUTER INC.
SCALE SHT OF
NONE 33 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+3V_MAIN
1.175V -> 1.025V 1.30V -> 1.10V
VCORE POWER SEQUENCING
CPU core follows CPU I/O voltage NO STUFF NO STUFF NO STUFF VCORE_FAST<1> 34
1 1
1 C439
(approx. 7ms delay)
R297 R314
1 R328 1R324 1
R304 1
R329 1R325 1
R322 0.1UF NO_4XVCORE
VCORE_FAST<2> 34
470K
470K 0 0 0 470K 470K 10K 16 20% 1
R288
+5V_MAIN
5% 5% 5% 5% 5% 5% 5% 5% 2 10V
CERM NO_4XVCORE
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W VCC 402 0 VCORE_FAST<3> 34
MF MF MF MF MF MF MF 5% 1
MF
2 402 2 402 2 402 2 402 2 402 2 402 2 402 1/16W R289NO_4XVCORE
2 402 U11 MF
402
0 VCORE_FAST<4> 34
2
PI3B3257 4
2 5% 1
1/16W R290
VCORE_SLOW<1> VCORE_VID<1>
R408 1
R398 1 1
R356 A1 QSOP Y1
SYM_VER-2
34
MF 0 NO_4XVCORE
100K 34 VCORE_FAST<1> 3 2 402 5%
100K 100K 1%
B1 1/16W 1
R292
5% 5% VCORE_SLOW<2> 5 Y2 7 34 VCORE_VID<2> MF
1/16W 1/16W DP2 1/16W A2 2 402 0
D 38 23 16 15 8 7 5 MAXBUS_SLEEP MF
402 2
MF
402 2 BAS16TW
SOT-363
MF
2 402
VCORE_SLOW<3>
34 VCORE_FAST<2>
11
6
B2
A3 Y3
9 34 VCORE_VID<3>
5%
1/16W
MF
39 38 34 5 CPU_VCORE_SLEEP D
CPU_VCORE_PWR_SEQ 6 1 34 VCORE_FAST<3> 10 2 402
B3 C2 1 C689 1 C5 1 C699 1 C234 1
VCORE_SLOW<4> 14 12 34 VCORE_VID<4>
A4 Y4 10UF 10UF 10UF 10UF 10UF
13
R318 34 VCORE_FAST<4>
B4 20%
6.3V 2
20%
6.3V 2
20%
6.3V 2
20%
6.3V 2
20%
6.3V 2
1
3 0 1 CRITICAL SEL = 0; Y1=A1 CERM CERM CERM CERM CERM
R267 CPU_VCORE_SEQ_L 34 30 7 CPU_VCORE_HI_OC 1 2 VCORE_MUX_SEL
SEL SEL = 1; Y1=B1
805 805 805 805 805
10K
5%
1 Q12 5%
1/16W
39 VCORE_MUX_EN 15
OE
1/16W 2N3904 MF
MF SM 402 NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF GND Keep trace fat (40-100 mils) and short!!
402 2 3 2 1
R303 1R313 1R327 1R323 1R301 1
R305 1
R330 1R326 1
R302 8
C682 1 C674 1 C274 1 C7 1 C680 1
CPU_VCORE_SEQ 1 Q17 0 470K 470K 470K 470K 0 470K 0 +PBUS
10UF 10UF 10UF 10UF 10UF
5% 5% 5% 5% 5% 5% 5% 5% 1K 20% 20% 20% 20% 20%
2N3904 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 5% 6.3V 6.3V 6.3V 6.3V 6.3V
SM MF MF MF MF MF MF MF MF 1/16W CERM 2 CERM 2 CERM 2 CERM 2 CERM 2
2 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 MF 805 805 805 805 805
<D4> <D3> <D2> <D1> <D4> <D3> <D2> <D1> 2 402 CRITICAL CRITICAL CRITICAL CRITICAL
1 1 1 1
C427 C431 C443 C430
+5V_MAIN 8.2UF 8.2UF 8.2UF 8.2UF
DP2 20%
2 16V
20%
2 16V
20%
2 16V
20%
2 16V C693 1 C13 1 C116 1 C6 1 C695 1
BAS16TW TANT
CASE-D
TANT
CASE-D
TANT
CASE-D
TANT
CASE-D
10UF 10UF 10UF 10UF 10UF
SOT-363 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V
5 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2
35 33 27 19 SLEEP_L_LS5 805 805 805 805 805
38 VCORE_VCC PLACE C423 CLOSE 1 CRITICAL CRITICAL CRITICAL
DP2 TO PINS 15 & 13!! D2 CRITICAL
1 1 1
BAS16TW
SM 1
C432 C441 C444 C445
SOT-363 R3491 1 C498 MBR0530 8.2UF 8.2UF 8.2UF 8.2UF
39 33 32 29 19 DCDC_EN
4 3 20 20%
1UF 2 20%
2 16V
20%
2 16V
20%
2 16V
20%
2 16V C679 1 C285 1 C4 1 C3 1 C687 1
5% TANT TANT TANT TANT 10UF 10UF 10UF 10UF 10UF
2 10V
VCORE_BOOST
1/16W CASE-D CASE-D CASE-D CASE-D 20% 20% 20% 20% 20%
CERM 6.3V 6.3V 6.3V 6.3V 6.3V
MF 603
402 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2
805 805 805 805 805
C 38
5 5 C
NO STUFF
+3V_MAIN R4071 C507 1 7 15 CRITICAL CRITICAL XW15
R384 1
0
1UF VCC VDD SM
0 R397 5%
1/16W 20% Q50 Q49
34 30 7 CPU_VCORE_HI_OC 1 2
27.4K MF 10V
CERM 2
U20 SI7860DP SI7860DP
CPU_VCORE_SLEEP_F 1 2
5%
1/16W
1%
1/16W
402 2
603 MAX1717 VCORE_VPLUS
4
SO-8-PWRPK 4
SO-8-PWRPK
MF MF QSOP NO STUFF CRITICAL
402 2 Keep trace fat and short!! CPU_VCORE_SLEEP
402 VCORE_SHDN_L 2 SKP/SDN V+ 1
R429 1 C455 L36
5 34 38 39
(VCORE_SNS) 5 FBS 2.2 0.0047uF 1 2 3 Keep trace fat and short!! CRITICAL
3
BST 22 10% 1 2 3
38 VCORE_ILIM 10 ILIM
VCORE_BST 2 1
25V
2 CERM R331
R366 DH 24 5%
402 0.0012
1
(VCORE_GNDSNS) 11 GNDS 1/16W 1
0 MF
14 INT_GPIO1_PU 1 2 34 MAX1717_AB_SEL 16 A/B 603 1.2UH-18.3A 1%
5% NO STUFF CRITICAL 38 VCORE_DH
1 C518 5 6 7 8 5 6 7 8 5 6 7 8 SM1
1W
MF
1/16W
1 0.1UF 2512
MF
402 R337 38 VCORE_REF 9 REF 20%
25V CRITICAL CRITICAL CRITICAL
470K 2 CERM
5% 603
1/16W
MF
38 VCORE_TON 8 TON LX 23 38 VCORE_LX Q54 Q55 Q53
IRF7832 IRF7832 IRF7832 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
2 402 6 DL 14 4 4 4 CRITICAL
38 VCORE_CC CC 38 VCORE_DL
SO-8 SO-8 SO-8 2 C728 1 C734 1 C733 1 C732 1 C885 1
34 VCORE_VID<0>
<D0> MIN_LINE_WIDTH=10 21 D0 GND 13 38 VCORE_GND R7321 D25 220UF 220UF 220UF 220UF 220UF
2.2 B540C 20% 20% 20% 20% 20%
34 VCORE_VID<1> MIN_LINE_WIDTH=10 20 D1 XW5 1 2 3 1 2 3 1 2 3 5% 1
SM 2V 2
TANT
2V 2
TANT
2V 2
TANT
2V 2
TANT
2V 2
TANT
34 VCORE_VID<2> MIN_LINE_WIDTH=10 19 D2 FB 4 39 38 VCORE_FB
SM C768 1 NO STUFF 1/4W
MF
7343 7343 7343 7343 7343
MIN_LINE_WIDTH=10 18
1 2 0.0047uF 1210 2
34 VCORE_VID<3> D3 TIME 3 VCORE_TIME 38 10% CRITICAL CRITICAL CRITICAL CRITICAL
34 VCORE_VID<4> MIN_LINE_WIDTH=10 17 D4 VGATE 12 VCORE_VGATE 14 38
R415 25V
CERM 2 CPU_VCORE_SNUB 1
C731 1
C730 1
C729 1
C884
1
100 2
402
220UF 220UF 220UF 220UF
MAX1717 VID CAN TAKE 3.3V TO 5.5V INPUTS 20% 20% 20% 20%
1
R336 C529 1 R4481 R3851 1 C459 C512 1 1
5%
C764 2 2V 2 2V 2 2V 2 2V
470K 0.01UF 66.5K 12.7K 1UF 220PF
5%
R434 C521 1
1/16W
MF
0.0022uF
1
TANT
7343
TANT
7343
TANT
7343
TANT
7343
5% 20% 1% 1% 20% 25V 390K 0.001UF 402
1/16W 16V 1/16W 1/16W 10V CERM 2 5% NO STUFF 10%
50V
MF CERM 2 MF MF 2 CERM 1/16W 20%
B 2 402 402 402 2 402 2 603 402 MF
402 2
50V
CERM 2 XW7
SM
CERM
603 2
B
402
VCORE_GNDA 1 2
+5V_MAIN VCORE_OFFSET Connect MAX1717 GND pin 13
R805 1 1
R376 to GND at bottom-side FET Keep trace fat and short!!
1
100K 2
VCORE_SEL_OFF_PU
R809 162K
1.5K 1% GROUND SENSE VOLTAGE DIVIDER
5% 1% 1/16W R2
1/16W 1/16W MF
MF MF This allows for an offset to the ground sense to adjust the output voltage.
402 2 402 2 603
NO STUFF
VCORE_SEL_ON VCORE_GNDDIV
VREF = 2.0V, HENCE VOFFSET = 2.0V * (R1/(R1+R2)) AND VCORE = VDAC + VOFFSET.
34 38
R806
OUTPUT VOLTAGE 1
0 2
6
1
R321
OMIT
PLACE THIS SHORT AT
5%
1/16W
D
Q86 3.01K PIN OF 1000uF CAP
VDAC MF 2N7002DW
SOT-363
1%
1/16W
R1
NOTE: R310 (R2) NO STUFFED FOR NO OFFSET CASE
CLOSEST TO CPU
XW3
D3 D2 D1 D0 34 MAX1717_AB_SEL
402 2 G S MF
2 402 SM
D4=0 D4=1 R807
0
1 38 34 VCORE_GNDSNS 2 1
1 2 AB_SEL_LOW
2.00 1.275 0 0 0 0 3 38 VCORE_SNS
5% D Q86 ROUTE AS DIFFERENTIAL PAIR
1.95 1.250 0 0 0 1 1/16W
MF 2N7002DW NO STUFF
402
SOT-363
1.90 1.225 0 0 1 0 5 G S
R315
1.85 1.200 0 0 1 1 NO STUFF 4 38 34 VCORE_GNDDIV 1
2.05K2 FMAX CONNECTOR
CRITICAL
1
1.80 1.175 0 1 0 0 R808 1%
1/16W NO STUFF
100K MF
1.75 1.150 0 1 0 1 5%
1/16W PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_HEAD
402 J5
M-ST-SM-52465-1217
MF TABLE_5_ITEM
A
1.70
1.65
1.125
1.100
0
0
1
1
1
1
0
1
2 402 114S3013
114S4993
1
1
RESISTOR
RESISTOR
R321
R321
?
?
1_30_VCORE
1_32_VCORE
TABLE_5_ITEM
NO STUFF
R312
100
VCORE_GNDDIV_TEST
1
2
12
11
VCORE_VID<0>
VCORE_VID<1>
34
34
VCORE SUPPLY
1.60 1.075 1 0 0 0
38 34 VCORE_GNDSNS 1
1%
2 VCORE_GNDSNS_TEST
30 +3V_PMU_RESET
3
4
10
9
VCORE_VID<2>
VCORE_VID<3>
34
34
A
1/16W
MF 30 23 22 SOFT_PWR_ON_L
5 8 VCORE_VID<4>
1.55 1.050 1 0 0 1 FOR V-STEP: 402
NC (RFU)
6 7
34
1.50 1.025 1 0 1 0 When A/B_ is high (fast): D4-D0 read as-is I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1.45 1.000 1 0 1 1 A/B_ = When A/B_ is low (slow): <=1K-ohm -> 0 II NOT TO REPRODUCE OR COPY IT
1.40 0.975 1 1 0 0 D<4..0> Hi/Fast Lo/Slow >=100K-ohm -> 1
<= 1K PU 1 0 SIZE DRAWING NUMBER REV.
1.35 0.950 1 1 0 1
1.30 0.925 1 1 1 0
>= 100K PU
>= 100K PD
1
0
1
1 If all pull-ups are >=100K and all APPLE COMPUTER INC.
D 051-6459 A
<= 1K PD 0 0 pull-downs are <=1K, V A = V B . SCALE SHT OF
NO CPU NO CPU 1 1 1 1 NONE 34 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+1_5V_SLEEP LOADS
1) AGP I/O - IF USING D3COLD
+1_5V_MAIN
1
R715
0 2
2) MAXBUS I/O - IF 1.5V INTERFACE
+1_5V_SLEEP
1.5V/2.5V SWITCHER
+1_5V_SLEEP_VIN
5%
1/16W
MF Q46 +1_5V_MAIN LOADS +5V_MAIN +2_5V_SLEEP LOADS
603 SI3446DV 1) FBCORE/FBIO IF USING D3COLD
NO STUFF 1 TSOP 1) INTREPID CORE 2) INTREPID MEMORY I/O
38 +1_5V_LDO
2) AGP I/O IF USING D3HOT
R712 2
D 1
0 2
5 THERE’S 100K PULL-UP ON PG 31 ALREADY
+2_5V_MAIN LOADS
+2_5V_MAIN +2_5V_SLEEP D
6 3 1_5V_SLEEP_EN_L 35
5%
BAS16TW
1/16W
R461 1 R480
2
1) MAP31 - FBCORE/FBIO IF USING D3HOT
SOT-363
MF 4 20
DP3
603 100K 2 1 38 MAX1715_VCC 2) GIGABIT ETHERNET - AVDDL
5%
C723 1 1 C726 1/16W
MF
5% 3) DDR SODIMMS - CORE/IO 2 3 6 7
10UF 2200pF 1/16W 1 C603
5
402 2
20%
6.3V
5%
50V
NO STUFF MF
402
1 C581 2.2UF
4) DDR MUXES
CRITICAL
CERM 2 2 CERM 1 2.2UF 20% 5) CLOCK SLEWING I/O
805 603 R421 20% 2 10V
Q85
35 33 3V_5V_OK 0 2 10V
CERM
CERM
805
6) PCI1510 CORE R709
DP3 5%
1/16W 805
NO STUFF
SLEEP 1
100K 2 4
SI6467BDQ
BAS16TW MF 1
R419 39 35 33 30 25 23 TSSOP
SOT-363
2 402 0 5%
+5V_MAIN 6 1 1/16W
3 5%
1/16W
MF
402
C705 1
1 5 8
10UF
BAS16TW
38 MAX1715_TON MF
D
Q19
3
2 402 20%
SOT-363
DP3
R450 2N7002 6.3V
CERM 2
1 1 330K 2 1 SM 805
R455 R607 33 DCDC_EN_L 1 MAX1715_ON_RC G S
38 2_5V_ILIM 38 1_5V_ILIM +PBUS C709
4
100K 100K 5%
5% 5% 1/16W
MF
1 C531 2 2200pF
1/16W 1/16W
MF MF 402 0.01UF R4181 1
R423 +PBUS 2_5V_SLEEP_PWREN_L 1 2
2 402 2 402 DIODE PROVIDE PROVIDE QUICK SHUT-DOWN 20%
16V 158K 158K NO STUFF NO STUFF
POWER DOWN DELAY 1.5MS TO 3.5MS 2 CERM 1% 1% 5%
1_5V_SLEEP_EN_L 35
402 1/16W
MF
1/16W
MF 21 20
R611 1 C888 50V
CERM
402 2 2 402 SLEEP_L_LS5_INV 1
100K 2 1000PF 603
3 VCC VDD 35 10%
+PBUS 25V
2 X7R
D
Q82 MAX1715_GND 35 38
U22 MAX1715_SKIP 38
CRITICAL CRITICAL
5%
1/16W 402
2N7002DW MAX1715 MF
402
35 SLEEP_L_LS5_INV 5 G S
SOT-363
3
QSOP
4
1 C559 1 C582
ILIM1 V+ +2_5V_MAIN 4.7UF 4.7UF
CRITICAL CRITICAL 20% 20%
33 SLEEP_L_LS5_NET 12 ILIM2 NC_15 15
6 4 NC 2 25V 2 25V
C544 1 C519 1 10 ON1 NC_23 23 NC
CERM
1206
CERM
1206
4.7UF 4.7UF
C R417
100K 2
D
Q82
2N7002DW
SOT-363
20%
25V
CERM 2
20%
25V
CERM 2
R493
4.7
11 ON2 NC_28 28 NC R479
4.7
C
33 1 2 G 1 2 25 BST2 18 1 2 38 2_5V_BOOST
19 SLEEP_L_LS5
27
S 1206 1206 38 1_5V_BOOST 38 1_5V_BST BST1 38 2_5V_BST
34 5% 5% 5%
1/16W 1 1/16W 26 DH1 CRITICAL DH2 17 1/16W
MF
402
1 C886 8 7 6 5 1 C575
MF
603
MF
603 5 6 7 8
1000PF 27 LX1 LX2 16 1 C580
10% 0.1UF
2 25V CRITICAL 20% 0.1UF CRITICAL
X7R 25V
2 CERM
24 DL1 DL2 19 20%
402 25V
Q57 603 +1_5V_MAIN 5 TON PGND 22 MAX1715_GND
2 CERM
603
Q69
+1_5V_MAIN IRF7805 IRF7805
4 38 1_5V_DH 38 2_5V_DH 4
SM 1 SM
CRITICAL OUT1 OUT2 14 CRITICAL +2_5V_MAIN
38 1_5V_2_5V_OK 7 PGOOD
L35 MAX1715_REF 9 REF SKIP 6 L45
4.7UH 3 2 1
38
1 2 3 4.7UH
1 2 2 FB2 13
38 1_5V_LX 35
38
1_5V_FB FB1 MAX1715_FB2 35 38 2_5V_LX 1 2
SM4 SM4
NO STUFF AGND THRML
1 1
R425 8 7 6 5 R4221
8 29
5 6 7 8
R616
5.11K 15.4K
1% 0 1 POSCAPS POSCAPS POSCAPS 1%
POSCAPS POSCAPS
1/16W
MF
CRITICAL 5%
1/16W R420 CRITICAL
1 1
1/16W
MF
2 402 MF 0 1 C809 1
C782 C780 C788 2 402
1 C740 1
C751 1
C745 1_5V_FB
Q56 402 2 5% Q68 2
10UF 150UF 150UF 150UF MAX1715_FB2
10UF
20%
150UF 150UF
35 38
2
IRF7811W 4 1_5V_DL
1/16W
MF
38 2_5V_DL 4
IRF7811W D33
SM
20%
6.3V 20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
35
2 402 2 CERM
38 TANT TANT
20% 20% SO-8 SO-8 1
2 6.3V
CERM 2 6.3V
TANT
2 6.3V
TANT
1
R424 D23 NO STUFF 1 C499 NO STUFF MBRS130LT3 805
TANT
SMD-1 SMD-1 SMD-1 R672
805 SMD-1 SMD-1 10K SM 1 C908 1 C907 1 10K
1% MBRS130LT3 1UF 1%
1/16W 3 2 1 0.0022UF 20%
10V
0.022UF 1 2 3 1/16W
1 10% 20% MF
MF
2 402 2 50V
CERM
XW6
SM
OMIT 2 CERM
603 2 16V
CERM 2 402
402 38 402
1 2 35 MAX1715_GND
B CHANGE R424 BACK TO 10K, 1%, AND STUFF 5.11K FOR 1.5V OPERATION +1_8V_MAIN B
CONNECTING 1_5V_FB TO GND, FORCES 1.8V OUTPUT
+3V_MAIN
1.8V SWITCHER +1_8V_MAIN LOADS
1) INTREPID PLLS
2 3 6 7
CRITICAL
+1_8V_SLEEP
R190 Q84
100K 2 4
SI6467BDQ
SLEEP 1
CONTINUOUS MODE
39 35 33 30 25 23
5%
TSSOP
+1_8V_SLEEP LOADS
1/16W
C891 1 C93 1 1
R727 R797 1
MF
402 1 5 8
1) MPC7450 - MAXBUS I/O - IF 1.8V INTERFACE
22UF 22UF 4.7M 0 1

R802 2) CPU JTAG & MaxBus Pull-ups
20% 1
16
20% 6.3V 2 5% 5% 100K
1 C893 R803 C276 1 3) CPU PLL Config Straps
1
6.3V CERM
CERM 2 1206
1/16W
MF
1/16W
MF 5% 22PF 232K 10UF 4) OPTIONAL VIDEO MEMORY (M10 PRO ONLY)
1206
2 402 2 402
SVIN PVIN 1/16W 5% 1% 20%
U58 MF 2 50V
CERM
1/16W 6.3V 2
CERM
2 402 402
MF
+1_8V_MAIN 805
LTC3412 LTC3412_PGOOD 2 402
LTC3412_RT 5 RT TSSOP CRITICAL C235
PGOOD 2 2200pF
LTC3412_RUNSS 7 RUN/SS L75 OMIT 1_8V_SLEEP_PWREN_L 2 1
1
R810 1.0UH-3.5A
CRITICAL
100K 6 LTC3412_ITH 3 ITH 38 10 1_8V_SW 1 2 +1_8V_MAIN_LX_F 1XW11 2 NO STUFF 5%
NO STUFF 50V
5%
1/16W LTC3412_SYNC 6 SYNC/MODE 11 SM JUMPER
R610 1 C887 CERM
MF D Q83 BURST MODE OPEN 100K 2 603
2 402 2N7002DW SW 14 35 SLEEP_L_LS5_INV 1 1000PF
NO STUFF 10%
SOT-363 LTC3412_VFB 4 15 5% 25V
3V_5V_OK_INV 2 G S 1
R798 VFB 1/16W 2 X7R
MF 402
1 0 THERM
3 1
R627 5% 1
R799 SGND PGND PAD
1 C894 402
1.5V/1.8V/2.5V SUPPLIES
15K 1/16W 22UF
8
12
13
17
110K
A D Q83
2N7002DW 1 C890
1%
1/16W
MF
1 C892
470PF
MF
2 402 1%
1/16W 1 C677
20%
6.3V
2 CERM
1206 NOTICE OF PROPRIETARY PROPERTY
A
SOT-363 2 402 10% MF 1
R801 22UF
3V_5V_OK 5 G S 100PF 50V
2 CERM 2 402 20%
35 33
5% LTC3412_ITH_RC LTC3412_VFB_DIV 309K 2 6.3V THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
50V 402 1% CERM
2 CERM 1/16W 1206 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
4 1 AGREES TO THE FOLLOWING
402 1 C683 R800 MF
2 402
1000PF 75K OMIT I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
5% 1% II NOT TO REPRODUCE OR COPY IT
2 25V
CERM
1/16W
MF XW1
603 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
2 402 SM
LTC3412_GND 1 2 SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.

D 051-6459 A
SCALE SHT OF
NONE 35 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GROUP SIG_NAME MAX_VIAS MAX_EXPOSED_LENGTH STUB_LENGTH NET_SPACING_TYPE NO_TEST PULSE_PARAM GROUP SIG_NAME MAX VIAS MAX EXPOSED LENGTH STUB_LENGTH NET_SPACING_TYPE PULSE PARAM
CPU_AACK_L 250.0000 10 MIL SPACING 5 8

INTREPID SYSCLK_CPU_UF 10 MIL SPACING 8
CPU_ADDR<0..31> 5 250 83 MHZ SYSCLK_CPU 4 200.0000 10 MIL SPACING

MAXBUS CPU_ARTRY_L 250.0000 10 MIL SPACING
5 8
5 8
CLOCKS INT_CPUFB_OUT 3 10 MIL SPACING
5 8
CPU_BG_L 250.0000 10 MIL SPACING 5 8 INT_CPUFB_OUT_SHORT 3 10 MIL SPACING 8
CPU_BR_L 250.0000 10 MIL SPACING 5 8 INT_CPUFB_OUT_NORM 3 10 MIL SPACING 8
CPU_CI_L 5 250.0000 5 8 INT_CPUFB_IN_NORM 3 10 MIL SPACING 8
CPU_DATA<0..31> 5 250 83 MHZ 6 8 INT_CPUFB_LONG 3 10 MIL SPACING 8
CPU_DATA<32..63> 5 250 83 MHZ 6 8 INT_CPUFB_IN 200.0000 10 MIL SPACING 8
CPU_DBG_L 5 250.0000 10 MIL SPACING 5 8 SYSCLK_DDRCLK_A0_UF 3 200.0000 10 MIL SPACING 9
CLOCK LINE CONSTRAINTS

D
CPU_DTI<0..2>
CPU_DRDY_L_UF
5 250
10 MIL SPACING
5 8 SYSCLK_DDRCLK_A0_L_UF
SYSCLK_DDRCLK_A1_UF
3
3
200.0000
200.0000
10 MIL SPACING
10 MIL SPACING
9
9
D
CPU_DRDY_L 250.0000 10 MIL SPACING 5 8 SYSCLK_DDRCLK_A1_L_UF 3 200.0000 10 MIL SPACING
DIGITAL SIGNALS
9
CPU_GBL_L 5 250.0000 5 8 SYSCLK_DDRCLK_B0_UF 3 200.0000 10 MIL SPACING 9
CPU_HIT_L 250.0000 10 MIL SPACING 5 8 SYSCLK_DDRCLK_B0_L_UF 3 200.0000 10 MIL SPACING 9
CPU_QACK_L 5 250.0000 10 MIL SPACING 5 8 SYSCLK_DDRCLK_B1_UF 3 200.0000 10 MIL SPACING 9
CPU_QREQ_L 250.0000 10 MIL SPACING 5 8 SYSCLK_DDRCLK_B1_L_UF 3 200.0000 10 MIL SPACING 9
CPU_TA_L 250.0000 10 MIL SPACING 5 8 SYSCLK_DDRCLK_A0 DDRCLK_A0 3 200.0000 10 MIL SPACING 9 11
CPU_TBST_L 5 250.0000 10 MIL SPACING 5 8 SYSCLK_DDRCLK_A0_L DDRCLK_A0 200.0000 10 MIL SPACING 9 11
CPU_TEA_L 250.0000 5 8 SYSCLK_DDRCLK_A1 DDRCLK_A1 3 200.0000 10 MIL SPACING 9 11
CPU_TS_L 250.0000 10 MIL SPACING 5 8 SYSCLK_DDRCLK_A1_L DDRCLK_A1 200.0000 10 MIL SPACING 9 11
CPU_TSIZ<0..2> 5 250 5 8 SYSCLK_DDRCLK_B0 DDRCLK_B0 3 200.0000 10 MIL SPACING 9 11
CPU_TT<0..4> 5 250 5 8 SYSCLK_DDRCLK_B0_L DDRCLK_B0 3 200.0000 10 MIL SPACING 9 11
CPU_WT_L 5 250.0000 5 8 SYSCLK_DDRCLK_B1 DDRCLK_B1 3 200.0000 10 MIL SPACING 9 11
SYSCLK_DDRCLK_B1_L DDRCLK_B1 3 200.0000 10 MIL SPACING 9 11
INT_REF_CLK_OUT 3 200.0000 10 MIL SPACING 14
INT_REF_CLK_IN 200.0000 10 MIL SPACING 14
CLK66M_GPU_AGP_UF 200.0000 10 MIL SPACING 12
CLK66M_GPU_AGP 4 200.0000 10 MIL SPACING 12 18

MEM_DATA<7..0>
GROUP 0 4 200 167 MHZ 9 10
INT_AGP_FB_OUT 200.0000 10 MIL SPACING 12
RAM_DATA_A<7..0> 4 200 167 MHZ 10 11
INT_AGP_FB_IN 4 200.0000 10 MIL SPACING 12
RAM_DATA_B<7..0> 4 200 167 MHZ 10 11
TOTAL LENGTH CONTROLLED BY SPREADSHEET CLK33M_CBUS_UF 200.0000 10 MIL SPACING 12
MEM_DQS<0> 200 9 10
CLK33M_CBUS SHOULD BE AT MOST 4 VIAS FOR CLK 6 200.0000 10 MIL SPACING 12 17
RAM_DQS_A<0> 4 200 10 11
CLK33M_AIRPORT_UF 200.0000 10 MIL SPACING 12
RAM_DQS_B<0> 4 200 10 11
CLK33M_AIRPORT SHOULD BE AT MOST 4 VIAS FOR CLK 6 200.0000 10 MIL SPACING 12 24 39
MEM_DQM<0> 4 200 9 10
CLK33M_USB2_UF 200.0000 10 MIL SPACING 12
RAM_DQM_A<0> 4 200
C RAM_DQM_B<0> 4 200
10 11
10 11
CLK33M_USB2
INT_PCI_FB_OUT
SHOULD BE AT MOST 4 VIAS FOR CLK 6 200.0000
200.0000
10 MIL SPACING
10 MIL SPACING
12 26
12
C
MEM_DATA<15..8>
GROUP 1 4 200 167 MHZ 9 10
INT_PCI_FB_IN 3 200.0000 10 MIL SPACING 12
RAM_DATA_A<15..8> 4 200 167 MHZ 10 11
RAM_DATA_B<15..8> 4 200 167 MHZ 10 11

TOTAL LENGTH CONTROLLED BY SPREADSHEET
MEM_DQS<1> 4 200 9 10
RAM_DQS_A<1> 4 200 10 11
RAM_DQS_B<1> 4 200 10 11
MEM_DQM<1> 200 9 10
RAM_DQM_A<1> GPU_CLK27M_OUT 10 MIL SPACING

4 200
RAM_DQM_B<1> 4 200
10 11
10 11
MAP31 GPU_CLK27M_UF 10 MIL SPACING
MEM_DATA<31..16> GPU_SSCLK_UF 10 MIL SPACING
GROUP 2/3 4 200 167 MHZ 9 10
GPU_SSCLK_IN 10 MIL SPACING
RAM_DATA_A<31..16> 4 200 167 MHZ 10 11
RAM_DATA_B<31..16> GPU_FBCLK0 10 MIL SPACING

4 200 167 MHZ 10 11
TOTAL LENGTH CONTROLLED BY SPREADSHEET GPU_FBCLK0_L 10 MIL SPACING
MEM_DQS<3..2> 4 200 167 MHZ 9 10
RAM_DQS_A<3..2> GPU_FBCLK1 10 MIL SPACING

4 200 167 MHZ 10 11
GPU_FBCLK1_L
DDR RAM_DQS_B<3..2> 4 200 167 MHZ 10 11
10 MIL SPACING
GPU_DVO_CLKP
RAM MEM_DQM<3..2> 4 200 167 MHZ 9 10
10 MIL SPACING 19 20
RAM_DQM_A<3..2> 4 200 167 MHZ

RAM_DQM_B<3..2> 4 200 167 MHZ
10 11
10 11
CRYSTALS CLK27M_GPU_XOUT 10 MIL SPACING
CLK27M_XTAL_IN 10 MIL SPACING
MEM_DATA<47..32>
GROUP 4/5 4 200 167 MHZ 9 10
CLK27M_GPU_XIN 10 MIL SPACING
RAM_DATA_A<47..32> 4 200 167 MHZ 10 11
CLK18M_INT_XIN 10 MIL SPACING 14
RAM_DATA_B<47..32> 4 200 167 MHZ 10 11
TOTAL LENGTH CONTROLLED BY SPREADSHEET CLK18M_INT_XOUT 10 MIL SPACING 14
MEM_DQS<5..4> 4 200 167 MHZ 9 10
CLK18M_XTAL_IN 10 MIL SPACING 14
RAM_DQS_A<5..4> 4 200 167 MHZ 10 11
CLK18M_INT_EXT 10 MIL SPACING 14
RAM_DQS_B<5..4> 4 200 167 MHZ 10 11
CLK25M_ENET_XIN 10 MIL SPACING 27
MEM_DQM<5..4> 4 200 167 MHZ 9 10
B RAM_DQM_A<5..4>
RAM_DQM_B<5..4>
4
4
200
200
167 MHZ
167 MHZ
10 11
10 11
CLK25M_ENET_XOUT
NEC_XT1
10 MIL SPACING
10 MIL SPACING
27
26
B
NEC_XT2 THERE’S ANOTHER 280MIL LEG 10 MIL SPACING 26
MEM_DATA<55..48>
GROUP 6 4 200 167 MHZ 9 10
RAM_DATA_A<55..48> 4 200 167 MHZ 10 11 SND_SCLK 7 200.0000 10 MIL SPACING 14 25 39
RAM_DATA_B<55..48> 4 200
167 MHZ 10 11 SOUND SND_CLKOUT 200.0000 10 MIL SPACING 14 25 39
MEM_DQS<6> 4 200 9 10
RAM_DQS_A<6> CLKENET_PHY_RX 200.0000 27

200
RAM_DQS_B<6> 4 200
10 11
10 11
ETHERNET CLKENET_LINK_RX 3 200.0000 10 MIL SPACING 13 27
MEM_DQM<6> 200 9 10
MARVELL CLKENET_PHY_GBE_REF 200.0000 27
RAM_DQM_A<6> CLKENET_LINK_GBE_REF 3 200.0000 10 MIL SPACING 13 27

4 200 10 11
RAM_DQM_B<6> CLKENET_PHY_TX 200.0000 27

4 200 10 11
MEM_DATA<63..56> CLKENET_LINK_TX 5 200.0000 10 MIL SPACING 13 27

GROUP 7 4 200 167 MHZ 9 10
CLKENET_LINK_GTX 200.0000 13
RAM_DATA_A<63..56> 4 200 167 MHZ 10 11
RAM_DATA_B<63..56> CLKENET_PHY_GTX 3 200.0000 10 MIL SPACING 13 27

4 200 167 MHZ 10 11
MEM_DQS<7> 4 200 9 10
CLKFW_PHY_PCLK 200.0000
RAM_DQS_A<7> 200 10 11
FIREWIRE CLKFW_LINK_PCLK 3 200.0000 10 MIL SPACING
28
13 28
RAM_DQS_B<7> 200 10 11
MEM_DQM<7> CLKFW_PHY_LCLK 3 200.0000 10 MIL SPACING 13 28

4 200 9 10
RAM_DQM_A<7> CLKFW_LINK_LCLK 200.0000 13

4 200 10 11
RAM_DQM_B<7> FW_XI 200.0000 10 MIL SPACING 28

4 200 10 11
MEM_ADDR<12..0> FW_OSC 200.0000 10 MIL SPACING 28

ADDR 4 83 MHZ 9
RAM_ADDR<12..0> 6 200 9 11
MEM_BA<1..0> 4 9
RAM_BA<1..0> 6 200 9 11
MEM_CS_L<3..0> 4 9
CONTROL RAM_CS_L<3..0> 6 200 9 11
SIGNAL CONSTRAINTS - PAGE 1
A MEM_CKE<3..0> 4 9
A
RAM_CKE<3..0> 6 200 9 11
MEM_RAS_L 4 9
RAM_RAS_L 200.0000 9 11
MEM_CAS_L 4 9
RAM_CAS_L 200.0000 9 11
MEM_WE_L 4 9
RAM_WE_L 200.0000 9 11
MEM_MUXSEL_H<1..0> 3 9 10
MEM_MUXSEL_L<1..0>
RAM_MUXSEL_H
3
5
9 10

D 051-6459 A
RAM_MUXSEL_L SCALE SHT OF
5 10
NONE 36 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GROUP SIG_NAME DELAY_RULE MAX_VIAS MAX_EXPOSED_LENGTH STUB_LENGTH NET_SPACING_TYPE NO_TEST PULSE_PARAM Differential Signals
GROUP SIG_NAME DIFFERENTIAL_PAIR MAX_EXPOSED_LENGTH NET_SPACING_TYPE MAX_VIAS
AGP_AD<15..0>
AGP 5 100 66 MHz 12 18
MDI_M<0> ENET_MDI0 27
AGP_CBE<1..0> 5 100 66 MHz 12 18 ETHERNET
AGP BYTES 0-1
MDI_P<0> ENET_MDI0 27
Digital Signals (cont’d)
AGP_AD_STB<0> 4 100 8 MIL SPACING 12 18
MDI_M<1> ENET_MDI1 SPACING DELETED BECAUSE 27
AGP_AD_STB_L<0> 4 100 8 MIL SPACING 12 18
MDI_P<1> ENET_MDI1 OF PHYSICAL CONSTRAINTS 27
AGP BYTES 2-3 AGP_AD<31..16> 5 100 66 MHz 12 18
MDI_M<2> ENET_MDI2 AROUND MARVELL PHY 27
AGP_CBE<3..2> 5 100 66 MHz 12 18
AGP_AD_STB<1> MDI_P<2> ENET_MDI2 27

4 100 8 MIL SPACING 12 18
AGP_AD_STB_L<1> MDI_M<3> ENET_MDI3 27

100 8 MIL SPACING 12 18
AGP_SBA<7..0> MDI_P<3> ENET_MDI3 27

AGP SIDEBAND 5 100 66 MHz 12 18
RJ45_DN<0> RJ45_DP0 10 MIL SPACING 27 39
D
AGP_SB_STB
AGP_SB_STB_L 4
100.0000
100.0000
8 MIL SPACING
8 MIL SPACING
12 18
12 18
RJ45_DP<0> RJ45_DP0 10 MIL SPACING 27 39 D
AGP_FRAME_L RJ45_DN<1> RJ45_DP1 10 MIL SPACING 27 39
AGP CONTROL 250.0000 12 18
AGP_IRDY_L RJ45_DP<1> RJ45_DP1 10 MIL SPACING 27 39

250.0000 12 18
AGP_TRDY_L RJ45_DN<2> RJ45_DP2 10 MIL SPACING 27 39

6 250.0000 12 18
AGP_DEVSEL_L RJ45_DP<2> RJ45_DP2 10 MIL SPACING 27 39

250.0000 12 18
AGP_STOP_L RJ45_DN<3> RJ45_DP3 10 MIL SPACING 27 39

6 250.0000 12 18
AGP_PAR RJ45_DP<3> RJ45_DP3 10 MIL SPACING 27 39

6 250.0000
AGP_REQ_L 285.0000
12 18
12 18 FIREWIRE
FW_TPA0N FW_TPA0
MIN_LINE_WIDTH=3.4
INTERNAL LAYER
MIN_LINE_WIDTH=3.4
AGP_GNT_L FW_TPA0P FW_TPA0 10 MIL SPACING 28 29
250.0000 12 18
FW_TPB0N FW_TPB0
MIN_LINE_WIDTH=3.4
ER = 4.3 (DIELECTRIC CONSTANT)
AGP_RBF_L 250.0000 12 18
MIN_LINE_WIDTH=3.4
DVO GPU_DVOD<0..11> 5 250 19 20
FW_TPB0P FW_TPB0 10 MIL SPACING
MIN_LINE_WIDTH=3.4
28 29 W = 4MIL (TRACE WIDTH)
GPU_DVO_HSYNC FW_TPI0N FW_TPI0 10 MIL SPACING
19 20
FW_TPI0P FW_TPI0
MIN_LINE_WIDTH=3.4
10 MIL SPACING
B = 12.2MIL (DIST BETW 2 GND PLANES)
GPU_DVO_VSYNC 19 20
MIN_LINE_WIDTH=3.4
FW_TPO0N FW_TPO0 10 MIL SPACING
MIN_LINE_WIDTH=3.4 T = 0.7MIL (TRACE THICKNESS)
PCI_AD<31..0> MIN_DAISY_CHAIN 33 MHz 9 12 17 24 26 39 FW_TPO0P FW_TPO0 10 MIL SPACING
PCI PCI_CBE<3..0> MIN_DAISY_CHAIN 33 MHz 12 17 24 26 39 FW_TPA1N FW_TPA1 500.0000
MIN_LINE_WIDTH=3.4
S = 10MIL (SEPERATION OF DIFF TRACES)
MIN_LINE_WIDTH=3.4
PCI_FRAME_L FW_TPA1P
MIN_DAISY_CHAIN 12 17 24 26 39 FW_TPA1 500.0000 10 MIL SPACING
MIN_LINE_WIDTH=3.4
28 29
ZSINGLE = 51.57OHM
PCI_IRDY_L MIN_DAISY_CHAIN 12 17 24 26 39 FW_TPB1N FW_TPB1 500.0000 10 MIL SPACING 28 29
PCI_TRDY_L MIN_DAISY_CHAIN 12 17 24 26 39 FW_TPB1P FW_TPB1 500.0000

MIN_LINE_WIDTH=3.4
ZDIFF = 99.8OHM
MIN_LINE_WIDTH=3.4
PCI_DEVSEL_L MIN_DAISY_CHAIN 12 17 24 26 39 FW_TPI1N FW_TPI1 10 MIL SPACING 29 39
MIN_LINE_WIDTH=3.4
PCI_STOP_L MIN_DAISY_CHAIN 12 17 24 26 39 FW_TPI1P FW_TPI1 10 MIL SPACING 29 39
MIN_LINE_WIDTH=3.4
PCI_PAR MIN_DAISY_CHAIN 12 17 24 26 39 FW_TPO1N FW_TPO1 10 MIL SPACING 29 39
MIN_LINE_WIDTH=3.4
FW_TPO1P FW_TPO1 10 MIL SPACING 29 39
ULTRA ATA-100 UIDE_DATA<15..8> 200
NEED TO MATCH DELAY TO 250
100 MHZ 13 24 CLKLVDS_LN CLKLVDS_L 10 MIL SPACING 4 19 22 39
FOR FIREWIRE
UIDE_DATA<7> 200 13 24
LVDS CLKLVDS_LP CLKLVDS_L 10 MIL SPACING 4 19 22 39
UIDE_DATA<6..0> 200 100 MHZ 13 24
LOWER
LVDS_L0N LVDS_L0 10 MIL SPACING 19 22 39
UIDE_ADDR<2..0> 200 100 MHZ W = 3.4MIL (TRACE WIDTH)
C UIDE_RST_L 200.0000
13 24
13 24
LVDS_L0P
LVDS_L1N
LVDS_L0
LVDS_L1
10 MIL SPACING
10 MIL SPACING
19 22 39
19 22 39
C
UIDE_DIOW_L 200.0000 13 24 LVDS_L1P LVDS_L1 10 MIL SPACING 19 22 39
UIDE_DIOR_L 10 MIL SPACING 200.0000 13 24 LVDS_L2N
UIDE_DMACK_L 200.0000 13 24
LVDS_L2 10 MIL SPACING 19 22 39
T = 0.7MIL (TRACE THICKNESS)
LVDS_L2P LVDS_L2 10 MIL SPACING 19 22 39
UIDE_CS0_L 200.0000 13 24 UPPER CLKLVDS_UN CLKLVDS_U 10 MIL SPACING 4 19 22 39
S = 10MIL (SEPERATION OF DIFF TRACES)
UIDE_CS1_L 200.0000 13 24 CLKLVDS_UP
UIDE_DMARQ 200.0000 13
CLKLVDS_U 10 MIL SPACING 4 19 22 39
ZSINGLE = 53.37OHM
LVDS_U0N LVDS_U0 10 MIL SPACING 19 22 39
UIDE_IOCHRDY 10 MIL SPACING 200.0000 13 24 LVDS_U0P LVDS_U0 10 MIL SPACING 19 22 39
ZDIFF = 107.17OHM
UIDE_INTRQ 200.0000 13 LVDS_U1N LVDS_U1 10 MIL SPACING 19 22 39
HD_DATA<15..0> 5 200 100 MHZ 24 LVDS_U1P
TOTAL UIDE+HD SKEW <500MIL LVDS_U1 10 MIL SPACING 19 22 39
HD_ADDR<2..0> 5 200 100 MHZ 24 LVDS_U2N LVDS_U2 10 MIL SPACING 19 22 39
HD_RESET_L 5 200.0000 24 LVDS_U2P LVDS_U2 10 MIL SPACING 19 22 39
HD_DIOW_L 5 200.0000 24
TMDS TMDS_CONN_CLKN CLKCONN_TMDS 10 MIL SPACING 4 22 39
HD_DIOR_L 5 10 MIL SPACING 200.0000 24 TMDS_CONN_CLKP CLKCONN_TMDS 10 MIL SPACING 4 22 39
HD_DMACK_L 5 200.0000 24 TMDS_CLKN CLKTMDS 10 MIL SPACING 4 20 22
HD_CS0_L 5 200.0000 24 TMDS_CLKP CLKTMDS 10 MIL SPACING 4 20 22
HD_CS1_L 5 200.0000 24 TMDS_DN<0> TMDS_D0 10 MIL SPACING 20 22 39
HD_DMARQ 200.0000 13 24 TMDS_DP<0> TMDS_D0 10 MIL SPACING 20 22 39
HD_IOCHRDY 5 10 MIL SPACING 200.0000 24 TMDS_DN<1> TMDS_D1 10 MIL SPACING 20 22 39
HD_INTRQ 5 13 24 TMDS_DP<1> TMDS_D1 10 MIL SPACING 20 22 39
EIDE_DATA<15..0> TMDS_DN<2> TMDS_D2 10 MIL SPACING 20 22 39

EIDE EIDE_ADDR<2..0>
33 MHZ
33 MHZ
13 24
13 24
TMDS_DP<2> TMDS_D2 10 MIL SPACING 20 22 39
INTREPID EIDE_CS0_L 13 24 USB NEC_USB_DAM NEC_USB_DA MIN_LINE_WIDTH=5 10 MIL SPACING 26
EIDE_CS1_L NEC_USB_DAP NEC_USB_DA MIN_LINE_WIDTH=5 10 MIL SPACING 26

13 24
EIDE_RD_L USB_DEM USB_DE 5 MIL SPACING 14

13 24
USB_DEP USB_DE 5 MIL SPACING 14
B EIDE_WR_L
EIDE_IOCHRDY
13 24
13 24
NEC_USB_DBM NEC_USB_DB MIN_LINE_WIDTH=5 10 MIL SPACING 26
INTERNAL LAYER (USB1.1/USB 2.0) B
EIDE_INT NEC_USB_DBP NEC_USB_DB MIN_LINE_WIDTH=5 10 MIL SPACING 26
13 24
USB_DFM USB_DF 5 MIL SPACING 14
EIDE_RST_L 13 24
EIDE_DMACK_L 13 24
USB_DFP USB_DF 5 MIL SPACING 14 W = 4MIL(USB 1.1)/ 5MIL(USB 2.0) (TRACE WIDTH)
EIDE_DMARQ BT_USB_DM BT_USB_D 5 MIL SPACING 14 24 39
13 24
BT_USB_DP BT_USB_D 5 MIL SPACING 14 24 39
EIDE_OPTICAL_DATA<15..0> 33 MHZ 24 39
OPTICAL NEC_USB_RSDM1
EIDE_OPTICAL_ADDR<2..0> 33 MHZ 24 39
NEC_USB_RSD1 MIN_LINE_WIDTH=5 10 MIL SPACING 26
T = 0.7MIL (TRACE THICKNESS)
EIDE_OPTICAL_CS0_L NEC_USB_RSDP1 NEC_USB_RSD1 MIN_LINE_WIDTH=5 10 MIL SPACING 26
24 39
EIDE_OPTICAL_CS1_L 24 39
NEC_USB_RSDM2 NEC_USB_RSD2 MIN_LINE_WIDTH=5 10 MIL SPACING 26
S = 5MIL (USB 1.1) (SEPERATION OF DIFF TRACES)
EIDE_OPTICAL_RD_L 24 39
NEC_USB_RSDP2 NEC_USB_RSD2 MIN_LINE_WIDTH=5 10 MIL SPACING 26 S = 10MIL (USB 2.0) (SEPERATION OF DIFF TRACES)
EIDE_OPTICAL_WR_L MODEM_USB_DM MODEM_USB_D 5 MIL SPACING 14 25 39
24 39
MODEM_USB_DP MODEM_USB_D 5 MIL SPACING 14 25 39
ZSINGLE = 51.5OHM (USB 1.1)/ 46.2OHM (USB 2.0)
EIDE_OPTICAL_IOCHRDY 24 39
EIDE_OPTICAL_INT 24 39
LEFT_USB_DM LEFT_USB MIN_LINE_WIDTH=5 10 MIL SPACING 24 26 39
ZDIFF = 89.3OHM (USB 1.1)/ 89.4OHM (USB 2.0)
EIDE_OPTICAL_RST_L LEFT_USB_DP LEFT_USB MIN_LINE_WIDTH=5 10 MIL SPACING 24 26 39
24 39
EIDE_OPTICAL_DMAACK_L RIGHT_USB_DM RIGHT_USB MIN_LINE_WIDTH=5 10 MIL SPACING 26 32 39

24 39
EIDE_OPTICAL_DMA_RQ RIGHT_USB_DP RIGHT_USB MIN_LINE_WIDTH=5 10 MIL SPACING 26 32 39

24 39
POWER 1772_CSSN 1772_CSS 31

ENET_LINK_RXD<7..0> 5 13 27
ETHERNET MII SUPPLIES
ENET_RX_DV 1772_CSSP 1772_CSS 31
13 27
ENET_RX_ER 1772_CSIN 1772_CSI 31

13 27
ENET_PHY_TXD<7..0> 1772_CSIP 1772_CSI 31

5 13 27
ENET_LINK_TXD<7..0> 3V_SNSM 3V_SNS 33

13
ENET_PHY_TX_ER 3V_SNSP 3V_SNS 33

5 13 27
ENET_LINK_TX_ER 5V_SNSM 5V_SNS 33

13
ENET_PHY_TX_EN 5V_SNSP 5V_SNS 33

5
ENET_LINK_TX_EN
13 27
THERMOSTAT THERM1_DM THERM1 25
SIGNAL CONSTRAINTS - PAGE 2
A ENET_MDIO
13
13 27
THERM1_DP THERM1 25
A
ENET_MDC THERM2_DM THERM2 25
13 27
ENET_COL THERM2_DP THERM2 25

13 27 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
THERM1_M_DM THERM1_MAIN PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
ENET_CRS 13 27 AGREES TO THE FOLLOWING
THERM1_M_DP THERM1_MAIN I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
FIREWIRE MII FW_LINK_DATA<7..0> 5 13 28 THERM2_M_DM THERM2_MAIN II NOT TO REPRODUCE OR COPY IT
FW_PHY_DATA<7..0> 5 28 THERM2_M_DP THERM2_MAIN III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
FW_LINK_CNTL<1..0> 13 28 THERM1_A_DM THERM1_ALT 25
FW_PHY_CNTL<1..0> 28 THERM1_A_DP SIZE DRAWING NUMBER REV.
THERM1_ALT 25
FW_LINK_LREQ
FW_PHY_LREQ
13
13 28
THERM2_A_DM
THERM2_A_DP
THERM2_ALT
THERM2_ALT
25

D 051-6459 A
FW_PINT 13 28 SCALE SHT OF
NONE 37 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
POWER NET CONSTRAINTS GROUP SIG_NAME VOLTAGE MIN_LINE_WIDTH MIN_NECK_WIDTH GROUP SIG_NAME
1625_VIN
VOLTAGE
VOLTAGE=24V
MIN_LINE_WIDTH
MIN_LINE_WIDTH=10
MIN_NECK_WIDTH
32
GROUP SIG_NAME VOLTAGE MIN_LINE_WIDTH MIN_NECK_WIDTH CPU CPU_VCORE_SLEEP VOLTAGE=1.4V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 5 34 39
LTC1625 1625_VSW VOLTAGE=12.8V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 32
CPU_AVDD VOLTAGE=1.4V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 5
14V SWITCHER 1625_EXTVCC
MAXBUS_SLEEP VOLTAGE=1.8V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 5 7 8 15 16 23 34
VOLTAGE=5V MIN_LINE_WIDTH=10 32
+24V_PBUS VOLTAGE=24V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 39 1625_INTVCC VOLTAGE=5V MIN_LINE_WIDTH=10 32

MAIN/SLEEP +BATT VOLTAGE=12.6V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
DDR RAM DDR_VREF VOLTAGE=1.25V MIN_LINE_WIDTH=10 11
1625_SGND VOLTAGE=0V MIN_LINE_WIDTH=10 32
+2_5V_INTREPID VOLTAGE=2.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 9 10 15 16
+PBUS VOLTAGE=12.8V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 39 INTREPID +3V_INTREPID_USB VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 14
1V20_REF VOLTAGE=1.2V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 31 32
+5V_MAIN VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 PLLS

+1_5V_INTREPID_PLL VOLTAGE=1.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 8 12 14
+5V_SLEEP VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
+3V_MAIN VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
+1_5V_INTREPID_PLL1 VOLTAGE=1.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=6 14
LTC3707 3707_INTVCC VOLTAGE=5V MIN_LINE_WIDTH=10 MIN_NECK_WIDTH=10 33
+1_5V_INTREPID_PLL2 VOLTAGE=1.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=6 5V_SW VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10

+3V_SLEEP VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=6
14
5V SWITCHER 33
D +3V_PMU VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 39

+1_5V_INTREPID_PLL3
+1_5V_INTREPID_PLL4
VOLTAGE=1.5V
VOLTAGE=1.5V
MIN_LINE_WIDTH=15
MIN_LINE_WIDTH=15
MIN_NECK_WIDTH=6
MIN_NECK_WIDTH=5
14
14
5V_RSNS VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 33
D
+2_5V_MAIN VOLTAGE=2.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
+2_5V_SLEEP
+1_5V_INTREPID_PLL5 VOLTAGE=1.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=5 12 3V SWITCHER 3V_SW VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 33
VOLTAGE=2.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
+1_5V_INTREPID_PLL6 VOLTAGE=1.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=6 12 3V_RSNS VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 33
+1_8V_MAIN VOLTAGE=1.8V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=6 39
+1_5V_INTREPID_PLL7 VOLTAGE=1.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=6 8 3707_SGND VOLTAGE=0V MIN_LINE_WIDTH=10 33
+1_8V_SLEEP VOLTAGE=1.8V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
+1_5V_INTREPID_PLL8 VOLTAGE=1.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=6 14
+1_5V_MAIN VOLTAGE=1.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
+1_5V_SLEEP VOLTAGE=1.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 REFERENCE INT_MEM_VREF VOLTAGE=1.25V MIN_LINE_WIDTH=10 9
MAX1715 2_5V_LX VOLTAGE=2.5V MIN_LINE_WIDTH=50 MIN_NECK_WIDTH=10 35
+1_5V_LDO INT_AGP_VREF VOLTAGE=1.25V MIN_LINE_WIDTH=10 12 18

2.5V SWITCHER 2_5V_BST VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 35
VOLTAGE=1.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 35
+1_5V_SLEEP_VIN INT_MEM_REF_H VOLTAGE=0V MIN_LINE_WIDTH=10 9 2_5V_BOOST VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 35

UIDE_REF VOLTAGE=0V MIN_LINE_WIDTH=8 13 2_5V_DH VOLTAGE=2.5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 35
MIN_NECK_WIDTH REDUCED FOR TESTPOINTS 2_5V_DL VOLTAGE=2.5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10
ADAPTER +ADAPTER VOLTAGE=24V MIN_LINE_WIDTH=50 MIN_NECK_WIDTH=10 31 32
CARDBUS +VCC_CBUS_SW VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 17
35
+VPP_CBUS_SW VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 17

+ADAPTER_SW VOLTAGE=24V MIN_LINE_WIDTH=50 MIN_NECK_WIDTH=10 31
+ADAPTER_SENSE GPU_VCORE VOLTAGE=1.2V MIN_LINE_WIDTH=30 MIN_NECK_WIDTH=10 18 19 39

VOLTAGE=24V MIN_LINE_WIDTH=50 MIN_NECK_WIDTH=10 31
ATI M10 +GPU_MEM VOLTAGE=2.5V MIN_LINE_WIDTH=30 MIN_NECK_WIDTH=10 18 21
1.5V SWITCHER 1_5V_FB VOLTAGE=1.5V MIN_LINE_WIDTH=8 35
1_5V_LX VOLTAGE=1.5V MIN_LINE_WIDTH=50 MIN_NECK_WIDTH=10 35

+BATT_POS +3V_GPU VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 12 18 19 21
VOLTAGE=16.8V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
BATTERY BATT_NEG VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
31 39
31 39
+3V_GPU_FLT VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=8 21
1_5V_BST VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 35
1_5V_BOOST VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 35

CHARGER 1772_DCIN VOLTAGE=24V MIN_LINE_WIDTH=10 31
+1_5V_AGP VOLTAGE=1.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 12 15 16 18 19 21
1_5V_DH VOLTAGE=1.5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 35
1772_LX GPU_MEM_IO VOLTAGE=2.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
VOLTAGE=12.6V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 31 1_5V_DL VOLTAGE=1.5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 35
+BATT_14V_FUSE GPU_MEM_IO_FLT VOLTAGE=2.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 21
VOLTAGE=12.6V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 31 1_5V_ILIM MIN_LINE_WIDTH=8
+BATT_24V_FUSE +GPU_MEMCORE VOLTAGE=2.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 21
CONTROL 35
VOLTAGE=12.6V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 31 2_5V_ILIM MIN_LINE_WIDTH=8 35
+BATT_RSNS +1_8V_GPU VOLTAGE=1.8V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 18 19 20 21
VOLTAGE=12.6V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 31 MAX1715_TON MIN_LINE_WIDTH=8 35
+BATT_VSNS +2_5V_GPU_PNLIO VOLTAGE=2.5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 21
VOLTAGE=12.6V MIN_LINE_WIDTH=10 MIN_NECK_WIDTH=10 31 MAX1715_SKIP MIN_LINE_WIDTH=8 35
1772_LDO +1_8V_ATI_PVDD VOLTAGE=1.8V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 19 21
VOLTAGE=5.4V MIN_LINE_WIDTH=10 31 MAX1715_REF VOLTAGE=2.0V MIN_LINE_WIDTH=8 35
1772_DLOV +1_5V_AGP_GPU VOLTAGE=1.5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 21
VOLTAGE=5.4V MIN_LINE_WIDTH=10 31 MAX1715_VCC VOLTAGE=5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 35
1772_GND +1_5V_GPU_VDD15 VOLTAGE=1.5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 19
VOLTAGE=0V MIN_LINE_WIDTH=10 31 MAX1715_GND VOLTAGE=0V MIN_LINE_WIDTH=30 MIN_NECK_WIDTH=10 35
+1_8V_GPU_PLL VOLTAGE=1.8V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 21
MIN_NECK_WIDTH=10
C PMU +ADAPTER_ILIM VOLTAGE=24V MIN_LINE_WIDTH=10 32
I331
I332
+1_8V_GPU_VDDDI
GPU_VCORE_VDDCI
VOLTAGE=1.8V
VOLTAGE=1.2V
MIN_LINE_WIDTH=15
MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10
21
18
C
+2_5V_GPU_A2VDD VOLTAGE=2.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10
+ADAPTER_OR_BATT VOLTAGE=24V MIN_LINE_WIDTH=10 32 I336
+1_8V_GPU_AVDD VOLTAGE=1.8V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10
21
21
MAX1717 VCORE_VCC VOLTAGE=5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 34
+4_85V_RAW VOLTAGE=4.85V MIN_LINE_WIDTH=10 30 32 I334 VCORE_LX VOLTAGE=1.4V MIN_LINE_WIDTH=200 MIN_NECK_WIDTH=10 34

+1_8V_GPU_PNLPLL VOLTAGE=1.8V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 21
+4_6V_BU VOLTAGE=4.6V MIN_LINE_WIDTH=10 32 33 I333 VCORE_DH MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 34
+1_8V_GPU_PNLIO VOLTAGE=1.8V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 21
+4_85V_ESR VOLTAGE=4.85V MIN_LINE_WIDTH=10 32 I335 VCORE_DL MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 34
+GPU_MCLK VOLTAGE=2.5V MIN_LINE_WIDTH=10 MIN_NECK_WIDTH=10 21
+3V_PMU_ESR VOLTAGE=3.3V MIN_LINE_WIDTH=10 32 I337 VCORE_BOOST VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 34
+1_8V_GPU_AVDDQ VOLTAGE=1.8V MIN_LINE_WIDTH=10 MIN_NECK_WIDTH=10 21
+3V_PMU_AVCC VOLTAGE=3.3V MIN_LINE_WIDTH=10 25 30 I338 VCORE_BST VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 34
+1_8V_GPU_MEMPLL VOLTAGE=1.8V MIN_LINE_WIDTH=10 MIN_NECK_WIDTH=10 21
I341 VCORE_ILIM MIN_LINE_WIDTH=8 34
MISC I340
+3V_ATI_OSC_SLEEP VOLTAGE=3.3V MIN_LINE_WIDTH=10 MIN_NECK_WIDTH=10 18 VCORE_REF MIN_LINE_WIDTH=8 34
+5V_HD_SLEEP VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
HD 24 33
I339
+3V_ATI_SS VOLTAGE=3.3V MIN_LINE_WIDTH=10 MIN_NECK_WIDTH=10 18 VCORE_TON
+HD_LOGIC_SLEEP VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 24
VOLTAGE=5V MIN_LINE_WIDTH=8 34
+GPU_VDD15_UF VOLTAGE=1.5V MIN_LINE_WIDTH=20 19
I342 VCORE_CC MIN_LINE_WIDTH=8 34
+2_5V_SLEEP_NECK1 VOLTAGE=1.8V MIN_LINE_WIDTH=10 19
+5V_TPAD_SLEEP VOLTAGE=5V MIN_LINE_WIDTH=10 23 39 I343
VCORE_FB
TRACKPAD VOLTAGE=1.8V MIN_LINE_WIDTH=10 VOLTAGE=1.4V MIN_LINE_WIDTH=8 34 39
I347
+3V_SLEEP_NECK 21
VCORE_TIME MIN_LINE_WIDTH=8 34
+1_5V_AGP_NECK VOLTAGE=1.8V MIN_LINE_WIDTH=10 19
I345
VCORE_VGATE MIN_LINE_WIDTH=8 14 34
+3V_HALL_EFFECT VOLTAGE=3.3V MIN_LINE_WIDTH=10 23 39 +1_8V_PVDD_NECK VOLTAGE=2.5V MIN_LINE_WIDTH=10 19
I346
HALL EFFECT GPU_VCORE_NECK VOLTAGE=1.8V MIN_LINE_WIDTH=10
VCORE_GND VOLTAGE=0V MIN_LINE_WIDTH=30 34
I344 19
VCORE_GNDSNS VOLTAGE=0V MIN_LINE_WIDTH=8 34
+12_8V_INV VOLTAGE=12.8V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 +GPU_VDD15_NECK VOLTAGE=1.8V MIN_LINE_WIDTH=10
VIDEO 22 39 I348 19
VCORE_SNS VOLTAGE=1.4V MIN_LINE_WIDTH=8 34
+5V_INV_UF_SW VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 22 +2_5V_SLEEP_NECK2 VOLTAGE=3.3V MIN_LINE_WIDTH=10 21
I351
VCORE_GNDDIV VOLTAGE=0V MIN_LINE_WIDTH=8 34
+5V_INV_SW VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 22 39 +1_8V_SLEEP_NECK VOLTAGE=3.3V MIN_LINE_WIDTH=10 21
I349
+5V_DDC_SLEEP VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 22 39 +1_5V_SLEEP_NECK VOLTAGE=1.5V MIN_LINE_WIDTH=10 21
I350
+5V_DDC_SLEEP_UF VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 22 I352
+2_5V_GPU VOLTAGE=2.5V MIN_LINE_WIDTH=10 MIN_NECK_WIDTH=10 21 LTC1778 1778_VIN VOLTAGE=14V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 19
1778_VCC VOLTAGE=5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 19

+3V_LCD VOLTAGE=3.3V MIN_LINE_WIDTH=12 MIN_NECK_WIDTH=10 22
1778_GND VOLTAGE=0V MIN_LINE_WIDTH=30 MIN_NECK_WIDTH=10 19
+3V_LCD_SW VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 22
GPU_TV_GND1 VOLTAGE=0V MIN_LINE_WIDTH=25 22

SILICON I353
+3V_SI_PLLVCC VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=8 20 1778_BST VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 19
GPU_TV_GND2 VOLTAGE=0V MIN_LINE_WIDTH=25 22

IMIAGE I355
+3V_SI_AVCC VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=8 20 1778_BST_RC VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 19
I354
+3V_SI_VCC VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=8 20 1778_TG MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 19
TV_GND1 VOLTAGE=0V MIN_LINE_WIDTH=25 22 39
1778_BG MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 19
B TV_GND2 VOLTAGE=0V MIN_LINE_WIDTH=25 22 39

GPU_VCORE_SW VOLTAGE=1.2V MIN_LINE_WIDTH=50 MIN_NECK_WIDTH=10 19 B
1778_ION MIN_LINE_WIDTH=8 19
KB LED KBD_LED1_OUT VOLTAGE=0V MIN_LINE_WIDTH=10 23 39 1778_ITH MIN_LINE_WIDTH=8 19
KBD_LED2_OUT VOLTAGE=0V MIN_LINE_WIDTH=10 23 39 1778_ITH_RC MIN_LINE_WIDTH=8 19
FAN GND FANL_GND VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 25 39

88E1111 +2_5V_MARVELL VOLTAGE=2.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 27 1_5V_2_5V_OK MIN_LINE_WIDTH=8 35
+2_5V_MARVELL_AVDD VOLTAGE=2.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=8 27 1778_VFB MIN_LINE_WIDTH=8 19 39
FANR_GND VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 25 39 +1_0V_MARVELL VOLTAGE=1.0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=8 27 1778_FCB MIN_LINE_WIDTH=8 19
SOUND +5V_SOUND_SLEEP
LTC3405_SW VOLTAGE=1.0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=8 27 1778_VRNG MIN_LINE_WIDTH=8 19
VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
LM2594_IN VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 28
SND_AGND VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=15 25
+3V_FW_ESD_ILIM VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 29 LTC3411_VCC VOLTAGE=3.3V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10
FW +3V_FW_ESD VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 29
LTC3411 LTC3411_GND VOLTAGE=0V MIN_LINE_WIDTH=30 MIN_NECK_WIDTH=10
+FW_FUSE VOLTAGE=12.8V MIN_LINE_WIDTH=100 MIN_NECK_WIDTH=12 29 1_8V_SW VOLTAGE=1.8V MIN_LINE_WIDTH=30 MIN_NECK_WIDTH=10 35
+FW_SW VOLTAGE=12.8V MIN_LINE_WIDTH=100 MIN_NECK_WIDTH=12 29 1_8V_VFB MIN_LINE_WIDTH=8
+FW_PWR_OR VOLTAGE=33V MIN_LINE_WIDTH=100 MIN_NECK_WIDTH=12 28 29 LTC3411_ITH_RC MIN_LINE_WIDTH=8
+FW_VP0 VOLTAGE=33V MIN_LINE_WIDTH=100 MIN_NECK_WIDTH=12 29 LTC3411_ITH MIN_LINE_WIDTH=8
+FW_PWR_PORTA VOLTAGE=33V MIN_LINE_WIDTH=100 MIN_NECK_WIDTH=12 29 LTC3411_SYNC MIN_LINE_WIDTH=8
VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=6 GND +FW_VP1 VOLTAGE=33V MIN_LINE_WIDTH=100 MIN_NECK_WIDTH=12 29 LTC3411_SHDN MIN_LINE_WIDTH=8
+3V_FW VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 28 29
VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=12 CHGND1 +3V_FW_UF VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10

I/O AREA CHGND1 +3V_FW_AVDD_PORT2 VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
28
28
LTC1962 LTC1962_INT_VIN
LTC1962_L3_VIN
MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 14
INT PLLS MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10

VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=12 CHGND2 +3V_FW_AVDD_PORT1 VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=6 28 LTC1962_L3_VOUT MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10
INVERTER CHGND2 +3V_FW_AVDD_PORT0 VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 28 LTC1962_1V5_VIN MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10
CHGND3 +3V_FW_AVDD VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 28 LTC1962_1V5_VOUT
VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=12 MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10
TRACKPAD CHGND3
+1_95V_FW_DVDD VOLTAGE=1.95V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 28
CHGND4 +1_95V_FW_DVDD_RX0 VOLTAGE=1.95V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 28

VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=12 39
LVDS +1_95V_FW_DVDD_TX0 VOLTAGE=1.95V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 28 SIGNAL CONSTRAINTS - PAGE 3

A CHGND4
VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=12 CHGND5 +1_95V_FW_DVDD_PORT1 VOLTAGE=1.95V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 28
A
I/O AREA CHGND5
+1_95V_FW_PLLVDD
+1_95V_FW_PLL400VDD

VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=12 CHGND6 +1_95V_FW_PLL500VDD PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
I/O AREA CHGND6 FW_VGND0 VOLTAGE=0V MIN_LINE_WIDTH=100 MIN_NECK_WIDTH=12 29
FW_VGND1 VOLTAGE=0V MIN_LINE_WIDTH=100 MIN_NECK_WIDTH=12 29
ENET_CTAP_CHGND VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=12 27 FW_TPO0R VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
USB 2.0 NEC_AVDD VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
29 39
26
+3V_NEC_VDD VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 26

INTREPID D
SSCG
+3V_CG_PLL_MAIN
+2_5V_CG_MAIN
VOLTAGE=3.3V
VOLTAGE=2.5V
MIN_LINE_WIDTH=15
MIN_LINE_WIDTH=15
MIN_NECK_WIDTH=8
MIN_NECK_WIDTH=8
14

051-6459 A
SCALE SHT OF
NONE 38 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FUNCTIONAL TEST POINTS FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES

FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES +5V_INV_SW 22 38
KBD_X<9> 23 30
JTAG_ASIC_TMS TMDS_CONN_CLKP TV_C PCI_AD<7> 9 12 17 24 26 37 PCI_PAR 12 17 24 26 37
13 27 22 37 22
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES

FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES LEFT_USB_DM 24 26 37
KBD_Y<0> 23 30
JTAG_ASIC_TDI VGA_R 22 TV_Y PCI_AD<8> 9 12 17 24 26 37 PCI_CBE<0> 12 17 24 26 37
13 22

FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES KBD_Y<1> 23 30 FW_TPO1P LEFT_USB_DP 24 26 37
EIDE_OPTICAL_RST_L 24 37 29 37
PCI_AD<9> 9 12 17 24 26 37 PCI_CBE<1> 12 17 24 26 37
D
JTAG_ASIC_TDO_TP 27 VGA_G 22 TV_COMP 22

FUNC_TEST=YES D
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES RIGHT_USB_DM 26 32 37
EIDE_OPTICAL_WR_L KBD_Y<2> 23 30 FW_TPO1N 29 37
PCI_AD<10> 9 12 17 24 26 37 PCI_CBE<2> 12 17 24 26 37 24 37
JTAG_ASIC_TCK 13 27 VGA_B 22 SND_TO_AUDIO 14 25
FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES RIGHT_USB_DP 26 32 37
EIDE_OPTICAL_IOCHRDY 24 37
KBD_Y<3> 23 30 FW_TPI1P 29 37
JTAG_ASIC_TRST_L VGA_VSYNC SND_SYNC PCI_AD<11> 9 12 17 24 26 37 PCI_CBE<3> 12 17 24 26 37
13 27 22 14 25
FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES NEC_LEFT_USB_PWREN 24 26
EIDE_OPTICAL_INT 24 37
KBD_Y<4> 23 30 FW_TPI1N 29 37
CPU_CHKSTP_OUT_L VGA_HSYNC SND_CLKOUT PCI_AD<12> 9 12 17 24 26 37 AIRPORT_PCI_REQ_L 12 24
5 22 14 25 36

FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES KBD_Y<5> 23 30 CHARGE_LED_L NEC_LEFT_USB_OVERCURRENT 24 26
TPAD_F_TXD 30 31
PCI_AD<13> 9 12 17 24 26 37 AIRPORT_PCI_GNT_L 23
CPU_SRESET_L DVI_DDC_CLK_UF 12 24
5 22
FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=YES KBD_Y<6> 23 30 ADAPTER_DET NEC_RIGHT_USB_PWREN 26 32
TPAD_F_RXD 30 31
PCI_AD<14> 9 12 17 24 26 37 AIRPORT_PCI_INT_L 23
CPU_HRESET_L DVI_DDC_DATA_UF 14 24
5 7 23 22
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES KBD_Y<7> 23 30 SUTRO_ALS_GAIN_SW NEC_RIGHT_USB_OVERCURRENT 26 32
LID_CLOSED_L 23 24
PCI_AD<15> 9 12 17 24 26 37 EIDE_OPTICAL_DATA<0> 23
JTAG_CPU_TMS DVI_HPD_UF INT_AUDIO_TO_SND 24 37
5 23 22 14 25
FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES DCDC_EN 19 29 32 33 34
COMM_RESET_L KBD_NUMLOCK_LED 23 SUTRO_ALS_OUT 23 24
PCI_AD<16> 9 12 17 24 26 37 EIDE_OPTICAL_DATA<1> 14 25
JTAG_CPU_TDI LVDS_L0N SND_SCLK 24 37
5 23 19 22 37 14 25 36

FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES BBANG_HRESET_L 23
COMM_SHUTDOWN +BATT_POS 31 38 KBD_LED1_OUT 23 38
JTAG_CPU_TDO_TP LVDS_L0P SND_HW_RESET_L 24 37
5 19 22 37 14 25
COMM_RING_DET_L BATT_CLK 31 KBD_LED2_OUT 23 38
C JTAG_CPU_TCK 5 23 LVDS_L1N 19 22 37 SND_HP_SENSE_L 14 25

14 25 30
FUNC_TEST=YES
FUNC_TEST=YES
C
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES MAIN_RESET_L 14 17 18 20 24 26 30
FUNC_TEST=YES FUNC_TEST=YES BATT_DATA 31 COMM_TXD_L 14 25
PCI_AD<19> 9 12 17 24 26 37 EIDE_OPTICAL_DATA<4> KBD_ID 23 30
JTAG_CPU_TRST_L LVDS_L1P SND_LIN_SENSE_L 14 25 24 37
5 23 39 19 22 37
FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES RF_DISABLE_L_SPN 24
FUNC_TEST=YES FUNC_TEST=YES BATT_NEG 31 38 COMM_TRXC 14 25
PCI_AD<20> 9 12 17 24 26 37 EIDE_OPTICAL_DATA<5> +5V_TPAD_SLEEP 23 38
LVDS_L2N INT_I2C_DATA2 24 37
19 22 37 14 25
FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES AIRPORT_CLKRUN_L 24
FUNC_TEST=YES +3V_HALL_EFFECT PMU_BATT_DET_L 30 31 COMM_GPIO_L 14 25
PCI_AD<21> 12 17 24 26 37 EIDE_OPTICAL_DATA<6> 23 38
LVDS_L2P INT_I2C_CLK2 24 37
19 22 37 14 25
FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES ROM_RW_L 9 12 24
FUNC_TEST=YES FUNC_TEST=YES FANR_GND 25 38 COMM_DTR_L 14 25
CHGND4 PCI_AD<22> 12 17 24 26 37 EIDE_OPTICAL_DATA<7> KBD_CAPSLOCK_LED 23
CLKLVDS_LN I293 38 24 37
19 22 37
FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES ROM_ONBOARD_CS_L 9 24
FUNC_TEST=YES FUNC_TEST=YES COMM_RTS_L 14 25
SLEEP_LED 23 25 PCI_AD<23> 12 17 24 26 37 EIDE_OPTICAL_DATA<8> KBD_FUNCTION_L 23 30
CLKLVDS_LP I294 24 37
19 22 37
FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES ROM_CS_L 9 12 24
FUNC_TEST=YES FUNC_TEST=YES FANL_GND 25 38 COMM_RXD 14 25
PCI_AD<24> 9 12 17 24 26 37 EIDE_OPTICAL_DATA<9> KBD_CONTROL_L 23 30
INT_I2C_CLK0 LVDS_U0N 24 37
11 13 23 19 22 37
FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES CLK33M_AIRPORT 12 24 36
FUNC_TEST=YES FUNC_TEST=YES FANL_TACH 25 PMU_KB_RESET_L 30
KBD_COMMAND_L 23 30
INT_I2C_DATA0 11 13 23 LVDS_U0P 19 22 37
FUNC_TEST=YES
FANR_PWM 25 FUNC_TEST=YES FUNC_TEST=YES
I271
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES AIRPORT_IDSEL 24
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES PWR_BUTTON_L 23 25
KBD_OPTION_L 23 30
INT_I2C_CLK1 13 14 25 LVDS_U1N 19 22 37 BT_USB_DM 14 24 37 FUNC_TEST=YES
FANL_PWM 25
FUNC_TEST=YES
I272
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES ROM_OE_L 9 12 24
B FUNC_TEST=YES
INT_I2C_DATA1 13 14 25
FUNC_TEST=YES
LVDS_U1P 19 22 37
FUNC_TEST=YES
BT_USB_DP 14 24 37
KBD_SHIFT_L 23 30
FUNC_TEST=YES
RJ45_DP<0> 27 37
+PBUS 38
FUNC_TEST=YES
INT_MOD_DTI
B
I273 14 25
KBD_X<0> 23 30
+24V_PBUS 38
CBUS_DET_1_L LVDS_U2N MODEM_USB_DM PCI_AD<28> 9 12 17 24 26 37 EIDE_OPTICAL_DATA<13> 24 37
RJ45_DN<0> 27 37 FUNC_TEST=YES
17 19 22 37 14 25 37
I274 JTAG_CPU_TRST_L 5 23 39
KBD_X<1> 23 30
GPU_VCORE 18 19 38
CBUS_DET_2_L LVDS_U2P MODEM_USB_DP PCI_AD<29> 9 12 17 24 26 37 EIDE_OPTICAL_DATA<14> 24 37
RJ45_DP<1> 27 37 FUNC_TEST=YES
17 19 22 37 14 25 37
I275
MOD_BITCLK 14 25
FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES CPU_VCORE_SLEEP 5 34 38
KBD_X<2> 23 30 FUNC_TEST=YES
TMDS_DN<0> 20 22 37 CLKLVDS_UN 19 22 37 PCI_AD<0> 9 12 17 24 26 37 RJ45_DN<1> 27 37
I276
MOD_CLKOUT 14 25
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
KBD_X<3> 23 30
VCORE_FB 34 38
TMDS_DP<0> 20 22 37 CLKLVDS_UP PCI_AD<1> 9 12 17 24 26 37
PCI_AD<31> 9 12 17 24 26 37 EIDE_OPTICAL_DMA_RQ 24 37
RJ45_DP<2> 27 37 FUNC_TEST=YES
19 22 37
I277
MOD_DTO 14 25
KBD_X<4> 23 30
+1_8V_MAIN 38
TMDS_DN<1> 20 22 37 LVDS_DDC_CLK PCI_AD<2> 9 12 17 24 26 37
PCI_FRAME_L 12 17 24 26 37 EIDE_OPTICAL_RD_L 24 37
RJ45_DN<2> 27 37 I278 MOD_SYNC 14 25
19 22
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
KBD_X<5> 23 30
+3V_PMU 38
TMDS_DP<1> 20 22 37 LVDS_DDC_DATA PCI_AD<3> 9 12 17 24 26 37
PCI_TRDY_L 12 17 24 26 37 EIDE_OPTICAL_DMAACK_L 24 37
RJ45_DP<3> 27 37 I279 SLEEP 23 25 30 33 35
19 22

KBD_X<6> 23 30
+5V_DDC_SLEEP 22 38
TMDS_DN<2> 20 22 37 BRIGHT_PWM PCI_AD<4> 9 12 17 24 26 37
PCI_IRDY_L 12 17 24 26 37 EIDE_OPTICAL_ADDR<0> 24 37 RJ45_DN<3> 27 37 I280
1778_VFB 19 38
22

FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FW_TPO0R 29 38 +12_8V_INV 22 38
PCI_DEVSEL_L EIDE_OPTICAL_ADDR<1> KBD_X<7> 23 30
TMDS_DP<2> TV_GND1 PCI_AD<5> 12 17 24 26 37 24 37
20 22 37 22 38 9 12 17 24 26 37 FUNC_TEST=YES
VCORE_VID0
A FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
I281
FUNC_TEST=YES NOTICE OF PROPRIETARY PROPERTY
A
PCI_STOP_L EIDE_OPTICAL_ADDR<2> KBD_X<8> 23 30
TMDS_CONN_CLKN TV_GND2 PCI_AD<6> 9 12 17 24 26 37 12 17 24 26 37 24 37
22 37 22 38 VCORE_MUX_EN
FUNC_TEST=YES 34
FUNC_TEST=YES I286 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
I282
VCORE_VID1
FUNC_TEST=YES SRCLK_TP PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
I287 26 AGREES TO THE FOLLOWING
I291 SND_AMP_MUTE 25
FUNC_TEST=YES I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
FUNC_TEST=YES VCORE_VID2 II NOT TO REPRODUCE OR COPY IT
FUNC_TEST=YES SRMOD_TP I283
I288 26 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I292 SND_HP_MUTE_INV 25
TEB_TP SIZE DRAWING NUMBER REV.
I289 26 VCORE_VID3
FUNC_TEST=YES
I285
APPLE COMPUTER INC.

D 051-6459 A
FUNC_TEST=YES SCALE SHT OF
I290 TEST_TP 26
I284 VCORE_VID4
NONE 39 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REVISION HISTORY
REV 0.01 - 03/06/2003 5/22 7/2/03
3/3 102) fixed NO STUFF BOM option for R291 199) CHANGED J9 (CARDBUS) TO 516S0141 (NEW PIN PLATING SPEC)
1) Initial check-in of Enterprise schematic after conversion to Concept 14.2 103) add NO STUFF to R223 to correct startup level of GPU_VCORE_CNTL 200) CHANGED J20 (AIRPORT) TO 516S0142 (NEW PIN PLATING SPEC)
3/10 104) add NO STUFF to R300 to complete 3V sequecing on wake from sleep fix 201) CHANGED J10 (OPTICAL DRIVE) TO 516S0140 (NEW PIN PLATING SPEC)
2) added 8 new 10uF vcore caps 105) changed R376 to 158K and R321 to 2.74K to set CPU_VCORE offset to 35mV 202) CHANGED J13 (HARD DRIVE) TO 516S0140 (NEW PIN PLATING SPEC)
3) added jumpers at 1.5V, 1.8V, 2.5V, 3.3V, 5V, and PBUS supply outputs 203) CHANGED J12 (SOUND) TO 516S0144 (NEW PIN PLATING SPEC)
*** rev 04 released for EVT *** 204) CHANGED J8 (MODEM) TO 516S0143 (NEW PIN PLATING SPEC)
4) added 8 more 0.1uF vcore byapass caps
3/11 5/19/03 205) ADDED BOM TABLE TO PUT 0 OHM 402 ON L77,L80,L81,L82,L76,L78,L79
5) removed dedicated boot banger circuit (U5400,U5200,RP46,U9,U1000) 106) changed both AGP_NV_INT_L and AGP_ATI_INT_L to AGP_INT_L 7/9/03
6) updated firewire to phy to rev A prt number 107) removed redundant 3V_GPU pullup R687 (Intrepid side AGP_INT_L pullup) 207) CORRECTED C889 TO CONNECT TO INPUT (PIN 1) OF U55
208) REMOVED POWER JUMPERS XW25,XW17,XW16,XW10,XW14,XW18
D
7)
8)
9)
changed
changed
changed
cpu PLL config to 1083/833
reset to U56 (clock slewing chip) to MAIN_RESET_L
C550 to 138S0536 to limit AVL
108) added R699,R701,R707,R708 as 10k pulldowns to Intrepid USB ports A and C when NEC_USB is stuffed
109) changed SND_HP_MUTE_INV gate/inversion FETS to pullup to +3V_MAIN
110) added R711 as pullup to +3V_GPU on AUXWIN signal from M10 (U44)
209)
210)
CHANGED 197S0035 TO PRIMARY AND 197S0004 AS ALTERNATE
CHANGED 197S0037 TO PRIMARY AND 197S0603 AS ALTERNATE
FOR
FOR
Y1
Y3
(INTREPID)
(ETHERNET)
D
10) changed Vcore stuffing options to 1.4V/1.025V using analog mux to support slewing 111) added R698 as 0 ohm jumper between FW_PHY_PD and Intrepid 211) CHANGED 197S0038 TO PRIMARY AND 197S0608 AS ALTERNATE FOR Y5 (NEC USB2)
11) changed stuffing to set Vcore offset to 0mV by default 112) added U56, U57, R718,R714 for VGA Hsync and VGA Vsync buffering 212) CHANGED 197S0040 TO PRIMARY AND 197S0008 AS ALTERNATE FOR Y4 (LMU)
12) changed comments to eliminate references to L3 in power supply section 113) changed L72,L73,L74 to 155S0164 (new high speed part) 213) CHANGED 197S0041 TO PRIMARY AND 197S0604 AS ALTERNATE FOR Y6 (PMU)
3/18 114) added NO STUFF BOM option to R223 to correct for sense of GPU_VCORE_CNTL 7/22/03
13) changed stuffing options for GPU PCI ID to 0x319 115) added NO STUFF BOM option to R300 to avoid sleep wake problem 214) ADDED 1_32V_VCORE AND 1_30V_VCORE BOM OPTIONS FOR 2 DIFFERENT CPU VCORE SPECS
14) changed R164 (DAC1RSET) to 107 ohm pulldown 6/3/03 215) UPDATED CAP MATERIAL TYPES
15) added 10K pulldown to U43 pin A21 116) Intgrated new 1.8V switcher (LTC3412)(U58)(353S0650) and inductor (L75- 152S0142) 216) CHANGED FROM 715 PIN TO 667 PIN SYMBOL FOR U44 (M10)
16) changed fan controller to ADT7460 117) changed 2.5V_SLEEP FET (U48) and 1.8V_SLEEP FET (U6) to higher current part (Si6467BDQ - 376S0161) 7/28/03
3/19 118) added 10K pulldown (R720) on FW_PHY_PD_INT for when R698 is removed 217) CHANGED TMDS TERMINATION FROM 2X 162 TO 2X 49.9 OHMS PER PAIR
17) added pads for 0.1uF cap from +Adapter to digital gnd for EMC 119) changed R728 and R729 to 1210 0ohm resistors to support switching the entire memory bus between 1.8V and 2.5V 218) CHANGED 126S0036 FROM ALT TO PRIMARY, REPLACING 126S0035 FOR CPU VCORE INPUT CAPS
18) added pads for 0 ohm between chassis and digital gnd near ENET connector for EMC 120) added R721 as jumper between +2_5V_SLEEP and +2_5V_GPU
*** RELEASED FOR PRODUCTION 7/28/03 ***
19) corrected path to correct for last checkin 6/4/03
20) removed BOM table for MAP31 121) NO STUFF R631 to remove MAIN_RESET_L from clock slewing chip
21) REMOVED ALL RELATIVE_PROPAGATION_DELAY AND PROPAGATION_DELAY PROPERTIES TO 122) changed FWB connector to new part with extra ground tabs (514S0059)
PRERPARE FOR CONSTRAINT BACK ANNOTATION 6/5/03
22) changed CHGND on R616 to CHGND1
123) changed I2C 0 and 1 pullups (RP12) to 2.2K to improve rise/fall times (sensor check config errors)
23) ***BOARD RENUMBERED*** 124) added CRITICAL flag to new 1.8V switcher (U58), inductor (L75), 1.8V sleep FET (U6), and 2.5V sleep FET (48)
3/28 125) removed gnd caps (C651 and C647) on I2S clock at sound connector (J12)
24) integrated M10 pages from Q16 schematic and renumbered them 126) added LC filter on SND_SYNC for EMI (L77 and C895)
4/10 127) added LC filter on SND_CLKOUT for EMI (80 and C899)
25) updated physical constraints for M10 power nets 128) added LC filter on INT_AUDIO_TO_SND for EMI (L81 and C896)
26) added DP7 for M10 power sequencing 129) added LC filter on SND_TO_AUDIO for EMI (L82 and C897)
27) added RP27,RP28,RP32, and RP57 for TMDS series termination 130) added LC filter on SND_AMP_MUTE for EMI (L76 and C898)
28) update PLL CFG high 0010 1.25GHz 131) added LC filter on SND_HW_RESET_L for EMI (L78 and C900)
low 1011 833MHz 132) added LC filter on SND_SCLK for EMI (L79 and C901)
29) update sscg/nosscg stuffing option on intrepid boot straps 133) added C902 and R804 to prevent latch-up condition in GPU Vcore circuit when using powermiser
30) removed D31 between +Batt and 24V_Pbus 134) removed R331 (CPU Vcore positioning resistor)
31) add Vcore DAC resistors (R288,R289,R290,R292) for no mux case 135) changed C728,C729,C730,C731,C732,C733,C734,C884,C885 to 220uF Rubycon caps (128S0024)
32) change intrepid PLL LDO stuffing back to 1.8V main 136) add Vcore offset change circuit to modify offset in low (Q86,R805,R806,R807,R808,R809)
33) change C640 and C646 to 0.01uF (Apple # 132S1047) for FW check config 137) changed Q83 into dual (2N7002DW) and added R810 to invert 3V_5V_ON before switching RUN/SS
34) change I2C pullups (R29 and R102) to 1K 6/6/03
35) changed bootrom part number to 341S1255 138) rotated J26 (FW B connector)
C 4/18
36) changed C756 to 128S0025 (Sanyo only 6.3V 330uF)
139) changed D29 to B340B (3A part - 371S0159)
6/9/03
C
37) add pads for 90 ohm chokes to FWB path close to connector (route through the pads) 140) modified Vcore offset select circuit with Takashi’s changes - changed Gnd reference to VCORE_GND_SNS
38) changed Vcore inductor (L36) to molded core part (152S0125) 141) added double inverter to buffer THERM _L_OC (added Q87,R811,R812)
39) changed Pbus inductor (L37) to molded core part (152S0126) 142) removed redundant pullup on THERM_L_OC (R780)
40) added seperate 1_8V_GPU_TPVDD filter and LDO (U54) 6/9/03
4/21 143) added cap on gate of the second FET in Q87 for possible turn on delay (C903)
41) replace disctrete LCL with single chip LCL filters (155S0154) for VGA (L ,L , and L ) 144) changed inner shield of FWB connector J26 to connect to chassis gnd
42) add 165 ohm chokes on TMDS data pairs at connector (L ,L , and L ) 145) changed R336 and R325 to 0 ohm to set Vcore VID to 1.3V/1.15V
43) move BS1 to bottom side 146) changed R321 to 2.49K to set Vcore offset to +25mV
44) move CPU thermal sensor (Q39) to input 1 on fan controller and power supply sensor (Q66) to input 2 147) added 10 ohm resistor (R814) and 1uF cap (C904) to filter power to ADT7460 (Gary Leo)
45) added trace from Vcore to fan controller ADC input 6/10/03
46) added FET inverters (Q78) to PWM outputs of fan controller (U3) to prevent spinup at boot 148) changed R612 to 10K to prevent UIDE DMACK from floating
47) added FET (Q79) for +3V_Sleep for M10 power sequencing 149) changed C80,C88,C81,C89,C82,C102,C79,C87 to NO STUFF (TMDS common-mode termination)
4/27 150) changed R205,R218,R211,R219,R210,R220,R204,R214 to 162 ohm 1% (TMDS common-mode termination)
48) changed TMDS data chokes to 90 ohm (155S0128) 151) changed RP27,RP32,RP28,RP57 to 10ohm (TMDS series termination)
49) changed C762 and C766 to 4.7uF 1206 caps
50) changed TMDS data chokes to 90 ohms (155S0128) *** released for EVT2 6/10/03 ***
51) changed C762 and C766 to 4.7uF 1206 6/13/03
52) changed Q51 to Si7860DP (376S0119) 152) fixed NO STUFF on R291
53) changed Q48 to Si7892DP (376S0120) 153) removed NO STUFF from C80,C88,C81,C89,C82,C102,C79,C87 (TMDS common-mode termination)
54) changed D24 to B340LB (371S0132) 154) removed NO STUFF from R638 (pullup on slewing chip FSEL)
55) changed L30 to 2.2uH Tokin inductor (152S0139) 155) removed NO STUFF from C903 (cap on input to second part of THERM_OC_L buffer)
56) added Q58, R307, and C515 for GPU Vcore control inverter 156) CHANGED R321 TO 1K FOR VCORE OFFSET OF 12MV (VCORE = 1.30V -30MV/+100MV)
57) changed R416 to 2.2ohms
58) changed R364 to 102K *** released for EVT2 6/13/03 ***
59) added 0.1uF 50V C883 to RS- of Max4172 (NO stuff) 6/18/03
60) changed D18 to 1N914 157) changed R228 to pullup to 1.8V for DVO interface conpatibility
61) changed L38 and L41 to 4.7uH (152S0137) 158) added R234 and INT_TMDS option to maintain internal TMDS capability
62) added Q81, R308, R309, and R310 for power sequencing (no stuff) 159) changed L30 to 3 pin symbol
63) changed Q49 and Q50 to Si7860DP (376S0119) 160) added U5 to use as external TMDS transmitter (DVI)
64) changed L36 to 1.2uH 18.3A (152S0125) 161) added R41 to create +3V_GPU_SI power for SIL1162 (U5)
65) added R331 1mohm sense resistor to CPU Vcore 162) added L14, C130, C132, and C165 for 3V AVCC filtering for SIL1162 (U5)
66) added C885 and C884 , 1000uF CPU Vcore outpur caps 163) added L13, C14, C129, C131, C133 for 3V PVCC filtering for SIL1162 (U5)
67) added Q82, R607, R455, R417, and C886 for 1.5V sleep sequencing
B 68) added Q83 and 100K R608 for 1.8V sequencing
69) added 15.4K R616 and 10K R672 for 2.5V switcher feedback divider
164) added L15, C255, C233, C218 for 3V Vcc filtering for SIL1162 (U5)
165) added R235 and R237 as options for MAIN_RESET_L to U5
166) added R231. R232, and C284 for Vref for U5
B
70) changed pinout of sound connector for sousaphone 167) added R66, R99, R202, R212, R222, R224, R88, R110, R223 as straps for U5
71) removed Q44 (5V sound sleep fet) 168) added RP58, RP59, RP60, RP61 for series termination of SIL1162 TMDS output
72) changed Q31 to invert headphone Mute to sousaphone 169) added L16, C304, C327, C647 for filtering GPU VDDR4
4/28 170) added R255 and R251 to strap GPU_DVODMODE correctly for 1.8V DVO
73) changed CPU_VCORE_SLEEP location back to across bypass caps to correct after adding reference resistor 171) added R268 to connect L16 to +3V_GPU_FLT when not using SIL1162
74) changed D5 to schottky diode (MBR0540) 172) added C681, C668, C678, C651 to filter the thermal sensor diff pairs
75) fixed unnamed net (LTC3411_SHDN_SEQ)
76) changed drain/source polarity of Q76 (FET from +BATT to Pbus) 6/19/03
173) changed GPU_MEM_IO to +GPU_MEM to connect ATI Vref to correct memory voltage
4/28 174) swapped TMDS CLKN and CLKP on RP57 and RP58 for layout
77) moved XW15 to connect to CPU_VCORE_SLEEP_UF (before positioning resistor) 175) swapped DN<0> and DP<0> on RP27 for layout
78) changed Fan control nets to FanL and FanR from Fan1 and Fan2 176) corrected un-named nets in TMDS common-mode filters
79) SWAPPED CONNECTIONS SO THAT OUTPUT 1 FROM FAN CONTROLLER CONNECTS TO 177) added physical constriants for new Silicon Image power rails
LEFT FAN (CPU) AND FAN 2 CONNECTS TO THE RIGHT FAN (GPU) 178) CHANGED C728,C731,C734,C733,C730,C732,C729,C885,C885 TO 128S0022
80) updated power constraints with new fan net names (124S0024 WILL BE DELETED AS A DUPLICATE IN THE LIBRARY)
4/28 6/23/03
81) change Q58 on pg19 to Q80 to consolidate parts 179) NO STUFF’ed C895,C899,C896,C897,C898,C900, and C901 to fix no sound problem
82) CHANGED U55 TO MM1571J FOR COST SAVINGS 180) changed C890 to 100pF for improved transient response (Takashi)
83) changed L72,L73,L74 to 90 ohm ferrites 181) Removed bypass traces on FWB chokes and stuffed L70 and L71
84) added 10K pullup to +5V_MAIN to SND_HP_MUTE 182) CHANGED R491 TO 52.3K 1%, R475 TO 127K 1%, AND R476 TO 4.7M 5% IN A29
85) repinout Sousaphone connector ADAPTER DETECT CIRCUIT DIVIDERS TO REDUCE SHUTDOWN CURRENT
86) remore redundant pullups on FANL_TACH and FANR_TACH 183) added R331 as CPU Vcore sense resistor (1 mohm 1% 2512)
87) added TP to all NC on NEC USB2 part for NAND tree testing 184) No STUFF’ed C651 and C678
88) added NEC_USB bomoption to 0 ohm resistor on NEC_AVSS_F 185) added C688,C690,C846,C905 for thermal pair filtering at fan controller
186) added C906 to prevent shoot-thru on Q64 (currently NO STUFF’ed)
4/30 187) added C907 to prevent shoot-thru on Q68 (currently NO STUFF’ed)
89) repinout Sousaphone connector (J12) 188) changed R517 to 100K
90) no stuff R322 to eliminate 3V_sleep pump up 189) changed GND reference for input side of Q86 to digital GND (the other FET in Q856 remains on VCORE_GNDSNS
91) updated various text notes with correct reference designators
6/24/03
5/1 190) added C908 to prevent gate shoot-thru on Q56
92) change L30 to 152S0139 (Tokin CPI-1050-2R2) 11A 191) added R279 to power TMDS PLL from LVDS filter when using external TMDS transmitter
93) remove FANR_TACH functional test point 192) changed R325 to 470K to set the low Vcore to 1.10V
A 94) add CHGND4 and SLEEP_LED functional test points
95) swap INT_AUDIO_TO_SND and SND_TO_AUDIO on Sousaphone connector (J12)
*** rev 01 released for EVT ***
193) stuffed Vcore offset switch (R807,R805,R809,Q86)
194) changed R809 to 1.5K 1% to set low Vcore offset to 10mV
A
195) changed R321 to 3.01K 1% to set high Vcore offset to 30mV
5/6
96) remove NO STUFF on R477 (set 5V and 3.3V switcher in pulse skipping mode) 6/25/03 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
97) change R337 to 470K and remove No Stuff and no stuff R336 to change Vcore DAC to 1.35V/1.15V 196) rotated L70 and L71 for layout (PCB symbol problem) PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
197) changed Q53,Q54,Q55 to IRF7832 (376S0148) for better thermal performance AGREES TO THE FOLLOWING
98) change R321 to 499ohm to set 5mV Vcore offset
99) change L72,L73,L74 to 155S0165 (D part for EVT only) 198) NO STUFF’ed C908 (Q56 gate shoot-thru cap) I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
*** rev 02 released for EVT *** *** released for DVT 6/26/03 *** II NOT TO REPRODUCE OR COPY IT
5/7
100) no stuff Q79 to disable 3V_SLEEP sequencing to work around wake from sleep bug with M10 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
101) added BOM table to define correct part number for M10 without heatspreader (338S0133)
*** rev 03 released for EVT *** SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.

D 051-6459 A
SCALE SHT OF
NONE 40 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
*** Signal Cross-Reference for the entire design *** 3V_SNSM 33C4< 37A2> AGP_SBA<5> 12B2<> 18C6> CG_RESET_L 14B7< CPU_DATA<60> 6B8<> 8B3< 8B4<> ENET_ENERGY_DET 14B5<> 27B7<> GPU_SSCLK_UF 36C1> LCD_DIGON_L 22A6< MEM_DATA<63..56> 36A5>
3V_SNSP 33C4< 37A2> AGP_SBA<6> 12B2<> 18C6> CHARGE_DISABLE 31A7<> CPU_DATA<61> 6B8<> 8B3< 8B4<> ENET_HSDACM 27A7<> GPU_THERM_DM 18A6<> LCD_PWREN_L 22A5<> MEM_DATA<57> 9B8<> 10C1<>
+1_0V_MARVELL 27D2< 38B3> 3V_SW 33C4<> 38D1> AGP_SBA<7> 12B2<> 18C6<> CHARGE_LED_L 30C6<> 30D7< 31D8<> 39D2> CPU_DATA<62> 6A8<> 8B3< 8B4<> ENET_HSDACP 27A7<> GPU_THERM_DP 18A6<> LED_LINK10 27B5<> MEM_DATA<58> 9B8<> 10C1<>
+1_5V_AGP 12C5< 12D1< 12D4< 15D6< 16C8< 3V_TG 33D4<> AGP_SB_STB 12B2< 12B2<> 18C6<> 37D5> CHGND1 38A6> CPU_DATA<63> 6A8<> 8B3< 8B4<> ENET_LINK_RXD<0> 13C5< 27C7> GPU_TV_GND1 22B8<> 38B6> LED_LINK100 27B5<> MEM_DATA<59> 9B8<> 10C1<>
18C6< 18D6< 19A8< 19B4<> 19D5<> 3V_VOSNS 33C4<> AGP_SB_STB_L 12A2< 12A2<> 18C6<> 37D5> CHGND2 38A6> CPU_DBG_L 5C3< 8A4<> 8C2< 36D5> ENET_LINK_RXD<7..0> 37A5> GPU_TV_GND2 22A8<> 38B6> LED_RX_SPN 27B5> MEM_DATA<60> 9B8<> 10C1<>
21B8< 21D6< 38C3> 5V_BG 33C5<> AGP_ST<0> 12A2<> 18C6< CHGND3 38A6> CPU_DRDY_L 5C3> 8A4< 8C2< 36D5> ENET_LINK_RXD<1> 13C5< 27C7> GPU_VCORE 18A6< 19A3<> 19B5<> 19D4< 38C3> LEFT_USB_DM 24B2<> 26B3< 37A2> 39D1> MEM_DATA<61> 9B8<> 10B1<>
+1_5V_AGP_GPU 21C5< 38C3> 5V_BOOST 33C5<> AGP_ST<1> 12A2<> 18C6< CHGND4 38A6> 39B6> CPU_DRDY_L_UF 36D5> ENET_LINK_RXD<2> 13C5< 27C7> 39B2> LEFT_USB_DP 24B2<> 26A3< 37A2> 39D1> MEM_DATA<62> 9B8<> 10B1<>
+1_5V_AGP_NECK 19B4<> 38B3> 5V_BOOST_ESR 33D6<> AGP_ST<2> 12A2<> 18C6< CHGND5 38A6> CPU_DTI<0> 5C3< 8A4<> ENET_LINK_RXD<3> 13C5< 27B7> GPU_VCORE_CNTL 19A3<> LID_CLOSED_L 23A7<> 39C4> MEM_DATA<63> 9B8<> 10B1<>
+1_5V_GPU_VDD15 19D3< 38C3> 5V_HD_PWREN 33A8<> AGP_STOP_L 12B2<> 12C2< 18B7<> 37D5> CHGND6 38A6> CPU_DTI<0..2> 36D5> ENET_LINK_RXD<4> 13C5< 27B7> GPU_VCORE_CNTL_L 19A4< 19B7<> LM2594_IN 28D8<> 38B3> MEM_DQM<0> 9C6<> 10C7<> 36C5>
+1_5V_INTREPID_PLL 8D6< 12D4< 12D8< 14D6<> 38D3> 5V_ITH 33C5<> AGP_STP_L 18C6< CLK10M_PMU_XIN 30B6< CPU_DTI<1> 5C3< 8A4<> ENET_LINK_RXD<5> 13C5< 27B7> GPU_VCORE_NECK 19B5<> 38B3> LT1962_INT_ADJ 14D6< MEM_DQM<1> 9C6<> 10B7<> 36C5>
+1_5V_INTREPID_PLL1 14C3< 38D3> 5V_ITH_RC 33C6< AGP_SUS_STAT_L_PU 18C6< CLK10M_PMU_XOUT 30B6< CPU_DTI<2> 5C3< 8A4<> ENET_LINK_RXD<6> 13C5< 27B7> GPU_VCORE_PWR_SEQ 19A8<> LT1962_INT_BYP 14D6<> MEM_DQM<2> 9C6<> 10C5<>
+1_5V_INTREPID_PLL2 14D3< 38D3> 5V_RSNS 33D7< 38D1> AGP_TRDY_L 12B2<> 12C2< 18B7<> 37D5> CLK10M_PMU_XOUT_UF 30B7< CPU_EDTI 5B2< 5C3< ENET_LINK_RXD<7> 13C5< 27B7> GPU_VCORE_SEQ 19A8< LTC1625_ITH 31D3<> MEM_DQM<3..2> 36B5>
+1_5V_INTREPID_PLL3 14D3< 38D3> 5V_RUNSS 33C5< AGP_WBF_L 12A4<> 12B2< 18B7> CLK18M_INT_EXT 14A6<> 36B1> CPU_EMODE0_L 5A3< 7A4< ENET_LINK_TXD<0> 13B4< 13D5> GPU_VCORE_SEQ_L 19A8< LTC1962_1V5_VIN 38A1> MEM_DQM<3> 9C6<> 10B5<>
+1_5V_INTREPID_PLL4 14D3< 38D3> 5V_SLEEP_PWREN 33A8<> AIRPORT_CLKRUN_L 24C6<> 39C1> CLK18M_INT_XIN 14A5< 36B1> CPU_EMODE1_L 5A3< 5C2< ENET_LINK_TXD<7..0> 37A5> GPU_VCORE_SW 19A4<> 38B1> LTC1962_1V5_VOUT 38A1> MEM_DQM<4> 9C6<> 10C3<>
+1_5V_INTREPID_PLL5 12D3< 38D3> 5V_SNSM 33C5< 37A2> AIRPORT_IDSEL 24C5<> 39B1> CLK18M_INT_XOUT 14A5<> 36B1> CPU_GBL_L 5A7<> 8B6<> 36D5> ENET_LINK_TXD<1> 13B4< 13D5> GPU_VCORE_VDDCI 18A5< 38C3> LTC1962_INT_VIN 14D7<> 38A1> MEM_DQM<5..4> 36B5>
+1_5V_INTREPID_PLL6 12D6< 38D3> 5V_SNSP 33C5< 37A2> AIRPORT_PCI_GNT_L 12D7<> 24D5<> 39C4> CLK18M_XTAL_IN 14A5< 36B1> CPU_HIT_L 5A7> 8B6< 8D2< 36D5> ENET_LINK_TXD<2> 13B4< 13D5> GPU_Y 19D6<> 22B8< LTC1962_L3_VIN 38A1> MEM_DQM<5> 9C6<> 10B3<>
+1_5V_INTREPID_PLL7 8D5< 38D3> 5V_SW 33C5<> 38D1> AIRPORT_PCI_INT_L 14B5<> 14D7< 24D5<> 39C4> CLK25M_ENET_XIN 27A7< 36B1> CPU_HRESET_INV 7A7<> ENET_LINK_TXD<3> 13B4< 13D5> HD_ADDR<0> 24C2<> 24C3< LTC1962_L3_VOUT 38A1> MEM_DQM<6> 9C6<> 10C1<> 36B5>
+1_5V_INTREPID_PLL8 14D3< 38D3> 5V_TG 33C5<> AIRPORT_PCI_REQ_L 12A7< 12D7<> 24D6<> 39D4> CLK25M_ENET_XOUT 27A7<> 36B1> CPU_HRESET_L 5B3< 5C2< 7A5< 7A8< 23A2<> 39C8> ENET_LINK_TXD<4> 13B4< 13D5> HD_ADDR<2..0> 37C5> LTC3405_SW 27D4<> 38B3> MEM_DQM<7> 9C6<> 10B1<> 36A5>
D
+1_5V_LDO
+1_5V_MAIN
+1_5V_SLEEP
35D8< 38D6>
38D6>
38D6>
5V_VOSNS
1625_BG
1625_BST
33C5<>
32C5<>
32C5<
AIRPORT_PME_L_TP 24D5<>
AMP_CONTROL 25C5<> 25D5<>
ATI_AGP_FBSKEW<0> 19C2< 19C7<>
CLK25M_XTAL_IN
CLK27M_GPU_XIN
27A7<
36B1>
CLK27M_GPU_XOUT 36B1>
CPU_L1TSTCLK
CPU_L2TSTCLK
CPU_LSSD_MODE
5B2< 5B3<
5B3< 5C2<
5B3< 5C2<
ENET_LINK_TXD<5> 13B4< 13D5>
ENET_LINK_TXD<6> 13A4< 13D5>
ENET_LINK_TXD<7> 13A4< 13D5>
HD_ADDR<1>
HD_ADDR<2>
HD_CS0_L
24C2<> 24C3<
24B3< 24C1<>
24C2<> 24C3< 37B5>
LTC3411_GND
LTC3411_ITH
LTC3411_ITH_RC
38A1>
38A1>
38A1>
MEM_DQS<0>
MEM_DQS<1>
MEM_DQS<2>
9C6<>
9C6<>
9C6<>
10C7<>
10B7<>
10C5<>
36C5>
36C5> D
+1_5V_SLEEP_NECK 21A3<> 38B3> 1625_BST_ESR 32C5<> ATI_AGP_FBSKEW<1> 19C2< 19C7<> CLK27M_XTAL_IN 36B1> CPU_MCP_L 5B3< 5D2< ENET_LINK_TX_EN 13D5<> 37A5> HD_CS1_L 24B3< 24C1<> 37B5> LTC3411_SHDN 38A1> MEM_DQS<3..2> 36B5>
+1_5V_SLEEP_VIN 35D8<> 38D6> 1625_COMP 31D2< 32C6< ATI_BUS_CFG<0> 19B2< 19C7<> CLK32K_PMU_XIN 30B3<> CPU_M_DM 25A8< 25B6< ENET_LINK_TX_ER 13D5<> 37A5> HD_DATA<0> 24C2<> 24D3< LTC3411_SYNC 38A1> MEM_DQS<3> 9C6<> 10B5<>
+1_8V_ATI_PVDD 19C5<> 21B6< 21B6< 21D6<> 38C3> 1625_DIV 32C8< ATI_BUS_CFG<1> 19B2< 19C7<> CLK32K_PMU_XOUT 30B3<> CPU_M_DP 25B6< 25B8< ENET_MDC 13C5> 27B7< 37A5> HD_DATA<15..0> 37C5> LTC3411_VCC 38B1> MEM_DQS<4> 9C6<> 10C3<>
+1_8V_ATI_TPVDD 21D2<> 1625_ENABLE 32D7<> ATI_BUS_CFG<2> 19B2< 19C7<> CLK32K_PMU_XOUT_UF 30B2<> CPU_PLL_CFG<0> 5C3< 7D3< ENET_MDIO 13C5<> 27B7<> 37A5> HD_DATA<1> 24C2<> 24D3< LTC3412_GND 35A6<> MEM_DQS<5..4> 36B5>
+1_8V_DVO_F 21B2< 1625_ENABLE_L 32D6<> ATI_CLK27M_IN 18C1< 19B7< CLK33M_AIRPORT 12D8< 24D5<> 36C1> 39B1> CPU_PLL_CFG<1> 5C3< 7D3< ENET_PHY_TXD<0> 13B5< 27C7< HD_DATA<2> 24D2<> 24D3< LTC3412_ITH 35A6<> MEM_DQS<5> 9C6<> 10B3<>
+1_8V_GPU 18A7< 19D8< 20A5< 21A2< 21A6< 1625_EXTVCC 32D5<> 38D1> ATI_CLK27M_OSC 18D2< CLK33M_AIRPORT_UF 12C7<> 36C1> CPU_PLL_CFG<2> 5C3< 7D3< ENET_PHY_TXD<7..0> 37A5> HD_DATA<3> 24D2<> 24D3< LTC3412_ITH_RC 35A6< MEM_DQS<6> 9C6<> 10C1<> 36B5>
21B1< 21B6< 21C8< 21D6< 21D8< 38C3> 1625_FCB 32C6< ATI_CLK27M_OSC_SS 18B2< 18D1< CLK33M_CBUS 12D8< 17A7< 36C1> CPU_PLL_CFG<3> 5C3< 7D3< ENET_PHY_TXD<1> 13B5< 27C7< HD_DATA<4> 24C3< 24D2<> LTC3412_PGOOD 35A4<> MEM_DQS<7> 9C6<> 10B1<> 36A5>
+1_8V_GPU_AVDD 21D5< 38C3> 1625_INTVCC 32C5<> 38D1> ATI_DBI_HI_PU 18C6<> CLK33M_CBUS_UF 12C7<> 36C1> CPU_PLL_CFG<4> 5C3< 7D3<> ENET_PHY_TXD<2> 13B5< 27C7< HD_DATA<5> 24C3< 24D2<> LTC3412_RT 35A6< MEM_MUXSEL_H<0> 9B6<> 10A6<
+1_8V_GPU_AVDDQ 21D4< 21D7< 38C3> 1625_RUNSS 32C6< ATI_DBI_LO_PU 18C6<> CLK33M_USB2 12C8< 26B7< 36C1> CPU_PLL_CFGEXT 7D4<> ENET_PHY_TXD<3> 13B5< 27C7< HD_DATA<6> 24C3< 24D2<> LTC3412_RUNSS 35A6<> MEM_MUXSEL_H<1..0> 36A5>
+1_8V_GPU_MEMPLL 21B5< 38C3> 1625_SGND 32B7<> 38D1> ATI_DVODMODE 21A3< CLK33M_USB2_UF 12C7<> 36C1> CPU_PLL_FS00 7C4<> ENET_PHY_TXD<4> 13B5< 27C7< HD_DATA<7> 24C3< 24D2<> LTC3412_SYNC 35A6<> MEM_MUXSEL_H<1> 9B6<> 10A4<
+1_8V_GPU_PLL 21D5< 38C3> 1625_TG 32C5<> ATI_GPIO7_SPN 19C7<> CLK66M_AGP_15V_TP 12C4> CPU_PLL_FS01 7C4< ENET_PHY_TXD<5> 13B5< 27C7< HD_DATA<8> 24C3< 24D1<> LTC3412_VFB 35A6<> MEM_MUXSEL_L<0> 9B6<> 10A6<
+1_8V_GPU_PNLIO 21A5< 38C3> 1625_VFB 32B5<> ATI_GPIO8_PD 19C7<> CLK66M_GPU_AGP 12C8< 18B7< 36C1> CPU_PLL_FS10 7C4< ENET_PHY_TXD<6> 13A5< 27C7< HD_DATA<9> 24C3< 24D1<> LTC3412_VFB_DIV 35A6< MEM_MUXSEL_L<1..0> 36A5>
+1_8V_GPU_PNLPLL 21B5< 38C3> 1625_VIN 32C6< 38D1> ATI_GPIO9_SPN 19C7<> CLK66M_GPU_AGP_UF 12C7<> 36C1> CPU_PLL_STOP_BASE 7C7< ENET_PHY_TXD<7> 13A5< 27C7< HD_DATA<10> 24C3< 24D1<> LTC3707_START_RC 33B6<> MEM_MUXSEL_L<1> 9B6<> 10A4<
+1_8V_GPU_TP_PLL 21B4< 21D1< 1625_VSW 32C4<> 38D1> ATI_GPIO10_SPN 19C7<> CLKENET_LINK_GBE_REF 13C5< 27C8< 36B1> CPU_PLL_STOP_OC 7C4<> 7C8<> 30B6<> ENET_PHY_TX_EN 13D6< 27C7< 37A5> HD_DATA<11> 24D1<> 24D3< LVDS_DDC_CLK 19C5<> 22B5<> 39A7> MEM_RAS_L 9A5< 9C6<> 36A5>
+1_8V_GPU_VDDDI 21C7< 21D4< 38C3> 1772_ACIN 31B5< ATI_GPIO11_SPN 19C7<> CLKENET_LINK_GTX 13C5<> 36A1> CPU_PMONIN_L 5A3< 5C2< ENET_PHY_TX_ER 13D6< 27C7< 37A5> HD_DATA<12> 24B3< 24D1<> LVDS_DDC_DATA 19C5<> 22B5<> 39A7> MEM_WE_L 9A5< 9C6<> 36A5>
+1_8V_MAIN 38D6> 39A2> 1772_ACOK_L 31B5<> 31C4<> ATI_GPIO12_SPN 19C7<> CLKENET_LINK_RX 13D5< 27C8< 36B1> CPU_PULLDOWN 5A2< 5A3< 5A3< 5C7<> ENET_RSET 27A5< HD_DATA<13> 24B3< 24D1<> LVDS_L0N 19B5> 22B4<> 37C2> 39C7> MLB_ALS_GAIN_SW 23C4<> 23C8<>
+1_8V_MAIN_LX_F 35A4<> 1772_BST 31B4<> ATI_GPIO13_SPN 19C7<> CLKENET_LINK_TX 13D5< 27D8< 36A1> CPU_PULLUP 5A3< 5C2< ENET_RST_L 27B7< HD_DATA<14> 24C1<> 24C3< LVDS_L0P 19B5> 22B4<> 37C2> 39C7> MLB_ALS_OP_COMP 23D7<
+1_8V_PVDD_NECK 19B5<> 38B3> 1772_BST_ESR 31C3< ATI_HSYNC 19D5<> 22C8< CLKENET_PHY_GBE_REF 27C7<> 36B1> CPU_QACK_L 5B3< 8B6<> 36D5> ENET_RX_DV 13D5< 27B7> 37A5> HD_DATA<15> 24B3< 24C1<> LVDS_L1N 19B5> 22B4<> 37C2> 39C7> MLB_ALS_OP_IN 23D7<
+1_8V_SLEEP 38D6> 1772_CCI 31B5<> ATI_MEMTEST 18A6<> CLKENET_PHY_GTX 13C6< 27C7< 36A1> CPU_QREQ_L 5B3> 8B6< 8C2< 36D5> ENET_RX_ER 13C5< 27B7> 37A5> HD_DIOR_L 24A3< 24C2<> 37B5> LVDS_L1P 19B5> 22B4<> 37C2> 39C7> MLB_ALS_OUT 23C4<> 23D6<
+1_8V_SLEEP_NECK 21A3<> 38B3> 1772_CCS 31B5< ATI_MEMVMODE0 18A7< CLKENET_PHY_RX 27C7<> 36B1> CPU_SHD0_L 5A7<> 5D2< ENET_VSSC 27A7<> HD_DIOW_L 24A3< 24C1<> 37B5> LVDS_L2N 19B5> 22B4<> 37C2> 39C7> MLB_ALS_OUT_FB 23D7<>
+1_95V_FW_DVDD 28C4< 28C7<> 28D5< 38A3> 1772_CCV 31B5<> ATI_MEMVMODE1 18A7< CLKENET_PHY_TX 27D7<> 36B1> CPU_SHD1_L 5A7<> 5D2< EXT_SWING 20A5<> HD_DMACK_L 24A3< 24C2<> 37B5> LVDS_L2P 19B5> 22B4<> 37C2> 39C7> MLB_PHOTODIODE 23D8<>
+1_95V_FW_DVDD_PORT1 28D6< 38A3> 1772_CCV_RC 31B5< ATI_OSC_OE 18D3< CLKFW_LINK_LCLK 13C3<> 36A1> CPU_SMI_L 5B3< 5C2< 30C4<> FANL_GND 25A3<> 38B6> 39B3> HD_DMARQ 13C6< 24C2<> 37B5> LVDS_L3N_TP 19B5> MODEM_USB_DM 14B1< 25C3<> 37A2> 39B6>
+1_95V_FW_DVDD_RX0 28C5< 38A3> 1772_CELLS 31B4< ATI_PVDD_BYP 21D6<> CLKFW_LINK_PCLK 13C3<> 28C3< 36A1> CPU_SRESET_L 5B2< 5B3< 39C8> FANL_PWM 25A3<> 25B2<> 39B3> HD_INTRQ 13C6< 24C1<> 37B5> LVDS_L3P_TP 19B5> MODEM_USB_DP 14B1< 25C3<> 37A2> 39B6>
+1_95V_FW_DVDD_TX0 28C5< 38A3> 1772_CLS 31A4< ATI_R2SET 19D6<> CLKFW_PHY_LCLK 13C2< 28B8< 36A1> CPU_SRWX_L 5A3< 5C2< FANL_TACH 25A3<> 25B2< 39B3> HD_IOCHRDY 24A3< 24C1<> 37B5> LVDS_U0N 19C5> 22A4<> 37C2> 39B7> MOD_BITCLK 14A2< 25C3<> 39B1>
+1_95V_FW_PLL400VDD 28D5< 38A3> 1772_CSIN 31B4<> 37A2> ATI_RSET 19D6<> CLKFW_PHY_PCLK 28B4> 28C3< 36A1> CPU_TA_L 5B3< 8A4<> 8D2< 36D5> FANR_GND 25B2<> 38B6> 39B3> HD_RESET_L 24A3< 24D2<> 37B5> LVDS_U0P 19C5> 22A4<> 37C2> 39B7> MOD_CLKOUT 14A2< 25C4<> 39A1>
+1_95V_FW_PLL500VDD 28D5< 38A3> 1772_CSIP 31B4<> 37A2> ATI_RSTB_MSK 18C6<> CLKLVDS_LN 19B5> 22A4<> 37C2> 39B7> CPU_TBEN 5B3< 5D2< 8A6<> FANR_PWM 25A2<> 25B1<> 39B3> HIGH_VCORE 19A2<> LVDS_U1N 19C5> 22A4<> 37C2> 39B7> MOD_DTO 14A2< 25C4<> 39A1>
+1_95V_FW_PLLVDD 28D5< 28D7<> 38A3> 1772_CSSN 31C5< 37A2> ATI_SSCLK_IN 18B1< 19B7<> CLKLVDS_LP 19B5> 22A4<> 37C2> 39B7> CPU_TBST_L 5A7> 8B6<> 36D5> FANR_TACH 25B2< 25B2<> HIGH_VCORE_DIV 19A3< LVDS_U1P 19C5> 22A4<> 37C2> 39B7> MOD_SYNC 14A2< 25C3<> 39A1>
+2_5V_CG_MAIN 14C6< 38A3> 1772_CSSP 31C5< 37A2> ATI_SSCLK_UF 18B1<> CLKLVDS_UN 19B5> 22A4<> 37C2> 39B7> CPU_TEA_L 5B3< 8A4<> 8C2< 36D5> FB_4_85V_BU 32A5< HPD_4V_REF 22C3< LVDS_U2N 19B5> 22A4<> 37B2> 39B7> MPIC_CPU_INT_L 5B2< 5B3< 14B5>
+2_5V_GPU 21A7< 21B6< 21D3< 21D7< 21D8< 1772_DCIN 31B5< 38C6> ATI_TESTEN 19B7< CLKLVDS_UP 19B5> 22A4<> 37C2> 39A7> CPU_TSIZ<0> 5A7> 8B6<> FP_PWR_EN 19C6<> 22A6< 22B3<> HPD_BASE 22C1< LVDS_U2P 19B5> 22A4<> 37B2> 39B7> NEC_AMC_TP 26A5<
38B3> 1772_DHI 31B4<> ATI_TMDS_CLKN 19B7> 20B4< COMM_DTR_L 14C2> 25D1<> 39B2> CPU_TSIZ<0..2> 36D5> FP_PWR_EN_L 22B3<> HPD_ON 22C2<> LVDS_U3N_TP 19B5> NEC_AVDD 26D6< 38A3>
+2_5V_GPU_A2VDD 21D4< 21D7< 38C3> 1772_DLO 31B4<> ATI_TMDS_CLKP 19B7> 20B4< COMM_GPIO_L 14C2<> 25D2<> 39C2> CPU_TSIZ<1> 5A7> 8B6<> FWB_TPB0 28A3< HPD_ON_RC 22C2< LVDS_U3P_TP 19B5> NEC_AVSS_F 26A5< 26B4<
+2_5V_GPU_PNLIO 21A5< 38C3> 1772_DLOV 31B4<> 38C6> ATI_TMDS_DN<0> 19B7> 20B4< COMM_RESET_L 14C5<> 25C4<> 39C4> CPU_TSIZ<2> 5A7> 8B6<> FWB_TPB1 28A4< HPD_PWR_SNS_EN 19C7<> 22C3<> MAIN_RESET_L 14C7< 17A7< 17D5< 18C8< 20B8< NEC_CRUN_L 26A7<>
+2_5V_INTREPID 9A8< 10D3< 10D5< 10D7< 10D8< 15D7< 1772_GND 31A5<> 38C6> ATI_TMDS_DN<1> 19B7> 20A4< COMM_RING_DET_L 14B5<> 14C7< 25C3<> 30C6<> 39C4> CPU_TS_L 5C7<> 8D2< 8D6<> 36D5> FWPLL_BYP 28C8<> HPD_PWR_SW 22C2<> 24D6<> 26B8< 30D4<> 30D7< 39C1> NEC_IDSEL 26B7<
16B8< 38D3> 1772_ICHG 31B5<> ATI_TMDS_DN<2> 19B7> 20A4< COMM_RTS_L 14C2> 25D1<> 39B2> CPU_TT<0> 5A7<> 8B6<> FW_BIAS0 28A5<> IAC_FB 31D4< MAX1715_FB2 35B1< 35B4< NEC_IO_RESET_L 26B7< 26B7<
+2_5V_MAIN 38D6> 1772_ICTL 31B5<> ATI_TMDS_DP<0> 19B7> 20B4< COMM_RXD 14C2<> 25D1<> 39B2> CPU_TT<0..4> 36C5> FW_BIAS1 28A5<> IAC_RC_COMP 31D4< MAX1715_GND 35B5<> 35C5< 38C1> NEC_LEFT_USB_OVERCURRENT 24B2<> 26C1< 39D1>
+2_5V_MARVELL 27B8< 27C4<> 38B3> 1772_IINP 31B5< ATI_TMDS_DP<1> 19B7> 20A4< COMM_SHUTDOWN 14C5<> 25C4<> 39C4> CPU_TT<1> 5A7<> 8B6<> FW_BMODE 28B7< INTREPID_ACS_REF 8A6< MAX1715_ON_RC 35C7<> NEC_LEFT_USB_PWREN 24B2<> 26B5<> 39D1>
+2_5V_MARVELL_AVDD 27C4< 38B3> 1772_LDO 31C4<> 38C6> ATI_TMDS_DP<2> 19B7> 20A4< COMM_TRXC 14C2<> 25D2<> 39C2> CPU_TT<2> 5A7<> 8B6<> FW_CORE_ADJ 28C8< INT_AGPPVT 12D4<> MAX1715_REF 35B5<> 38C1> NEC_LEGC 26A7<
+2_5V_SLEEP 38D6> 1772_LX 31B4<> 38C6> ATI_TPVDD_BYP 21D1<> COMM_TXD_L 14C2<> 25D2<> 39C2> CPU_TT<3> 5A7<> 8B6<> FW_CORE_BYP 28C7<> INT_AGP_FB_IN 12C4< 36C1> MAX1715_SKIP 35C4< 38C1> NEC_MAIN_RESET_L 26A7< 26B7<
+2_5V_SLEEP_NECK1 19C4<> 38B3> 1772_REF 31B5<> ATI_VSYNC 19D5<> 22C8< COMP_DISABLE 22C2<> CPU_TT<4> 5A7<> 8B6<> FW_CPS 28B7< INT_AGP_FB_OUT 12C4<> 36C1> MAX1715_TON 35C5< 38C1> NEC_NANDTESTEN_TP 26A5<
+2_5V_SLEEP_NECK2 21A3<> 38B3> 1772_VCTL 31B5< ATI_X1CLK_SKEW<0> 19C2< 19C7<> COMP_ENABLE 22C1<> CPU_VCORE_HI_OC 7B8< 30D4<> 34C8< 34D7< FW_INPUT_PD 28A7< INT_AGP_VREF 12B4< 12D4<> 18D5< 38D3> MAX1715_VCC 35D5< 38C1> NEC_NANDTESTOUT_TP 26A4<>
+3V_ATI_OSC_SLEEP 18D2< 38C3> 1778_BG 19A5<> 38B1> ATI_X1CLK_SKEW<1> 19B2< 19C7<> COMP_RC 32C6< CPU_VCORE_PWR_SEQ 34D8<> FW_LINK_CNTL<0> 13C3<> 28C3< INT_AUDIO_TO_SND 14B2< 25D8< 39C6> MAX1717_AB_SEL 34A7< 34C6< NEC_NC1_TP 26B5<>
C +3V_ATI_SS
+3V_FW
18B2< 38C3>
+3V_CG_PLL_MAIN 14C6< 38A3>
28A3< 28D7<> 29D5< 38A3>
1778_BST
1778_BST_RC
1778_FCB
19A5<> 38B1>
19A4<> 38B1>
19A5< 38B1>
BATTV_HIGH
BATTV_LOW
BATT_14PBUS_EN
31B7<>
31B8<>
31C1<>
CPU_AACK_L
CPU_ADDR<0>
CPU_ADDR<0..31>
5A7< 8B6<> 8C2< 36D5>
5C7<> 8D6<>
36D5>
CPU_VCORE_SEQ
CPU_VCORE_SEQ_L
CPU_VCORE_SLEEP
34D8<
34D8<
5C2< 5D8<> 34C1< 34D2< 38D3> 39B2>
FW_LINK_CNTL<1..0> 37A5>
FW_LINK_CNTL<1> 13C3<> 28C3<
FW_LINK_DATA<0> 13D3<> 28B8<
INT_AUDIO_TO_SND_F 25D7<> 25D7<
INT_CPUFB_IN 8A6< 8B6< 36D1>
INT_CPUFB_IN_NORM 8A4< 36D1>
MAX4172_OUT
MAXBUS_SLEEP
31D4<>
5A2< 5D1< 5D5< 7B7< 7D8< 8B8< 8C3<
8C8< 8D1< 8D8< 15D8< 16D8< 23B3<
NEC_NC2_TP
NEC_OCI<1>
NEC_OCI<2>
26B5<>
26B5< 26C3<
26B5< 26C3<
C
+3V_FW_AVDD 28C6< 38A3> 1778_GND 19A5< 19A7<> 38B1> BATT_14V_GATE 31C1<> CPU_ADDR<1> 5C7<> 8D6<> FW_LINK_DATA<7..0> 37A5> INT_CPUFB_LONG 8A4< 36D1> 23B3< 34D8< 38D3> NEC_OCI<3> 26B5<
+3V_FW_AVDD_PORT0 28C6< 38A3> 1778_ION 19A5< 38B1> BATT_24PBUS_EN 31C2<> CPU_ADDR<2> 5C7<> 8D6<> CPU_VCORE_SLEEP_F 34C2<> FW_LINK_DATA<1> 13D3<> 28B8< INT_CPUFB_OUT 8A6< 8A6<> 36D1> MDI0_PD 27B4< NEC_OCI<4> 26B5<
+3V_FW_AVDD_PORT1 28C6< 38A3> 1778_ITH 19A5<> 38B1> BATT_24V_GATE 31C1<> CPU_ADDR<3> 5C7<> 8D6<> CPU_VCORE_SNUB 34B3< FW_LINK_DATA<2> 13D3<> 28B8< INT_CPUFB_OUT_NORM 8A4< 36D1> MDI1_PD 27B4< NEC_OCI<5> 26B5<
+3V_FW_AVDD_PORT2 28D6< 38A3> 1778_ITH_RC 19A7< 38B1> BATT_CLK 31A4<> 39C3> CPU_ADDR<4> 5C7<> 8D6<> CPU_WT_L 5A7> 8B6<> 36C5> FW_LINK_DATA<3> 13D3<> 28A8< INT_CPUFB_OUT_SHORT 8A5< 36D1> MDI2_PD 27B4< NEC_PCI_INTA_L 26A7< 26B7>
+3V_FW_ESD 29B3<> 29D2<> 38B3> 1778_SHDN_L 19A6< BATT_DATA 31A4<> 39C3> CPU_ADDR<5> 5C7<> 8C6<> CSLOT_ADDR3_SPN 13B7> FW_LINK_DATA<4> 13C3<> 28A8< INT_DDRCLK2_N_TP 9B6<> MDI3_PD 27B3< NEC_PCI_INTB_L 26A7< 26B7>
+3V_FW_ESD_ILIM 29D4< 38B3> 1778_SHDN_L_D3COLD 19A7<> BATT_DIV 31A5< CPU_ADDR<6> 5C7<> 8C6<> CSLOT_ADDR4_SPN 13B7> FW_LINK_DATA<5> 13C3<> 28A8< INT_DDRCLK2_P_TP 9B6<> MDI_M<0> 27B5<> 37D2> NEC_PCI_INTC_L 26A7< 26B7>
+3V_FW_UF 28D7<> 38A3> 1778_TG 19A5<> 38B1> BATT_LOW 31A6<> CPU_ADDR<7> 5C7<> 8C6<> CSLOT_ADDR5_SPN 13B7> FW_LINK_DATA<6> 13C3<> 28A8< INT_DDRCLK5_N_TP 9B6<> MDI_M<1> 27B5<> 37D2> NEC_PCI_PERR_L 26B7<> 26C8<
+3V_GPU 12D1< 18B8< 18C5< 18C7< 18D6< 1778_VCC 19A5<> 38B1> BATT_LOW_L 31B6<> CPU_ADDR<8> 5C7<> 8C6<> CSLOT_ADDR6_SPN 13B7> FW_LINK_DATA<7> 13C3<> 28A8< INT_DDRCLK5_P_TP 9B6<> MDI_M<2> 27B5<> 37D2> NEC_PCI_SERR_L 26B7> 26C8<
19C4< 19C5< 19C7< 19D7< 21A6< 21B1< 1778_VFB 19A2< 19A5< 38B1> 39A1> BATT_NEG 31A4<> 38C6> 39C3> CPU_ADDR<9> 5C7<> 8C6<> CSLOT_ADDR7_SPN 13B7> FW_LINK_LREQ 13C3<> 37A5> INT_ENET_RST_L 14B5<> 27B8< MDI_M<3> 27B5<> 37D2> NEC_PME_L 26A7> 26B7<
38C3> 1778_VIN 19A5< 38B1> BBANG_HRESET_L 23A4< 23C4<> 39C1> CPU_ADDR<10> 5B7<> 8C6<> CSLOT_ADDR8_SPN 13B7> FW_LKON 13C3<> 28B5<> INT_EXTINT3_PU 14B5<> 14B7< MDI_P<0> 27B5<> 37D2> NEC_PPON3_TP 26B5>
+3V_GPU_FLT 21B2< 38C3> 1778_VRNG 19A5< 38B1> BBANG_JTAG_TCK 23B3< 23C4<> CPU_ADDR<11> 5B7<> 8C6<> CSLOT_ADDR9_SPN 13B7> FW_OSC 28A4< 36A1> INT_EXTINT8_PU 14B5<> 14C7< MDI_P<1> 27B5<> 37D2> NEC_PPON4_TP 26B5>
+3V_GPU_SI 20C4< 20C8< 20D8< 3405_MODE 27D5< BBANG_TCK_EN 23B3< CPU_ADDR<12> 5B7<> 8C6<> CSLOT_CE1_L_SPN 13C7> FW_OSC_EN 28A3< INT_EXTINT10_PU 14A7< 14B5<> MDI_P<2> 27B5<> 37D2> NEC_PPON5_TP 26B5>
+3V_HALL_EFFECT 23C6<> 38B6> 39C4> 3405_VFB 27D4<> BCKFD_PROT_EN_L 31C6<> CPU_ADDR<13> 5B7<> 8C6<> CSLOT_CE2_L_SPN 13C7> FW_PC_PD 28B7< INT_EXTINT11_PU 14A7< 14B5<> MDI_P<3> 27B5<> 37D2> NEC_RIGHT_USB_OVERCURRENT 26C1< 32A7<> 39C1>
+3V_INTREPID_USB 14C3< 38D3> 3707_FCB 33C5< BCKFD_PROT_GATE 31D6<> CPU_ADDR<14> 5B7<> 8C6<> CSLOT_IORD_L_SPN 13C7> FW_PC_PU 28B7< INT_EXTINT12_PU 14A7< 14B5<> MEM_ADDR<0> 9B5< 9D6<> NEC_RIGHT_USB_PWREN 26B5<> 32A7<> 39C1>
+3V_LCD 22B4<> 38B6> 3707_FSET 33C5< BRIGHT_PWM 22A1<> 39A7> CPU_ADDR<15> 5B7<> 8C6<> CSLOT_IOWAIT_L_PU 13C7< FW_PHY_CNTL<0> 28B4<> 28C3< INT_EXTINT13_PU 14B5<> 14B7< MEM_ADDR<12..0> 36A5> NEC_RREF 26B5<>
+3V_LCD_SW 22A4<> 38B6> 3707_INTVCC 33D4<> 38D1> BRIGHT_PWM_UF 22A2<> CPU_ADDR<16> 5B7<> 8C6<> CSLOT_IOWR_L_SPN 13C7> FW_PHY_CNTL<1..0> 37A5> INT_EXTINT14_PU 14B5<> 14C7< MEM_ADDR<1> 9B5< 9D6<> NEC_SMI_L_TP 26A7>
+3V_MAIN 38D6> 3707_SGND 33B5<> 38D1> BT_USB_DM 14B1< 24B2<> 37B2> 39B6> CPU_ADDR<17> 5B7<> 8C6<> CSLOT_OE_L_SPN 13C7> FW_PHY_CNTL<1> 28B4<> 28C3< INT_EXTINT16_PU 14B5<> 14B7< MEM_ADDR<2> 9B5< 9D6<> NEC_USB_DAM 26B4< 26C3<> 37B2>
+3V_NEC_VDD 26D7< 26D7< 38A3> 3707_STBY 33C5<> BT_USB_DP 14C1< 24B2<> 37B2> 39B6> CPU_ADDR<18> 5B7<> 8C6<> CSLOT_WE_L_SPN 13C7> FW_PHY_DATA<0> 28B8<> INT_GPIO1_PU 14C5<> 14C7< 34C8< MEM_ADDR<3> 9B5< 9D6<> NEC_USB_DAP 26A4< 26C3<> 37B2>
+3V_PMU 38D6> 39A2> A29_CLS_ADJ 31A5<> CAPSLOCK_LED 23A8< CPU_ADDR<19> 5B7<> 8C6<> CURRENT_THRESHOLD 31C4< FW_PHY_DATA<7..0> 37A5> INT_GPIO9_PU 14A7< 14B5<> MEM_ADDR<4> 9B5< 9D6<> NEC_USB_DBM 26A4< 26C3<> 37B2>
+3V_PMU_AVCC 25A4< 30B6< 30D5<> 38C6> A29_CURRENT_ADJ 31C4<> CAPSLOCK_LED_L 23B8< 30C7< CPU_ADDR<20> 5B7<> 8C6<> CY25811_S0 18B2< FW_PHY_DATA<1> 28B8<> INT_GPIO12_PU 14B5<> 14B7< MEM_ADDR<5> 9B5< 9D6<> NEC_USB_DBP 26A4< 26C3<> 37B2>
+3V_PMU_ESR 32A2< 38C6> A29_DETECT 30A2< 31A5<> 31C4<> CBUS_ADDR<0> 17B1<> 17B4> CPU_ADDR<21> 5B7<> 8C6<> CY25811_S1 18B2< FW_PHY_DATA<2> 28B8<> INT_GPIO15_PU 14B5<> 14C7< MEM_ADDR<6> 9B5< 9D6<> NEC_USB_RSDM1 26C5<> 37B2>
+3V_PMU_RESET 30B7< 34A3<> A29_DET_L 30A3< CBUS_ADDR<1> 17B1<> 17B4> CPU_ADDR<22> 5B7<> 8C6<> DCDC_EN 19A7<> 29C7<> 32B7<> 33B6<> 34C8<> FW_PHY_DATA<3> 28A8<> INT_I2C_CLK0 11A3<> 11A8<> 13C2< 13C3<> 23D2< MEM_ADDR<7> 9B5< 9D6<> NEC_USB_RSDM2 26C5<> 37B2>
+3V_SI_AVCC 20C7< 38B3> AB_SEL_LOW 34A6<> CBUS_ADDR<2> 17B1<> 17B4> CPU_ADDR<23> 5B7<> 8C6<> 39C1> FW_PHY_DATA<4> 28A8<> 23D4<> 39B8> MEM_ADDR<8> 9B5< 9D6<> NEC_USB_RSDP1 26C5<> 37B2>
+3V_SI_PLLVCC 20C7< 38B3> AC_DIV 31C8< CBUS_ADDR<3> 17B1<> 17B4> CPU_ADDR<24> 5B7<> 8C6<> DCDC_EN_L 33B6< 33B7<> 35C7<> FW_PHY_DATA<5> 28A8<> INT_I2C_CLK1 13C2< 13C3<> 14B7< 25B4< 39B8> MEM_ADDR<9> 9A5< 9D6<> NEC_USB_RSDP2 26C5<> 37B2>
+3V_SI_VCC 20C6< 38B3> AC_ENABLE_GATE 31D6<> CBUS_ADDR<4> 17B1<> 17B4> CPU_ADDR<25> 5B7<> 8C6<> DDC_CLK_ISO 22D4<> FW_PHY_DATA<6> 28A8<> INT_I2C_CLK2 14A2<> 25C4<> 25D7<> 39C6> MEM_ADDR<10> 9A5< 9D6<> NEC_XT1 26D5< 36B1>
+3V_SLEEP 38D6> AC_ENABLE_L 31C6<> CBUS_ADDR<5> 17B1<> 17B4> CPU_ADDR<26> 5B7<> 8C6<> DDR_VREF 11D1< 11D3<> 11D5<> 11D6<> 11D8<> FW_PHY_DATA<7> 28A8<> INT_I2C_DATA0 11A3<> 11A8<> 13C2< 13C3<> 23D2<> MEM_ADDR<11> 9A5< 9D6<> NEC_XT2 26D5<> 36B1>
+3V_SLEEP_NECK 21A3<> 38B3> AC_GTR_18V 31C4<> CBUS_ADDR<6> 17B1<> 17B4> CPU_ADDR<27> 5B7<> 8C6<> 38D3> FW_PHY_LPS 13C3<> 28B8< 23D4<> 39B8> MEM_ADDR<12> 9A5< 9D6<> NEC_XT2_R 26D4<
+3V_SLP_OK_L 33B4<> AC_IN 27B8<> 29C7< 30B3< 31C5<> 31C7<> CBUS_ADDR<7> 17B1<> 17B4> CPU_ADDR<28> 5B7<> 8C6<> DVI_DDC_CLK 22D4<> FW_PHY_LREQ 13C2< 28B8< 37A5> INT_I2C_DATA1 13B2< 13C3<> 14B7< 25B4<> 39B8> MEM_BA<0> 9A5< 9D6<> NTEST1_TP 26B5<
+3V_SLP_ON 33A5<> AC_IN_FW_CNTL 29C7<> CBUS_ADDR<8> 17B1<> 17B4> CPU_ADDR<29> 5B7<> 8C6<> DVI_DDC_CLK_UF 22C5<> 22D3<> 39C7> FW_PHY_PD 14C5< 28B8< INT_I2C_DATA2 14A2<> 25C4<> 25C7<> 39C6> MEM_BA<1..0> 36A5> NUMLOCK_LED 23B8<
+4_6V_BU 32A3<> 33B6< 38C6> AC_IN_L 31C2<> 31C6<> CBUS_ADDR<9> 17B1<> 17B4> CPU_ADDR<30> 5B7<> 8C6<> DVI_DDC_DATA 22C4<> FW_PHY_PD_INT 14A7< 14C5<> INT_JTAG_TEI 13C2< 13C5< MEM_BA<1> 9A5< 9C6<> NUMLOCK_LED_L 23B8< 30C7<
+4_85V_ESR 32A4< 38C6> AC_IN_L_RC 31C2<> CBUS_ADDR<10> 17B4> 17C1<> CPU_ADDR<31> 5B7<> 8B6<> DVI_DDC_DATA_UF 22C5<> 39C7> FW_PHY_RESET_L 28A8< INT_MEM_REF_H 9B6< 38D3> MEM_CAS_L 9A5< 9C6<> 36A5> OVER_18V_ADJ 31C3<>
+4_85V_RAW 30B4< 32A4<> 38C6> ADAPTER_DET 30A4< 31D8<> 39C2> CBUS_ADDR<11> 17B1<> 17B4> CPU_ARTRY_L 5A7<> 8B6<> 8D2< 36D5> DVI_HPD 22C4<> FW_PINT 13C3<> 28B4> 37A5> INT_MEM_VREF 9A7< 9B6<> 38D3> MEM_CKE<0> 9B6<> 9C5< PCI1510_VR_EN_L 17C7<
+5V_DDC_SLEEP 22D3<> 22D5<> 38B6> 39A2> ADAPTER_I_REG 31D3<> CBUS_ADDR<12> 17B1<> 17B4> CPU_AVDD 5C3< 38D3> DVI_HPD_DIV 22C3< FW_PLL_ADJ 28C7< INT_MOD_BITCLK_UF 14A3<> 14A7< MEM_CKE<3..0> 36A5> PCI_AD<0> 9C3< 12D6<> 17C7<> 24B5<> 26D7<>
+5V_DDC_SLEEP_UF 22D6< 38B6> ADT7460_ADR_EN_L 25B3<> CBUS_ADDR<13> 17B1<> 17B4> CPU_BG_L 5C7< 8C2< 8D6<> 36D5> DVI_HPD_UF 22C3< 22C5<> 39C7> FW_PORT1_SEL 28B6< INT_MOD_CLKOUT_UF 14A3<> 14B7< MEM_CKE<1> 9B6<> 9C5< 39B6>
+5V_HD_SLEEP 24D1<> 33A7<> 38C6> ADT7460_FAN1_PWM 25B3<> CBUS_ADDR<14> 17B1<> 17B4> CPU_BR_L 5C7> 8D2< 8D6< 36D5> DVI_TRUN_ON_ILIM 22D2< FW_PWREN_L 29C6<> INT_MOD_DTI 14A2< 25C3<> 39B1> MEM_CKE<2> 9B6<> 9C5< PCI_AD<31..0> 37C5>
+5V_INV_SW 22B2<> 38B6> 39D1> ADT7460_FAN2_PWM 25B3<> CBUS_ADDR<15> 17B1<> 17B4> CPU_BUS_VSEL 5C3< 7A6< DVI_TURN_ON 22D3<> FW_PWR_GATE 29D6<> INT_MOD_DTI_UF 14A7< MEM_CKE<3> 9B6<> 9C5< PCI_AD<1> 9C3< 12D6<> 17C7<> 24B6<> 26D7<>
+5V_INV_UF_SW 22B2<> 38B6> ADT7460_THERM 25A5<> 25B3<> CBUS_ADDR<16> 17B1<> 17B4< CPU_CHKSTP_OUT_L 5B3<> 5C2< 39D8> DVI_TURN_ON_BASE 22D2< FW_R0 28A5<> INT_MOD_DTO_UF 14A3<> 14B7< MEM_CS_L<0> 9C5< 9C6<> 39A6>
+5V_MAIN 38D6> ADT7460_VCC 25C4< CBUS_ADDR<17> 17B2<> 17B4> CPU_CHKS_L 5A3< 5D2< EEPROM_ADDR 23D4< FW_R1 28A5<> INT_MOD_SYNC_UF 14A3<> 14A7< MEM_CS_L<3..0> 36A5> PCI_AD<2> 9C3< 12D6<> 17C7<> 24C5<> 26D7<>
+5V_SLEEP 38D6> ADT7460_VCORE_MON 5C8<> 25B4<> CBUS_ADDR<18> 17B2<> 17B4> CPU_CI_L 5A7> 8B6<> 36D5> EEPROM_WP_PD 23D3<> FW_TESTM 28A7< INT_PCI_FB_IN 12C7< 36C1> MEM_CS_L<1> 9C5< 9C6<> 39A6>
+5V_SOUND_SLEEP 38B6> AGP8X_DET_PU 18C6<> CBUS_ADDR<19> 17B2<> 17B4> CPU_CLKOUT_SPN 5C3> EIDE_ADDR<0> 13B7> 24B8< FW_TPA0N 28B1<> 29C4<> 37D2> INT_PCI_FB_OUT 12C7<> 36C1> MEM_CS_L<2> 9C5< 9C6<> PCI_AD<3> 9C3< 12D6<> 17C7<> 24C6<> 26C7<>
+5V_TPAD_SLEEP 23C7<> 38B6> 39C4> AGP_AD<0> 12D2<> 18C7<> CBUS_ADDR<20> 17B2<> 17B4> CPU_CLK_EN 8A6< 30C4<> EIDE_ADDR<2..0> 37B5> FW_TPA0N_CONN 29C3<> INT_PEND_PROC_INT 14A5> 30C4<> MEM_CS_L<3> 9C5< 9C6<> 39A6>
B +12_8V_INV
+24V_PBUS
+ADAPTER
22B1<> 38B6> 39A2>
38D6> 39B2>
31D8<> 32B7< 38D6>
AGP_AD<15..0>
AGP_AD<1>
AGP_AD<2>
37D5>
12C2<> 18C7<>
12C2<> 18C7<>
CBUS_ADDR<21>
CBUS_ADDR<22>
CBUS_ADDR<23>
17B2<> 17B4>
17A4> 17B2<>
17A4> 17B2<>
CPU_DATA<0>
CPU_DATA<0..31>
CPU_DATA<1>
6D8<> 8D4<>
36D5>
6D8<> 8D4<>
EIDE_ADDR<1>
EIDE_ADDR<2>
EIDE_CS0_L
13B7> 24B8<
13B7> 24B8<
13B7> 24B8< 37B5>
FW_TPA0P
FW_TPA0P_CONN
FW_TPA1N
28B1<> 29C4<> 37D2>
29C3<>
28B1<> 29A4<> 37C2>
INT_PROC_SLEEP_REQ_L 14A5< 30B4<>
INT_PU_RESET_L
INT_REF_CLK_IN
13D3< 25D4<> 30A2< 30C4<>
14A5< 14B5< 36C1>
MEM_DATA<0>
MEM_DATA<7..0>
MEM_DATA<1>
9D8<> 10C7<>
36C5>
9D8<> 10C7<>
PCI_AD<4>
PCI_AD<5>
9C3< 12D6<> 17C7<> 24C5<> 26C7<>
39A6>
9C3< 12D6<> 17C7<> 24C6<> 26C7<>
B
+ADAPTER_ILIM 32B6<> 38C6> AGP_AD<3> 12C2<> 18C7<> CBUS_ADDR<24> 17A4> 17B2<> CPU_DATA<2> 6D8<> 8D4<> EIDE_CS1_L 13B7> 24B8< 37B5> FW_TPA1P 28B1<> 29A4<> 37C2> INT_REF_CLK_OUT 14A5> 14B7< 36C1> MEM_DATA<2> 9D8<> 10C7<> 39A6>
+ADAPTER_OR_BATT 32A5<> 38C6> AGP_AD<4> 12C2<> 18C7<> CBUS_ADDR<25> 17A4> 17B2<> CPU_DATA<3> 6D8<> 8D4<> EIDE_DATA<0> 13C7<> 24C8< FW_TPB0N 28B1<> 29C4<> 37D2> INT_RESET_L 9B3< 13D3< 30C7< 30D4<> MEM_DATA<3> 9D8<> 10C7<> PCI_AD<6> 9C3< 12C6<> 17C7<> 24C5<> 26C7<>
+ADAPTER_SENSE 31D5<> 38C6> AGP_AD<5> 12C2<> 18C7<> CBUS_ADDR_16_UF 17B5<> CPU_DATA<4> 6D8<> 8D4<> EIDE_DATA<15..0> 37B5> FW_TPB0N_CONN 29C3<> INT_ROM_CS_L 12A6< 12C7> MEM_DATA<4> 9D8<> 10C7<> 39A6>
+ADAPTER_SW 31D6<> 38C6> AGP_AD<6> 12C2<> 18C7<> CBUS_BVD1_L 17B2<> 17C4< CPU_DATA<5> 6D8<> 8D4<> EIDE_DATA<1> 13C7<> 24C8< FW_TPB0P 28B1<> 29C4<> 37D2> INT_ROM_OE_L 12A6< 12C7> MEM_DATA<5> 9D8<> 10C7<> PCI_AD<7> 9C3< 12C6<> 17C7<> 24C6<> 26C7<>
+BATT 38D6> AGP_AD<7> 12C2<> 18C7<> CBUS_BVD2_L 17B2<> 17C4< CPU_DATA<6> 6D8<> 8D4<> EIDE_DATA<2> 13C7<> 24C8< FW_TPB0P_CONN 29C3<> INT_ROM_RW_L 12A6< 12C7> MEM_DATA<6> 9D8<> 10C7<> 39D5>
+BATT_14V_FUSE 31D1<> 38C6> AGP_AD<8> 12C2<> 18C7<> CBUS_CE1_L 17C1<> 17C4> CPU_DATA<7> 6D8<> 8D4<> EIDE_DATA<3> 13C7<> 24C8< FW_TPB1N 28B1<> 29A4<> 37C2> INT_SND_CLKOUT 14A3<> MEM_DATA<7> 9D8<> 10C7<> PCI_AD<8> 9C3< 12C6<> 17C7<> 24C6<> 26C7<>
+BATT_24V_FUSE 31B1< 31D2<> 38C6> AGP_AD<9> 12C2<> 18C7<> CBUS_CE2_L 17B4> 17C2<> CPU_DATA<8> 6D8<> 8D4<> EIDE_DATA<4> 13C7<> 24C8< FW_TPB1P 28B1<> 29A4<> 37C2> INT_SND_SCLK 14A3<> MEM_DATA<8> 9D8<> 10C7<> 39D5>
+BATT_POS 31A4<> 38C6> 39C3> AGP_AD<10> 12C2<> 18C7<> CBUS_DATA<0> 17A1<> 17A4<> CPU_DATA<9> 6C8<> 8D4<> EIDE_DATA<5> 13B7<> 24B8< FW_TPB2_PD 28A5<> INT_SND_SYNC 14B3<> MEM_DATA<15..8> 36C5> PCI_AD<9> 9C3< 12C6<> 17C7<> 24C5<> 26C7<>
+BATT_RSNS 31B2< 38C6> AGP_AD<11> 12C2<> 18C7<> CBUS_DATA<1> 17A1<> 17A4<> CPU_DATA<10> 6C8<> 8D4<> EIDE_DATA<6> 13B7<> 24C8< FW_TPI0N 37C2> INT_SND_TO_AUDIO 14B3<> MEM_DATA<9> 9D8<> 10C7<> 39D5>
+BATT_VSNS 31A4< 38C6> AGP_AD<12> 12C2<> 18C7<> CBUS_DATA<2> 17A1<> 17A4<> CPU_DATA<11> 6C8<> 8D4<> EIDE_DATA<7> 13B7<> 24C8< FW_TPI0P 37C2> INT_SUSPEND_ACK_L 8B6> 30B6<> MEM_DATA<10> 9D8<> 10C7<> PCI_AD<10> 9C3< 12C6<> 17C7<> 24C6<> 26C7<>
+FW_FUSE 29D7<> 38A3> AGP_AD<13> 12C2<> 18C7<> CBUS_DATA<3> 17A4<> 17C1<> CPU_DATA<12> 6C8<> 8C4<> EIDE_DATA<8> 13B7<> 24D8< FW_TPI1N 29A3<> 37C2> 39D2> INT_SUSPEND_REQ_L 8B6< 30B6<> 30C7< MEM_DATA<11> 9D8<> 10C7<> 39D5>
+FW_PWR_OR 28B8< 28D8<> 29D5<> 38A3> AGP_AD<14> 12C2<> 18C7<> CBUS_DATA<4> 17A4<> 17C1<> CPU_DATA<13> 6C8<> 8C4<> EIDE_DATA<9> 13B7<> 24D8< FW_TPI1P 29A3<> 37C2> 39D2> INT_TST_MONIN_PD 13C2< 13C5< MEM_DATA<12> 9D8<> 10B7<> PCI_AD<11> 9C3< 12C6<> 17C7<> 24C5<> 26C7<>
+FW_PWR_PORTA 29C5< 38A3> AGP_AD<15> 12C2<> 18C7<> CBUS_DATA<5> 17A4<> 17C1<> CPU_DATA<14> 6C8<> 8C4<> EIDE_DATA<10> 13B7<> 24D8< FW_TPO0N 37C2> INT_TST_MONOUT_TP 13C5> MEM_DATA<13> 9C8<> 10B7<> 39D5>
+FW_SW 29D5<> 38A3> AGP_AD<16> 12C2<> 18C7<> CBUS_DATA<6> 17A4<> 17C1<> CPU_DATA<15> 6C8<> 8C4<> EIDE_DATA<11> 13B7<> 24D8< FW_TPO0P 37C2> INT_TST_PLLEN_PD 13C5< 13D2< MEM_DATA<14> 9C8<> 10B7<> PCI_AD<12> 9C3< 12C6<> 17C7<> 24C6<> 26C7<>
+FW_VP0 29C2<> 38A3> AGP_AD<31..16> 37D5> CBUS_DATA<7> 17A4<> 17C1<> CPU_DATA<16> 6C8<> 8C4<> EIDE_DATA<12> 13B7<> 24D8< FW_TPO0R 29C2<> 38A3> 39A3> INT_WATCHDOG_L 14A5> 30C6<> MEM_DATA<15> 9C8<> 10B7<> 39D5>
+FW_VP1 29A3<> 38A3> AGP_AD<17> 12C2<> 18C7<> CBUS_DATA<8> 17A2<> 17A4<> CPU_DATA<17> 6C8<> 8C4<> EIDE_DATA<13> 13B7<> 24C8< FW_TPO1N 29A3<> 37C2> 39D2> INV_ON_PWM 19C6<> 22A3< MEM_DATA<16> 9C8<> 10C5<> PCI_AD<13> 9C3< 12C6<> 17C7<> 24C5<> 26C7<>
+GPU_MCLK 21C7< 21D4< 38C3> AGP_AD<18> 12C2<> 18C7<> CBUS_DATA<9> 17A2<> 17A4<> CPU_DATA<18> 6C8<> 8C4<> EIDE_DATA<14> 13B7<> 24C8< FW_TPO1P 29A3<> 37C2> 39D2> IO_RESET_L 17A7< 23D6< 26B8< 27B8< 30C6<> MEM_DATA<31..16> 36C5> 39C5>
+GPU_MEM 18A6<> 18B8< 21B4< 21B7< 21C6< AGP_AD<19> 12C2<> 18C7<> CBUS_DATA<10> 17A2<> 17A4<> CPU_DATA<19> 6C8<> 8C4<> EIDE_DATA<15> 13B7<> 24C8< FW_VGND0 29C2<> 38A3> 30D7< MEM_DATA<17> 9C8<> 10C5<> PCI_AD<14> 9C3< 12C6<> 17C7<> 24C6<> 26C7<>
21C8< 21D2< 38C3> AGP_AD<20> 12C2<> 18C7<> CBUS_DATA<11> 17A4<> 17C2<> CPU_DATA<20> 6C8<> 8C4<> EIDE_DMACK_L 13A7<> 24A8< 37B5> FW_VGND1 29A3<> 38A3> JTAG_ASIC_TCK 13C5< 13D2< 27A5< 39D8> MEM_DATA<18> 9C8<> 10C5<> 39C5>
+GPU_MEMCORE 21C5< 38C3> AGP_AD<21> 12C2<> 18C7<> CBUS_DATA<12> 17A4<> 17C2<> CPU_DATA<21> 6C8<> 8C4<> EIDE_DMARQ 13A7< 24B8< 37B5> FW_VREG_PD 28A7< JTAG_ASIC_TDI 13C5< 13D2< 39D8> MEM_DATA<19> 9C8<> 10C5<> PCI_AD<15> 9C3< 12C6<> 17C7<> 24C5<> 26C7<>
+GPU_VDD15_NECK 19B5<> 38B3> AGP_AD<22> 12C2<> 18C7<> CBUS_DATA<13> 17A4<> 17C2<> CPU_DATA<22> 6C8<> 8C4<> EIDE_INT 13A7< 24A8< 37B5> FW_XI 28A5<> 36A1> JTAG_ASIC_TDO_TP 27A5> 39D8> MEM_DATA<20> 9C8<> 10C5<> 39C5>
+GPU_VDD15_UF 19B5<> 19D4<> 38C3> AGP_AD<23> 12C2<> 18C7<> CBUS_DATA<14> 17A4<> 17C2<> CPU_DATA<23> 6C8<> 8C4<> EIDE_IOCHRDY 13B7< 24A8< 37B5> GAIN_SETTING2 23C7<> JTAG_ASIC_TMS 13C5< 13D2< 27A5< 39D8> MEM_DATA<21> 9C8<> 10C5<> PCI_AD<16> 9C3< 12C6<> 17C7<> 24C5<> 26C7<>
+HD_LOGIC_SLEEP 24C2<> 38C6> AGP_AD<24> 12C2<> 18C7<> CBUS_DATA<15> 17A4<> 17C2<> CPU_DATA<24> 6C8<> 8C4<> EIDE_OPTICAL_ADDR<0> 24A5<> 24B7< 39A4> GPU_AGP_TEST 18D6< JTAG_ASIC_TRST_L 13C2< 13C5< 27A5< 39D8> MEM_DATA<22> 9C8<> 10C5<> 39C5>
+PBUS 38D6> 39B2> AGP_AD<25> 12C2<> 18D7<> CBUS_DET_1_L 17C2<> 17C4< 39B8> CPU_DATA<25> 6C8<> 8C4<> EIDE_OPTICAL_ADDR<2..0> 37B5> GPU_AUXWIN 19C5<> JTAG_CPU_TCK 5B2< 5B3< 23B2> 39C8> MEM_DATA<23> 9C8<> 10C5<> PCI_AD<17> 9C3< 12C6<> 17C7<> 24C6<> 26C7<>
+VCC_CBUS_SW 17B1<> 17B2<> 17D2<> 38D3> AGP_AD<26> 12C2<> 18D7<> CBUS_DET_2_L 17A2<> 17C4< 39B8> CPU_DATA<26> 6C8<> 8C4<> EIDE_OPTICAL_ADDR<1> 24A5<> 24B7< 39A4> GPU_B 19D6<> 22D8< JTAG_CPU_TDI 5B2< 5C3< 23D4<> 39C8> MEM_DATA<24> 9C8<> 10C5<> 39C5>
+VPP_CBUS_SW 17B1<> 17B2<> 17D2<> 38C3> AGP_AD<27> 12B2<> 18D7<> CBUS_INPACK_L 17B2<> 17B4< CPU_DATA<27> 6C8<> 8C4<> EIDE_OPTICAL_ADDR<2> 24A6<> 24B7< 39A4> GPU_C 19D6<> 22A8< JTAG_CPU_TDO_TP 5C3> 39C8> MEM_DATA<25> 9C8<> 10C5<> PCI_AD<18> 9C3< 12C6<> 17B7<> 24C5<> 24D4<
1V20_REF 31C7< 32C8< 38D1> AGP_AD<28> 12B2<> 18D7<> CBUS_INT_L 14B5<> 14B7< 17A7<> CPU_DATA<28> 6C8<> 8C4<> EIDE_OPTICAL_CS0_L 24A5<> 24B7< 37B5> 39D4> GPU_CLK27M_OUT 36C1> JTAG_CPU_TMS 5B2< 5B3< 23C4<> 39C8> MEM_DATA<26> 9C8<> 10C5<> 26C7<> 39C5>
1V65_REF 31A5< AGP_AD<29> 12B2<> 18D7<> CBUS_IORD_L 17B2<> 17C4> CPU_DATA<29> 6C8<> 8C4<> EIDE_OPTICAL_CS1_L 24A6<> 24B7< 37B5> 39D4> GPU_CLK27M_UF 36C1> JTAG_CPU_TRST_L 5A3< 5B3< 23D4<> 39B1> 39C8> MEM_DATA<27> 9C8<> 10C5<> PCI_AD<19> 9C3< 12C6<> 17B7<> 24C6<> 26C7<>
1_5V_2_5V_OK 35C5> 38B1> AGP_AD<30> 12B2<> 18D7<> CBUS_IOWR_L 17B2<> 17C4> CPU_DATA<30> 6C8<> 8C4<> EIDE_OPTICAL_DATA<0> 24A5<> 24C7< 39C4> GPU_COMP 19D6<> 22A8< JTAG_ENET_TDI 13C5> 13D2< 27A5< MEM_DATA<28> 9C8<> 10C5<> 39C5>
1_5V_BOOST 35C6<> 38C1> AGP_AD<31> 12B2<> 18D7<> CBUS_MFUNC1_PD 17A7<> 17A7< CPU_DATA<31> 6C8<> 8C4<> EIDE_OPTICAL_DATA<15..0> 37B5> GPU_CORE_OK 19A6<> 19D4<> 21D2<> 21D7<> KBD_CAPSLOCK_LED 23A7<> 39B4> MEM_DATA<29> 9C8<> 10B5<> PCI_AD<20> 9B3< 12C6<> 17B7<> 24C5<> 26C7<>
1_5V_BST 35C5<> 38C1> AGP_AD_STB<0> 12A2<> 12B2< 18D6<> 37D5> CBUS_MFUNC2_PD 17A7<> 17A7< CPU_DATA<32> 6C8<> 8C4<> 8D8< EIDE_OPTICAL_DATA<1> 24A5<> 24C7< 39C4> GPU_DVI_DDC_CLK 19C5<> 22D3<> KBD_COMMAND_L 23A5< 23A7<> 30C6<> 39B4> MEM_DATA<30> 9C8<> 10B5<> 39C5>
1_5V_DH 35C5<> 38C1> AGP_AD_STB<1> 12A2<> 12B2< 18D6<> 37D5> CBUS_MFUNC3_PD 17A7<> 17A7< CPU_DATA<32..63> 36D5> EIDE_OPTICAL_DATA<2> 24A5<> 24C7< 39C4> GPU_DVI_DDC_DATA 19C5<> 22C3<> KBD_CONTROL_L 23A5< 23A7<> 30A8< 30C6<> 39B4> MEM_DATA<31> 9C8<> 10B5<> PCI_AD<21> 12C6<> 17B7<> 24C6<> 26C7<> 39C5>
1_5V_DL 35B5<> 38C1> AGP_AD_STB_L<0> 12A2<> 12B2< 18D6<> 37D5> CBUS_MFUNC4_PD 17A7<> 17A7< CPU_DATA<33> 6C8<> 8C4<> 8D8< EIDE_OPTICAL_DATA<3> 24A5<> 24C7< 39C4> GPU_DVOD<0> 19D7<> 20B7< KBD_FUNCTION_L 23A5< 23A7<> 30B6<> 39B4> MEM_DATA<32> 9C8<> 10C3<> PCI_AD<22> 12C6<> 17B7<> 24C5<> 26C7<> 39B5>
1_5V_FB 35B5< 35B7< 38C1> AGP_AD_STB_L<1> 12A2< 12A2<> 18D6<> 37D5> CBUS_MFUNC5_PD 17A7<> 17A7< CPU_DATA<34> 6C8<> 8C4<> 8D8< EIDE_OPTICAL_DATA<4> 24A5<> 24C7< 39C4> GPU_DVOD<0..11> 37D5> KBD_ID 23A7<> 23B5< 30B6<> 39C4> MEM_DATA<47..32> 36B5> PCI_AD<23> 12C6<> 17B7<> 24C6<> 26C7<> 39B5>
1_5V_ILIM 35C5<> 38C1> AGP_ATI_RESET_L 18B7< CBUS_MFUNC6_PD 17A7< 17A7<> CPU_DATA<35> 6C8<> 8C4<> 8D8< EIDE_OPTICAL_DATA<5> 24A5<> 24B7< 39C4> GPU_DVOD<1> 19D7<> 20B7< KBD_LED1_OUT 23A5<> 23A7<> 38B6> 39C2> MEM_DATA<33> 9C8<> 10C3<> PCI_AD<24> 9C1<> 12C6<> 17B7<> 24C5<> 26C7<>
1_5V_LX 35B5<> 38C1> AGP_ATI_VREF 18B7< CBUS_OE_L 17C1<> 17C4> CPU_DATA<36> 6B8<> 8C4<> 8D8< EIDE_OPTICAL_DATA<6> 24A5<> 24C7< 39C4> GPU_DVOD<2> 19D7<> 20B7< KBD_LED2_OUT 23A5<> 23A7<> 38B6> 39C2> MEM_DATA<34> 9C8<> 10C3<> 39B5>
1_5V_SLEEP_EN_L 35C7<> 35D7<> AGP_ATI_VREFG 18B7< CBUS_PCI_GNT_L 12D7<> 17A7< CPU_DATA<37> 6B8<> 8C4<> 8D8< EIDE_OPTICAL_DATA<7> 24A5<> 24C7< 39B4> GPU_DVOD<3> 19D7<> 20B7< KBD_LED_EN 23A5<> MEM_DATA<35> 9C8<> 10C3<> PCI_AD<25> 9C1<> 12C6<> 17B7<> 24C6<> 26C7<>
1_8V_SLEEP_PWREN_L 35A3<> AGP_BUSY_L 12C4<> 12D2< 18D6> CBUS_PCI_IDSEL 17B7< CPU_DATA<38> 6B8<> 8B4<> 8D8< EIDE_OPTICAL_DATA<8> 24A6<> 24D7< 39B4> GPU_DVOD<4> 19D7<> 20B7< KBD_LED_SET 23A5< MEM_DATA<36> 9C8<> 10C3<> 39B5>
1_8V_SW 35A5<> 38A1> AGP_CBE<0> 12B2<> 18B7<> CBUS_PCI_PERR_L 17B7<> 17D7< CPU_DATA<39> 6B8<> 8B4<> 8D8< EIDE_OPTICAL_DATA<9> 24A6<> 24D7< 39B4> GPU_DVOD<5> 19D7<> 20A7< KBD_NUMLOCK_LED 23B7<> 39C3> MEM_DATA<37> 9C8<> 10C3<> PCI_AD<26> 9C1<> 12C6<> 17B7<> 24C5<> 26C7<>
1_8V_VFB 38A1> AGP_CBE<1..0> 37D5> CBUS_PCI_REQ_L 12A7< 12D7<> 17A7> CPU_DATA<40> 6B8<> 8B4<> 8C8< EIDE_OPTICAL_DATA<10> 24A6<> 24D7< 39B4> GPU_DVOD<6> 19D7<> 20A7< KBD_OPTION_L 23A5< 23B7<> 30A8< 30B6<> 39B4> MEM_DATA<38> 9C8<> 10C3<> 39B5>
A 2_5V_BOOST
2_5V_BST
2_5V_DH
35C4<> 38D1>
35C4<> 38D1>
35C4<> 38D1>
AGP_CBE<1>
AGP_CBE<2>
AGP_CBE<3..2>
12B2<> 18B7<>
12B2<> 18B7<>
37D5>
CBUS_PCI_RESET_L
CBUS_PCI_SERR_L
CBUS_READY
17A7<
17B7> 17D7<
17B1<> 17C4<
CPU_DATA<41>
CPU_DATA<42>
CPU_DATA<43>
6B8<> 8B4<> 8C8<
6B8<> 8B4<> 8C8<
6B8<> 8B4<> 8C8<
EIDE_OPTICAL_DATA<11> 24A6<> 24D7< 39B4>
EIDE_OPTICAL_DATA<12> 24A6<> 24D7< 39B4>
EIDE_OPTICAL_DATA<13> 24A6<> 24C7< 39B4>
GPU_DVOD<7>
GPU_DVOD<8>
GPU_DVOD<9>
19D7<> 20A7<
19D7<> 20A7<
19D7<> 20A7<
KBD_SHIFT_L
KBD_X<0>
KBD_X<1>
23A5< 23B7<> 30A8< 30C6<> 39B4>
23A5< 23B7<> 30C6<> 39B4>
23A5< 23B7<> 30C6<> 39B4>
MEM_DATA<39>
MEM_DATA<40>
MEM_DATA<41>
9B8<> 10C3<>
9B8<> 10C3<>
9B8<> 10C3<>
PCI_AD<27>
PCI_AD<28>
9C1<> 12C6<> 17B7<> 24D6<> 26C8<>
39B5>
9C1<> 12C6<> 17B7<> 24C5<> 26C7<>
A
2_5V_DL 35B4<> 38D1> AGP_CBE<3> 12B2<> 18C7<> CBUS_REG_L 17B2<> 17C4> CPU_DATA<44> 6B8<> 8B4<> 8C8< EIDE_OPTICAL_DATA<14> 24A6<> 24C7< 39B4> GPU_DVOD<10> 19D7<> 20A7< KBD_X<2> 23B5< 23B7<> 30C6<> 39B4> MEM_DATA<42> 9B8<> 10C3<> 39B5>
2_5V_ILIM 35C5<> 38C1> AGP_DEVSEL_L 12B2<> 12C2< 18B7<> 37D5> CBUS_RESET_L 17B2<> 17C4> CPU_DATA<45> 6B8<> 8B4<> 8B8< EIDE_OPTICAL_DATA<15> 24A6<> 24C7< 39B4> GPU_DVOD<11> 19D7<> 20A7< KBD_X<3> 23B5< 23B7<> 30C6<> 39A4> MEM_DATA<43> 9B8<> 10C3<> PCI_AD<29> 9C1<> 12C6<> 17B7<> 24D6<> 26B7<>
2_5V_LX 35B4<> 38D1> AGP_FRAME_L 12B2<> 12C2< 18B7<> 37D5> CBUS_SUSPEND_PU 17A7< 17D7< CPU_DATA<46> 6B8<> 8B4<> 8B8< EIDE_OPTICAL_DMAACK_L 24A6<> 24A7< 37A5> 39A4> GPU_DVOD_DE 19C7<> 20A7< KBD_X<4> 23B5< 23B7<> 30C6<> 39A4> MEM_DATA<44> 9B8<> 10C3<> 39B5>
2_5V_SLEEP_PWREN_L 35C2<> AGP_GNT_L 12C2< 12D2<> 18B7< 37D5> CBUS_VCCD0_L 17C4<> CPU_DATA<47> 6B8<> 8B4<> 8B8< EIDE_OPTICAL_DMA_RQ 24A6<> 24B7< 37A5> 39A4> GPU_DVO_CLKP 19C7<> 20A7< 36B1> KBD_X<5> 23B5< 23B7<> 30C6<> 39A4> MEM_DATA<45> 9B8<> 10B3<> PCI_AD<30> 9C1<> 12C6<> 17B7<> 24D5<> 26B7<>
2_34V_REF 30A4< AGP_INT_L 14B5<> 18B7<> CBUS_VCCD1_L 17C4<> CPU_DATA<48> 6B8<> 8A8< 8B4<> EIDE_OPTICAL_INT 24A5<> 24A7< 37A5> 39D4> GPU_DVO_HSYNC 19C7<> 20A7< 37C5> KBD_X<6> 23B5< 23B7<> 30C6<> 39A4> MEM_DATA<46> 9B8<> 10B3<> 39B5>
3V_5V_OK 33B4<> 35A8<> 35D6< AGP_IRDY_L 12B2<> 12C2< 18B7<> 37D5> CBUS_VPPD0 17C4<> CPU_DATA<49> 6B8<> 8A8< 8B4<> EIDE_OPTICAL_IOCHRDY 24A5<> 24A7< 37A5> 39D4> GPU_DVO_VSYNC 19C7<> 20A7< 37C5> KBD_X<7> 23B5< 23B7<> 30C6<> 39A4> MEM_DATA<47> 9B8<> 10B3<> PCI_AD<31> 9C1<> 12C6<> 17B7<> 24D6<> 26B7<>
3V_5V_OK_INV 35A8<> AGP_PAR 12B2<> 18B7> 37D5> CBUS_VPPD1 17C5<> CPU_DATA<50> 6B8<> 8A8< 8B4<> EIDE_OPTICAL_RD_L 24A6<> 24A7< 37B5> 39A4> GPU_FBCLK0 36B1> KBD_X<8> 23B5< 23B7<> 30C6<> 39A4> MEM_DATA<48> 9B8<> 10C1<> 39A5>
3V_BG 33C4<> AGP_PIPE_L 12A2<> 12B2< CBUS_VS1 17B2<> 17C4<> CPU_DATA<51> 6B8<> 8A8< 8B4<> EIDE_OPTICAL_RST_L 24A7< 24B5<> 37A5> 39D4> GPU_FBCLK0_L 36B1> KBD_X<9> 23B5< 23B7<> 30C6<> 39D3> MEM_DATA<55..48> 36B5> PCI_CBE<0> 12C7<> 17B7<> 24C5<> 26B7<> 39D4>
3V_BOOST 33C4<> AGP_RBF_L 12A2<> 12C2< 18C6> 37D5> CBUS_VS2 17B2<> 17C4<> CPU_DATA<52> 6B8<> 8A8< 8B4<> EIDE_OPTICAL_WR_L 24A5<> 24A7< 37A5> 39D4> GPU_FBCLK1 36B1> KBD_Y<0> 23B7<> 30D6<> 39D3> MEM_DATA<49> 9B8<> 10C1<> PCI_CBE<3..0> 37C5>
3V_BOOST_ESR 33D3<> AGP_REQ_L 12C2< 12D2<> 18B7<> 37D5> CBUS_WAIT_L 17B2<> 17B4< CPU_DATA<53> 6B8<> 8A8< 8B4<> EIDE_RD_L 13A7> 24A8< 37B5> GPU_FBCLK1_L 36B1> KBD_Y<1> 23B7<> 30D6<> 39D3> MEM_DATA<50> 9B8<> 10C1<> PCI_CBE<1> 12C7<> 17B7<> 24C6<> 26B7<> 39D4>
3V_ITH 33C4<> AGP_SBA<0> 12B2< 18C6> CBUS_WE_L 17B1<> 17C4> CPU_DATA<54> 6B8<> 8A8< 8B4<> EIDE_RST_L 13B7> 24A8< 37B5> GPU_G 19D6<> 22D8< KBD_Y<2> 23B7<> 30D6<> 39D3> MEM_DATA<51> 9B8<> 10C1<> PCI_CBE<2> 12C7<> 17B7<> 24C6<> 26B7<> 39D4>
3V_ITH_RC 33C3< AGP_SBA<7..0> 37D5> CBUS_WP_L 17A1<> 17B4< CPU_DATA<55> 6B8<> 8A8< 8B4<> EIDE_WR_L 13A7> 24A8< 37B5> GPU_HPD 19C5< 22C3<> KBD_Y<3> 23B7<> 30D6<> 39D3> MEM_DATA<52> 9B8<> 10C1<> PCI_CBE<3> 12C7<> 17B7<> 24C6<> 26B7<> 39D4>
3V_PMU_VTAP 32B3< AGP_SBA<1> 12B2<> 18C6> CG_ADDRSEL 14B7< CPU_DATA<56> 6B8<> 8B3< 8B4<> ENET_COL 13C5< 27B7> 37A5> GPU_MEM_IO 38C3> KBD_Y<4> 23B7<> 30D6<> 39D3> MEM_DATA<53> 9B8<> 10C1<> PCI_DEVSEL_L 12B7< 12C7<> 17A7<> 24C5<> 26B7<>
3V_RSNS 33D2< 38D1> AGP_SBA<2> 12B2<> 18C6> CG_CLKOUT 14B6<> CPU_DATA<57> 6B8<> 8B3< 8B4<> ENET_COMA 27B7<> GPU_MEM_IO_FLT 21C2< 38C3> KBD_Y<5> 23B7<> 30D6<> 39D3> MEM_DATA<54> 9B8<> 10C1<> 37C5> 39A5>
3V_RUNSS 33C4< AGP_SBA<3> 12B2<> 18C6> CG_FSEL 14B7< 14C5<> CPU_DATA<58> 6B8<> 8B3< 8B4<> ENET_CRS 13C5< 27B7> 37A5> GPU_R 19D6<> 22D8< KBD_Y<6> 23B7<> 30C6<> 39C3> MEM_DATA<55> 9B8<> 10C1<> PCI_FRAME_L 12B7< 12C7<> 17B7<> 24C5<> 26B7<>
3V_SLEEP_PWREN_L 33A3<> AGP_SBA<4> 12B2<> 18C6> CG_LOCK 14B7<> CPU_DATA<59> 6B8<> 8B3< 8B4<> ENET_CTAP_CHGND 27A1< 38A6> GPU_SSCLK_IN 36B1> KBD_Y<7> 23B7<> 30C6<> 39C3> MEM_DATA<56> 9B8<> 10C1<> 37C5> 39A5>
41
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCI_IRDY_L 12B7< 12C7<> 17B7<> 24C6<> 26B7<> RAM_DATA_B<17> 10C6<> 11C3<> SND_SCLK_F 25C7< 25D7<> VCORE_GNDDIV 34A4< 34B5< 38B1>
37C5> 39A5> RAM_DATA_B<18> 10C6<> 11C3<> SND_SYNC 14B1< 25D8< 39D6> VCORE_GNDDIV_TEST 34A3<>
PCI_PAR 12C7<> 17B7<> 24C5<> 26B7<> 37C5> RAM_DATA_B<19> 10C6<> 11C3<> SND_SYNC_F 25C7<> 25D7< VCORE_GNDSNS 34A2<> 34A4< 38B1>
39D4> RAM_DATA_B<20> 10C6<> 11D5<> SND_TO_AUDIO 14B1< 25D8< 39D6> VCORE_GNDSNS_TEST 34A3<>
PCI_STOP_L 12A7< 12C7<> 17B7<> 24C5<> 26B7<> RAM_DATA_B<21> 10C6<> 11C5<> SND_TO_AUDIO_F 25D6<> 25D7< VCORE_ILIM 34C6<> 38C1>
37C5> 39A5> RAM_DATA_B<22> 10C6<> 11C5<> SOFT_PWR_ON_L 22D1< 23A8< 30A8< 30C6<> 30D7< VCORE_LX 34B5<> 38C1>
PCI_TRDY_L 12B7< 12C7<> 17A7<> 24C5<> 26B7<> RAM_DATA_B<23> 10C6<> 11C5<> 34A3<> VCORE_MUX_EN 34D5<> 39A2>
37C5> 39A5> RAM_DATA_B<24> 10C6<> 11C3<> SRCLK_TP 26A5> 39A4> VCORE_MUX_SEL 34D5<>
PLL_STOP_L 7C4<> 7C8<> RAM_DATA_B<25> 10C6<> 11C3<> SRMOD_TP 26A5< 39A4> VCORE_REF 34B6<> 38C1>
PMU_ACK_L 14C2< 30C4<> RAM_DATA_B<26> 10C6<> 11C3<> ST7_ICP_SEL_PD 23A2< 23D6< VCORE_SEL_OFF_PU 34B6<>
PMU_AC_DET 30A4< 30B4<> RAM_DATA_B<27> 10C6<> 11C3<> ST7_KBD_LED_OUT 23A4< 23C4<> VCORE_SEL_ON 34B6<>
PMU_AC_IN 30B4<> RAM_DATA_B<28> 10C6<> 11C5<> ST7_OSC1 23D5< VCORE_SHDN_L 34C6<>
PMU_BATT0_DET_L 30B4<> RAM_DATA_B<29> 10C6<> 11C5<> ST7_OSC2 23D5<> VCORE_SLOW<1> 34D6<
PMU_BATT1_DET_L_PU 30B4<> 30D2< RAM_DATA_B<30> 10C6<> 11C5<> ST7_PB6_PD 23B2< 23C4<> VCORE_SLOW<2> 34D6<
PMU_BATT_DET_L 30B3< 30D2< 31A4<> 39C3> RAM_DATA_B<31> 10C6<> 11C5<> ST7_RESET_L 23D5<> VCORE_SLOW<3> 34D6<
PMU_BYTE 30B6< 30C7< RAM_DATA_B<32> 10D4<> 11B3<> ST7_SENSOR4_SCK_PD 23B2< 23D4<> VCORE_SLOW<4> 34D6<
PMU_CAPSLOCK_LED_L 30C6<> RAM_DATA_B<47..32> 36B5> ST7_SENSOR4_SDA_PD 23B2< 23D4<> VCORE_SNS 34A1<> 38B1>
PMU_CHARGE_V 30C4<> 31B8<> RAM_DATA_B<33> 10C4<> 11B3<> ST7_SENSOR5_SCK_PU 23B2< 23D4<> VCORE_TIME 34B4<> 38B1>
D
PMU_CHRG_BATT_0 30C4<> 31A8<>
PMU_CLK
PMU_CNVSS
14C2<> 30C4<>
30B6< 30C7<
RAM_DATA_B<34>
RAM_DATA_B<35>
RAM_DATA_B<36>
10C4<> 11B3<>
10C4<> 11B3<>
10C4<> 11B5<>
ST7_SENSOR5_SDA_PU 23B2< 23D4<>
ST7_SLEEP_LED_H 23C2<> 23C4<>
ST7_XTAL_IN 23C5<
VCORE_TON
VCORE_VCC
VCORE_VGATE
34B6< 38C1>
34C6< 38C1>
14B5< 14B7< 34B4> 38B1>
D
PMU_CPU_HRESET_L 23A4< 23C4<> 30C4<> RAM_DATA_B<37> 10C4<> 11B5<> STOP_AGP_L 12D2< 12D4<> VCORE_VID0 39A3>
PMU_EPM 30D2< 30D4<> RAM_DATA_B<38> 10C4<> 11B5<> SUPPLY_M_DM 25B6< 25B8< VCORE_VID1 39A3>
PMU_FROM_INT 14C2<> 30C4<> RAM_DATA_B<39> 10C4<> 11B5<> SUPPLY_M_DP 25B6< 25B8< VCORE_VID2 39A3>
PMU_I2C_CLK 30B4<> 30C2< RAM_DATA_B<40> 10C4<> 11B3<> SUTRO_ALS_GAIN_SW 23C4<> 24B2<> 39C2> VCORE_VID3 39A3>
PMU_I2C_DATA 30B4<> 30C2< RAM_DATA_B<41> 10C4<> 11B3<> SUTRO_ALS_OUT 23C4<> 24B2<> 39C2> VCORE_VID4 39A3>
PMU_INT_L 14B5<> 14B7< 30B6<> RAM_DATA_B<42> 10C4<> 11A3<> SYSCLK_CPU 5C3< 8A6< 36D1> VCORE_VID<0> 34A2<> 34B8<
PMU_INT_NMI 14B5<> 14B7< 30D4<> RAM_DATA_B<43> 10C4<> 11A3<> SYSCLK_CPU_UF 8A6<> 36D1> VCORE_VID<1> 34A2<> 34B8< 34D4<>
PMU_KB_RESET_IN1 30A7<> RAM_DATA_B<44> 10C4<> 11B5<> SYSCLK_DDRCLK_A0 9D4< 11D8<> 36D1> VCORE_VID<2> 34A2<> 34B8< 34D4<>
PMU_KB_RESET_IN2 30A7<> RAM_DATA_B<45> 10C4<> 11B5<> SYSCLK_DDRCLK_A0_L 9D4< 11D8<> 36D1> VCORE_VID<3> 34A2<> 34B8< 34D4<>
PMU_KB_RESET_L 30A6> 30B7< 39B2> RAM_DATA_B<46> 10C4<> 11A5<> SYSCLK_DDRCLK_A0_L_UF 9B6<> 9D5< 36D1> VCORE_VID<4> 34A2<> 34B8< 34D4<>
PMU_LID_CLOSED_L 23A8< 23C4<> 30B2< 30C4<> RAM_DATA_B<47> 10C4<> 11A5<> SYSCLK_DDRCLK_A0_UF 9B6<> 9D5< 36D1> VGA_B 22C6<> 22D7< 39D7>
PMU_NMI_BUTTON_L 25C1< 30C2< 30C4<> RAM_DATA_B<48> 10D2<> 11A3<> SYSCLK_DDRCLK_A1 9D4< 11A6<> 36D1> VGA_G 22C5<> 22D7< 39D7>
PMU_NMI_L 30C2< 30C4<> RAM_DATA_B<55..48> 36B5> SYSCLK_DDRCLK_A1_L 9D4< 11A6<> 36D1> VGA_HSYNC 22C6<> 22C7< 39D7>
PMU_NUMLOCK_LED_L 30C6<> RAM_DATA_B<49> 10C2<> 11A3<> SYSCLK_DDRCLK_A1_L_UF 9B6<> 9D5< 36D1> VGA_HSYNC_BUF 22C8<>
PMU_OOPS 30B2< 30B4<> RAM_DATA_B<50> 10C2<> 11A3<> SYSCLK_DDRCLK_A1_UF 9B6<> 9D5< 36D1> VGA_R 22C5<> 22D7< 39D7>
PMU_PME_L 14B5<> 26B8< 30B2< 30C4<> RAM_DATA_B<51> 10C2<> 11A3<> SYSCLK_DDRCLK_B0 9D4< 11D3<> 36D1> VGA_VSYNC 22C5<> 22C7< 39D7>
PMU_POWERUP_OK 30B4<> 30D2< RAM_DATA_B<52> 10C2<> 11A5<> SYSCLK_DDRCLK_B0_L 9C4< 11D3<> 36C1> VGA_VSYNC_BUF 22C8<>
PMU_POWER_UP_L 29C7<> 30C6<> 30D7< 33B8< RAM_DATA_B<53> 10C2<> 11A5<> SYSCLK_DDRCLK_B0_L_UF 9B6<> 9C5< 36D1> ZV_LCDDATA20_PU 19C7<>
PMU_REQ_L 14B7< 14C2> 30C4<> RAM_DATA_B<54> 10C2<> 11A5<> SYSCLK_DDRCLK_B0_UF 9B6<> 9D5< 36D1>
PMU_RESET_BUTTON_L 25B1< 30C4<> 30D2< RAM_DATA_B<55> 10C2<> 11A5<> SYSCLK_DDRCLK_B1 9D4< 11A5<> 36C1>
PMU_RESET_L 30B6<> RAM_DATA_B<56> 10C2<> 11A3<> SYSCLK_DDRCLK_B1_L 9D4< 11A5<> 36C1>
PMU_SLEEP_LED 23C4<> RAM_DATA_B<63..56> 36A5> SYSCLK_DDRCLK_B1_L_UF 9B6<> 9D5< 36D1>
PMU_SLEEP_LED_L 23C2<> 30C4<> RAM_DATA_B<57> 10C2<> 11A3<> SYSCLK_DDRCLK_B1_UF 9B6<> 9D5< 36D1>
PMU_SMB_CLK 30B4<> 30C2< 31A3< RAM_DATA_B<58> 10C2<> 11A3<> SYSCLK_LA_TP 8A6<>
PMU_SMB_DATA 30B4<> 30C2< 31A2< RAM_DATA_B<59> 10C2<> 11A3<> SYSTEM_CLK_EN 14A5< 14B7< 30C4<>
PMU_TO_INT 14C2<> 30C4<> RAM_DATA_B<60> 10C2<> 11A5<> TEB_TP 26A5< 39A4>
POWER_UP 29C7<> RAM_DATA_B<61> 10C2<> 11A5<> TEST_TP 26A5< 39A4>
POWER_VALID 30B2< 30C4<> RAM_DATA_B<62> 10C2<> 11A5<> THERM1_A_DM 25A6< 25A8< 37A2>
PWR_BUTTON_L 23A7<> 25C2< 39B2> RAM_DATA_B<63> 10C2<> 11A5<> THERM1_A_DP 25A6< 25A8< 37A2>
RAM_ADDR<0> 9B4< 11B5<> 11B6<> RAM_DQM_A<0> 10B8<> 11D6<> 36C5> THERM1_DM 25A5< 25B5<> 25B5< 37A2>
RAM_ADDR<12..0> 36A5> RAM_DQM_A<1> 10C7<> 11D6<> 36C5> THERM1_DP 25A5< 25B5<> 25B5< 37A2>
RAM_ADDR<1> 9B4< 11B3<> 11B8<> RAM_DQM_A<2> 10B6<> 11C6<> THERM1_M_DM 37A2>
RAM_ADDR<2> 9B4< 11B5<> 11B6<> RAM_DQM_A<3..2> 36B5> THERM1_M_DP 37A2>
RAM_ADDR<3> 9B4< 11B3<> 11B8<> RAM_DQM_A<3> 10C5<> 11C6<> THERM2_A_DM 25A6< 25A8< 37A2>
RAM_ADDR<4> 9B4< 11B5<> 11B6<> RAM_DQM_A<4> 10B4<> 11B6<> THERM2_A_DP 25A6< 25A8< 37A2>
RAM_ADDR<5> 9B4< 11B3<> 11B8<> RAM_DQM_A<5..4> 36B5> THERM2_DM 25A5< 25B5<> 25B5< 37A2>
RAM_ADDR<6> 9B4< 11B5<> 11B6<> RAM_DQM_A<5> 10C3<> 11A6<> THERM2_DP 25A5< 25B5<> 25B5< 37A2>
RAM_ADDR<7> 9B4< 11B3<> 11B8<> RAM_DQM_A<6> 10B2<> 11A6<> 36B5> THERM2_M_DM 37A2>
RAM_ADDR<8> 9B4< 11B5<> 11B6<> RAM_DQM_A<7> 10C1<> 11A6<> 36A5> THERM2_M_DP 37A2>
RAM_ADDR<9> 9A4< 11B3<> 11B8<> RAM_DQM_B<0> 10C8<> 11D5<> 36C5> THERM_INV 25A5<>
RAM_ADDR<10> 9A4< 11B3<> 11B8<> RAM_DQM_B<1> 10C8<> 11D5<> 36C5> THERM_L_OC 25A4<> 30B4<>
C RAM_ADDR<11>
RAM_ADDR<12>
RAM_BA<0>
9A4< 11B5<> 11B6<>
9A4< 11B3<> 11B8<>
9A4< 11B3<> 11B8<>
RAM_DQM_B<2>
RAM_DQM_B<3..2>
RAM_DQM_B<3>
10C6<>
36B5>
10C6<>
11C5<>
11C5<>
TMDS_CLKN
TMDS_CLKP
TMDS_CLK_CMF
20B3< 20C1< 20C3< 22B7<> 37B2>
20B3< 20C2< 20C3< 22C7<> 37B2>
20C1<
C
RAM_BA<1..0> 36A5> RAM_DQM_B<4> 10C4<> 11B5<> TMDS_CONN_CLKN 22B6<> 22C7<> 37B2> 39A8>
RAM_BA<1> 9A4< 11B5<> 11B6<> RAM_DQM_B<5..4> 36B5> TMDS_CONN_CLKP 22C6<> 22C7<> 37B2> 39D7>
RAM_CAS_L 9A4< 11B5<> 11B6<> 36A5> RAM_DQM_B<5> 10C4<> 11B5<> TMDS_CONN_DN<0> 22C7<> 22D6<>
RAM_CKE<0> 9A3< 9C4< 11B6<> RAM_DQM_B<6> 10C2<> 11A5<> 36B5> TMDS_CONN_DN<1> 22B7<> 22D5<>
RAM_CKE<3..0> 36A5> RAM_DQM_B<7> 10C2<> 11A5<> 36A5> TMDS_CONN_DN<2> 22B6<> 22D5<>
RAM_CKE<1> 9A3< 9C4< 11B8<> RAM_DQS_A<0> 10B8<> 11D8<> 36C5> TMDS_CONN_DP<0> 22B7<> 22D6<>
RAM_CKE<2> 9A3< 9C4< 11C5<> RAM_DQS_A<1> 10C7<> 11D8<> 36C5> TMDS_CONN_DP<1> 22B7<> 22D5<>
RAM_CKE<3> 9A3< 9C4< 11C3<> RAM_DQS_A<2> 10B6<> 11C8<> TMDS_CONN_DP<2> 22B6<> 22D5<>
RAM_CS_L<0> 9C4< 11B8<> RAM_DQS_A<3..2> 36B5> TMDS_D0_CMF 20B1<
RAM_CS_L<3..0> 36A5> RAM_DQS_A<3> 10C5<> 11C8<> TMDS_D1_CMF 20B1<
RAM_CS_L<1> 9C4< 11B6<> RAM_DQS_A<4> 10B4<> 11B8<> TMDS_D2_CMF 20A1<
RAM_CS_L<2> 9C4< 11B3<> RAM_DQS_A<5..4> 36B5> TMDS_DN<0> 20B1< 20B3< 20C3< 22C8<> 37B2>
RAM_CS_L<3> 9C4< 11B5<> RAM_DQS_A<5> 10C3<> 11A8<> 39B8>
RAM_DATA_A<0> 10C8<> 11D8<> RAM_DQS_A<6> 10B2<> 11A8<> 36B5> TMDS_DN<1> 20A3< 20B1< 20C3< 22B8<> 37B2>
RAM_DATA_A<7..0> 36C5> RAM_DQS_A<7> 10C1<> 11A8<> 36A5> 39A8>
RAM_DATA_A<1> 10C8<> 11D8<> RAM_DQS_B<0> 10C8<> 11D3<> 36C5> TMDS_DN<2> 20A1< 20A3< 20B3< 22B7<> 37B2>
RAM_DATA_A<2> 10C8<> 11D8<> RAM_DQS_B<1> 10C8<> 11D3<> 36C5> 39A8>
RAM_DATA_A<3> 10B8<> 11D8<> RAM_DQS_B<2> 10C6<> 11C3<> TMDS_DP<0> 20B2< 20B3< 20C3< 22B8<> 37B2>
RAM_DATA_A<4> 10B8<> 11D6<> RAM_DQS_B<3..2> 36B5> 39A8>
RAM_DATA_A<5> 10B8<> 11D6<> RAM_DQS_B<3> 10C6<> 11C3<> TMDS_DP<1> 20A3< 20B2< 20C3< 22B8<> 37B2>
RAM_DATA_A<6> 10B8<> 11D6<> RAM_DQS_B<4> 10C4<> 11B3<> 39A8>
RAM_DATA_A<7> 10B8<> 11D6<> RAM_DQS_B<5..4> 36B5> TMDS_DP<2> 20A2< 20A3< 20B3< 22B7<> 37B2>
RAM_DATA_A<8> 10B8<> 11D8<> RAM_DQS_B<5> 10C4<> 11B3<> 39A8>
RAM_DATA_A<15..8> 36C5> RAM_DQS_B<6> 10C2<> 11A3<> 36B5> TPAD_F_RXD 23A7<> 39C4>
RAM_DATA_A<9> 10C7<> 11D8<> RAM_DQS_B<7> 10C2<> 11A3<> 36A5> TPAD_F_TXD 23A7<> 39C4>
RAM_DATA_A<10> 10C7<> 11D8<> RAM_MUXSEL_H 10A3< 10A5< 10B1<> 10B3<> 36A5> TPAD_RXD 23A8< 30C2< 30C4<>
RAM_DATA_A<11> 10C7<> 11D8<> RAM_MUXSEL_L 10A3< 10A5< 10B5<> 10B7<> 36A5> TPAD_TXD 23A8< 30B2< 30C4<>
RAM_DATA_A<12> 10C7<> 11D6<> RAM_RAS_L 9A4< 11B5<> 11B6<> 36A5> TPS2211_SHDN_L_PU 17C4<
RAM_DATA_A<13> 10C7<> 11D6<> RAM_WE_L 9A4< 11B3<> 11B8<> 36A5> TV_C 22A6<> 39D6>
RAM_DATA_A<14> 10C7<> 11D6<> RF_DISABLE_L_SPN 24D6<> 39C1> TV_COMP 22A6<> 39D6>
RAM_DATA_A<15> 10C7<> 11D6<> RIGHT_USB_DM 26A3< 32A7<> 37A2> 39D1> TV_GND1 22B6<> 38B6> 39A7>
RAM_DATA_A<16> 10C6<> 11D8<> RIGHT_USB_DP 26A3< 32A7<> 37A2> 39D1> TV_GND2 22A6<> 38B6> 39A7>
RAM_DATA_A<31..16> 36B5> RJ45_C0_PD 27B2<> TV_Y 22A6<> 39D6>
RAM_DATA_A<17> 10C6<> 11C8<> RJ45_C1_PD 27B2<> UIDE_ADDR<0> 13D7<> 24C4<
RAM_DATA_A<18> 10C6<> 11C8<> RJ45_C2_PD 27B2<> UIDE_ADDR<2..0> 37C5>
RAM_DATA_A<19> 10B6<> 11C8<> RJ45_C3_PD 27B2<> UIDE_ADDR<1> 13D7<> 24C4<
RAM_DATA_A<20> 10B6<> 11D6<> RJ45_DN<0> 27B2<> 37D2> 39B3> UIDE_ADDR<2> 13D7<> 24B4<
RAM_DATA_A<21> 10B6<> 11C6<> RJ45_DN<1> 27B2<> 37D2> 39B3> UIDE_CS0_L 13C7<> 24C4< 37C5>
RAM_DATA_A<22> 10B6<> 11C6<> RJ45_DN<2> 27B2<> 37D2> 39A3> UIDE_CS1_L 13C7<> 24B4< 37C5>
RAM_DATA_A<23> 10B6<> 11C6<> RJ45_DN<3> 27B2<> 37D2> 39A3> UIDE_DATA<0> 13D7<> 24D4<
RAM_DATA_A<24> 10B6<> 11C8<> RJ45_DP<0> 27B2<> 37D2> 39B3> UIDE_DATA<6..0> 37C5>
B RAM_DATA_A<25>
RAM_DATA_A<26>
RAM_DATA_A<27>
10C5<> 11C8<>
10C5<> 11C8<>
10C5<> 11C8<>
RJ45_DP<1>
RJ45_DP<2>
RJ45_DP<3>
27B2<> 37D2> 39B3>
27B2<> 37D2> 39A3>
27B2<> 37D2> 39A3>
UIDE_DATA<1>
UIDE_DATA<2>
UIDE_DATA<3>
13D7<> 24D4<
13D7<> 24D4<
13D7<> 24D4<
B
RAM_DATA_A<28> 10C5<> 11C6<> ROM_CS_L 9B3< 12A5< 24B6<> 39B1> UIDE_DATA<4> 13D7<> 24C4<
RAM_DATA_A<29> 10C5<> 11C6<> ROM_OE_L 9B3< 12A5< 24C5<> 39B1> UIDE_DATA<5> 13D7<> 24C4<
RAM_DATA_A<30> 10C5<> 11C6<> ROM_ONBOARD_CS_L 9B3< 24C6<> 39B1> UIDE_DATA<6> 13D7<> 24C4<
RAM_DATA_A<31> 10C5<> 11C6<> ROM_RW_L 9B3< 12A5< 24C6<> 39B1> UIDE_DATA<7> 13D7<> 24C4< 37C5>
RAM_DATA_A<32> 10C4<> 11B8<> ROM_WP_L 9B3< UIDE_DATA<8> 13D7<> 24C4<
RAM_DATA_A<47..32> 36B5> RSDM3_TP 26C5> UIDE_DATA<15..8> 37C5>
RAM_DATA_A<33> 10C4<> 11B8<> RSDM4_TP 26C5> UIDE_DATA<9> 13D7<> 24C4<
RAM_DATA_A<34> 10C4<> 11B8<> RSDM5_TP 26C5> UIDE_DATA<10> 13D7<> 24C4<
RAM_DATA_A<35> 10C4<> 11B8<> RSDP3_TP 26C5> UIDE_DATA<11> 13D7<> 24D4<
RAM_DATA_A<36> 10B4<> 11B6<> RSDP4_TP 26C5> UIDE_DATA<12> 13D7<> 24B4<
RAM_DATA_A<37> 10B4<> 11B6<> RSDP5_TP 26C5> UIDE_DATA<13> 13D7<> 24B4<
RAM_DATA_A<38> 10B4<> 11B6<> RUN_OR_AC 29C6<> UIDE_DATA<14> 13D7<> 24C4<
RAM_DATA_A<39> 10B4<> 11B6<> SI_A2 20B7< UIDE_DATA<15> 13D7<> 24B4<
RAM_DATA_A<40> 10B4<> 11B8<> SI_DDC_CLK 19C5<> 20B7< UIDE_DIOR_L 13C7<> 24A4< 37C5>
RAM_DATA_A<41> 10D3<> 11B8<> SI_DDC_DATA 19C5<> 20B7< UIDE_DIOW_L 13C7<> 24A4< 37C5>
RAM_DATA_A<42> 10C3<> 11A8<> SI_EDGE 20B7< UIDE_DMACK_L 13C7<> 24A4< 37C5>
RAM_DATA_A<43> 10C3<> 11A8<> SI_MSEN 20B5<> UIDE_DMARQ 13C7<> 37C5>
RAM_DATA_A<44> 10C3<> 11B6<> SI_PD 20B7< UIDE_INTRQ 13C7< 37C5>
RAM_DATA_A<45> 10C3<> 11B6<> SI_RST 20B7< UIDE_IOCHRDY 13C7< 24A4< 37C5>
RAM_DATA_A<46> 10C3<> 11A6<> SI_TMDS_CLKN 20B5<> 20C4< UIDE_REF 13C7<> 38D3>
RAM_DATA_A<47> 10C3<> 11A6<> SI_TMDS_CLKP 20B5<> 20C4< UIDE_RST_L 13C7<> 24A4< 37C5>
RAM_DATA_A<48> 10C2<> 11A8<> SI_TMDS_DN<0> 20B5<> 20C4< USB2_PCI_GNT_L 12C7<> 26B7<
RAM_DATA_A<55..48> 36B5> SI_TMDS_DN<1> 20B5<> 20C4< USB2_PCI_INT_L 14B5<> 14C7< 26A8<
RAM_DATA_A<49> 10C2<> 11A8<> SI_TMDS_DN<2> 20A5<> 20B4< USB2_PCI_REQ_L 12A7< 12D7<> 26B7>
RAM_DATA_A<50> 10C2<> 11A8<> SI_TMDS_DP<0> 20B5<> 20C4< USB_D1M 14C1< 26A5> 26B4<
RAM_DATA_A<51> 10C2<> 11A8<> SI_TMDS_DP<1> 20B5<> 20C4< USB_D1P 14C1< 26A4< 26A5>
RAM_DATA_A<52> 10B2<> 11A6<> SI_TMDS_DP<2> 20A5<> 20B4< USB_D2M 14D1< 26A4< 26A5>
RAM_DATA_A<53> 10B2<> 11A6<> SI_VREF 20A5< 20A7< USB_D2P 14D1< 26A4< 26A5>
RAM_DATA_A<54> 10B2<> 11A6<> SLEEP 23C4<> 25C6<> 30B6<> 30D7< 33A4< USB_DAM 14B2<> 14D2< 26A5>
RAM_DATA_A<55> 10B2<> 11A6<> 33A6< 33B3< 33B8<> 35B3< 35D2< 39A1> USB_DAP 14B2<> 14D2< 26A5>
RAM_DATA_A<56> 10B2<> 11A8<> USB_DBM 14B2<> 14D2<
RAM_DATA_A<63..56> 36A5> SLEEP_LED 23C1< 25C7<> 39B6> USB_DBP 14B2<> 14D2<
RAM_DATA_A<57> 10D1<> 11A8<> SLEEP_LED_I 23D1< USB_DCM 14B2<> 14C2< 26A5>
RAM_DATA_A<58> 10C1<> 11A8<> SLEEP_LED_L 23D2< USB_DCP 14B2<> 14C2< 26A5>
RAM_DATA_A<59> 10C1<> 11A8<> SLEEP_LED_SW_L 23C2<> USB_DDM 14B2<> 14C2<
RAM_DATA_A<60> 10C1<> 11A6<> SLEEP_LED_UF 23C1< USB_DDP 14B2<> 14C2<
RAM_DATA_A<61> 10C1<> 11A6<> SLEEP_LS5 33A5<> 33A8< USB_DEM 14B2<> 14B2< 37B2>
RAM_DATA_A<62> 10C1<> 11A6<> SLEEP_LS5_EN_L 33A5<> USB_DEP 14B2<> 14C2< 37B2>
RAM_DATA_A<63> 10C1<> 11A6<> SLEEP_L_LS5 19A7<> 27A8<> 33A5<> 34C8<> 35C8< USB_DFM 14B2<> 14B2< 37B2>
RAM_DATA_B<0> 10C8<> 11D3<> SLEEP_L_LS5_EN_L 33A6<> USB_DFP 14B2<> 14B2< 37B2>
A RAM_DATA_B<7..0> 36C5>
RAM_DATA_B<1>
RAM_DATA_B<2>
10C8<> 11D3<>
10C8<> 11D3<>
SLEEP_L_LS5_INV
SLEEP_L_LS5_NET
SLEEP_NET
35A3< 35C2< 35C8<>
33B3<> 35C8<>
33A3<>
USB_OC_AB_L
USB_OC_CD_L
USB_OC_EF_L
14B2< 14C7<
14B2< 14C7<
14B2< 14D7<
A
RAM_DATA_B<3> 10C8<> 11D3<> SLEEP_NET_INV 33A3<> USB_PWREN_AB_L 14B2<> 14C7<
RAM_DATA_B<4> 10C8<> 11D5<> SMC_TP 26B5< USB_PWREN_CD_L 14B2<> 14C7<
RAM_DATA_B<5> 10C8<> 11D5<> SND_AGND 25C7<> 38B6> USB_PWREN_EF_L 14B2<> 14D7< THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
RAM_DATA_B<6> 10C8<> 11D5<> SND_AMP_MUTE 25C8< 25D6<> 39A4> VCORE_BOOST 34C4<> 38C1> PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
RAM_DATA_B<7> 10C8<> 11D5<> SND_AMP_MUTE_F 25C7< 25D6<> VCORE_BST 34C5<> 38C1> AGREES TO THE FOLLOWING
RAM_DATA_B<8> 10C8<> 11D3<> SND_AMP_MUTE_L 14C5<> 25D5<> VCORE_CC 34B6<> 38B1> I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
RAM_DATA_B<15..8> 36C5> SND_CLKOUT 14B1< 25D8< 36B1> 39D6> VCORE_CNTL_RC 19A3<>
RAM_DATA_B<9> 10C8<> 11D3<> SND_CLKOUT_F 25C7<> 25D7< VCORE_DH 34B5<> 38C1> II NOT TO REPRODUCE OR COPY IT
RAM_DATA_B<10> 10C8<> 11D3<> SND_HP_MUTE 25C5<> VCORE_DL 34B5<> 38C1>
RAM_DATA_B<11> 10C8<> 11D3<> SND_HP_MUTE_INV 25C5<> 25C6<> 39A4> VCORE_FAST<1> 34D3< 34D5<
RAM_DATA_B<12> 10C8<> 11D5<> SND_HP_MUTE_L 14C5<> 25C4<> VCORE_FAST<2> 34D3< 34D5<
RAM_DATA_B<13> 10C8<> 11D5<> SND_HP_SENSE_L 14B5<> 25D6<> 39C6> VCORE_FAST<3> 34D3< 34D5< SIZE DRAWING NUMBER REV.
RAM_DATA_B<14> 10C8<> 11D5<> SND_HW_RESET_L 14A7< 14B5<> 25C8< 39C6> VCORE_FAST<4> 34D3< 34D5<
RAM_DATA_B<15>
RAM_DATA_B<16>
10C8<>
10C6<>
11D5<>
11D3<>
SND_HW_RESET_L_F
SND_LIN_SENSE_L
25C6<> 25C7<
14B5<> 25D6<> 39C6>
VCORE_FB
VCORE_GND
34B5< 38B1> 39A2>
34B5<> 38B1>
APPLE COMPUTER INC.
D 051-6459 A
RAM_DATA_B<31..16> 36B5> SND_SCLK 14B1< 25C8< 36B1> 39C6> VCORE_GNDA 34B6<>
SCALE SHT OF
NONE 42
42 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
*** Part Cross-Reference for the entire design *** C166 CAP 19 C335 CAP 16 C503 CAP 27 C671 CAP 21 C839 CAP 26 L28 IND 22 R29 RES 14 R197 RES 8
C167 CAP 19 C336 CAP 16 C504 CAP 27 C672 CAP 21 C840 CAP 26 L29 IND 22 R30 RES 24 R198 RES 9
BS1 PCB_STANDOFF 4 C168 CAP 5 C337 CAP 16 C505 CAP 27 C673 CAP 23 C841 CAP 26 L30 IND_3P 19 R31 RES 24 R199 RES 9
C1 CAP 22 C169 CAP 5 C338 CAP 19 C506 CAP 27 C674 CAP 34 C842 CAP 26 L31 IND 22 R32 RES 24 R200 RES 18
C6 CAP 34 C174 CAP 16 C343 CAP 5 C511 CAP 27 C679 CAP 34 C847 CAP 21 L36 IND_3P 34 R37 RES 18 R205 RES 20
C7 CAP 34 C175 CAP 16 C344 CAP 5 C512 CAP 34 C680 CAP 34 C848 CAP 21 L37 IND_3P 32 R38 RES 18 R206 RES 5
C13 CAP 34 C181 CAP 16 C350 CAP 16 C518 CAP 34 C686 CAP 14 C854 CAP 21 L43 FILTER_4P 29 R44 RES 18 R212 RES 20
D
C16
C17
C18
CAP
CAP
CAP
16
16
16
C184
C185
C186
CAP
CAP
CAP
16
16
19
C353
C354
C355
CAP
CAP
CAP
14
16
16
C521
C522
C523
CAP
CAP
CAP
34
11
11
C689
C690
C691
CAP
CAP
CAP
34
25
14
C857
C858
C859
CAP
CAP
CAP
21
21
21
L46
L47
L48
IND
IND
IND
23
23
23
R47
R48
R49
RES
RES
RES
7
7
14
R215
R216
R217
RES
RES
RES
8
12
12
D
C21 CAP 16 C189 CAP 5 C358 CAP 21 C526 CAP 11 C694 CAP_P 33 C862 CAP 21 L51 IND 28 R52 RES 13 R220 RES 20
C43 CAP 16 C211 CAP 16 C380 CAP 21 C548 CAP 11 C716 CAP 21 C884 CAP_P 34 L73 FILTER_4P 22 R74 RES 24 R242 RES 10
C44 CAP 16 C212 CAP 16 C381 CAP 21 C549 CAP 11 C717 CAP 22 C885 CAP_P 34 L74 FILTER_4P 22 R75 RES 24 R243 RES 10
C53 CAP 16 C221 CAP 19 C390 CAP 16 C558 CAP 30 C726 CAP 35 C894 CAP 35 PD1 PHOTODIODE_2P 23 R84 RES 26 R252 RES 10
C54 CAP 16 C222 CAP 19 C391 CAP 16 C559 CAP 35 C727 CAP 10 C895 CAP 25 Q1 TRA_2N7002DW 7 R85 RES 5 R253 RES 19
C55 CAP 16 C223 CAP 5 C392 CAP 16 C560 CAP 33 C728 CAP_P 34 C896 CAP 25 Q2 TRA_2N7002DW 7 R86 RES 5 R254 RES 19
C56 CAP 16 C224 CAP 5 C393 CAP 16 C561 CAP 28 C729 CAP_P 34 C897 CAP 25 Q3 TRA_2N7002 7 R87 RES 5 R255 RES 21
C C60
C61
C62
CAP
CAP
CAP
16
16
18
C228
C229
C230
CAP
CAP
CAP
16
16
16
C397
C398
C399
CAP
CAP
CAP
16
16
16
C565
C566
C567
CAP
CAP
CAP
11
33
33
C733
C734
C735
CAP_P
CAP_P
CAP
34
34
10
C901
C902
C903
CAP
CAP
CAP
25
19
25
Q7
Q8
Q9
TRA_FDG6324L 22
TRA_2N7002 22
TRA_2N7002DW 33
R91
R92
R93
RES
RES
RES
14
13
24
R259
R260
R261
RES
RES
RES
19
19
19
C
C63 CAP 18 C231 CAP 16 C400 CAP 16 C568 CAP 32 C736 CAP 10 C904 CAP 25 Q10 TRA_2N7002DW 31 R94 RES 24 R262 RES 19
C64 CAP 18 C232 CAP 19 C401 CAP 16 C569 CAP 32 C737 CAP 10 C905 CAP 25 Q11 TRA_SI3443DV 22 R95 RES 24 R263 RES 19
C65 CAP 18 C233 CAP 20 C402 CAP 16 C570 CAP 28 C738 CAP 10 C906 CAP 31 Q12 TRA_2N3904 34 R96 RES 26 R264 RES 14
C66 CAP 18 C234 CAP 34 C403 CAP 16 C571 CAP 28 C739 CAP 22 C907 CAP 35 Q13 TRA_SI4435DY 31 R97 RES 5 R265 RES 19
C67 CAP 18 C235 CAP 35 C404 CAP 16 C572 CAP 31 C740 CAP 35 C908 CAP 35 Q14 TRA_FDG6324L 32 R98 RES 5 R266 RES 19
C68 CAP 18 C236 CAP 16 C405 CAP 16 C573 CAP 11 C741 CAP 10 D1 DIODE 27 Q15 TRA_2N7002DW 27 R99 RES 20 R267 RES 34
C69 CAP 18 C237 CAP 16 C406 CAP 16 C574 CAP 30 C742 CAP 10 D2 DIODE_SCHOT 34 Q16 TRA_SI4435DY 31 R100 RES 14 R268 RES 21
C70 CAP 18 C238 CAP 16 C407 CAP 16 C575 CAP 35 C743 CAP 10 D3 DIODE_SCHOT 32 Q17 TRA_2N3904 34 R101 RES 24 R269 RES 19
C71 CAP 18 C239 CAP 16 C408 CAP 21 C576 CAP 33 C744 CAP 22 D4 DIODE 32 Q19 TRA_2N7002 35 R102 RES 14 R270 RES 19
C72 CAP 5 C240 CAP 16 C409 CAP 21 C577 CAP 28 C745 CAP_P 35 D5 DIODE_SCHOT 19 Q20 TRA_2N7002DW 31 R103 RES 12 R271 RES 19
C73 CAP 5 C241 CAP 16 C410 CAP 16 C578 CAP 31 C746 CAP 22 D6 DIODE_SCHOT 33 Q21 TRA_2N7002DW 31 R104 RES 18 R272 RES 19
C75 CAP 16 C243 CAP 16 C412 CAP 21 C580 CAP 35 C748 CAP 10 D8 ZENER 29 Q23 TRA_2N7002DW 33 R106 RES 5 R274 RES 19
C76 CAP 16 C244 CAP 16 C413 CAP 21 C581 CAP 35 C749 CAP 22 D9 DIODE 31 Q24 TRA_SI4435DY 31 R107 RES 5 R277 RES 14
C77 CAP 18 C245 CAP 9 C414 CAP 21 C582 CAP 35 C750 CAP_P 32 D10 DIODE 31 Q25 TRA_2N7002DW 29 33 R108 RES 5 R278 RES 14
C78 CAP 18 C246 CAP 16 C415 CAP 21 C583 CAP 33 C751 CAP_P 35 D11 DIODE_SCHOT 32 Q26 TRA_2N7002DW 25 R109 RES 5 R279 RES 21
C79 CAP 20 C247 CAP 12 C416 CAP 22 C584 CAP 32 C752 CAP 10 D12 DIODE_DUAL_6P 29 Q27 TRA_2N7002DW 31 R110 RES 20 R281 RES 14
C80 CAP 20 C248 CAP 16 C417 CAP 16 C585 CAP 32 C753 CAP 10 D13 DIODE_SCHOT 33 Q28 TRA_SI3443DV 33 R111 RES 14 R284 RES 21
C81 CAP 20 C249 CAP 16 C418 CAP 16 C586 CAP 28 C754 CAP 27 D14 DIODE_SCHOT_3P2 28 Q29 TRA_2N7002DW 31 R112 RES 12 R286 RES 26
C82 CAP 20 C250 CAP 16 C419 CAP 14 C587 CAP 28 C755 CAP 27 D15 DIODE_DUAL_6P 29 Q30 TRA_2N7002DW 31 R113 RES 14 R287 RES 15
C83 CAP 12 C251 CAP 16 C420 CAP 21 C588 CAP 29 C756 CAP_P 33 D16 DIODE 33 Q31 TRA_2N7002DW 25 R114 RES 14 R288 RES 34
C85 CAP 14 C253 CAP 19 C422 CAP 16 C590 CAP 33 C758 CAP_P 32 D18 DIODE 32 Q33 TRA_2N3906 23 R116 RES 24 R290 RES 34
C86 CAP 24 C254 CAP 19 C423 CAP 16 C591 CAP 28 C759 CAP 33 D19 DIODE_SCHOT 32 Q35 TRA_2N7002DW 22 23 R117 RES 13 R291 RES 14
C89 CAP 20 C257 CAP 5 C426 CAP 21 C594 CAP 11 C762 CAP 19 D22 DIODE_SCHOT 33 Q38 TRA_2N7002DW 22 R120 RES 5 R294 RES 19
C90 CAP 5 C258 CAP 5 C427 CAP_P 34 C595 CAP 11 C763 CAP 33 D23 DIODE_SCHOT 35 Q39 TRA_2N3904 25 R121 RES 8 R295 RES 25
C91 CAP 5 C259 CAP 16 C428 CAP 21 C596 CAP 11 C764 CAP 34 D24 DIODE_SCHOT 19 Q40 TRA_TP0610 22 R122 RES 8 R296 RES 33
C92 CAP 5 C260 CAP 16 C429 CAP 21 C597 CAP 11 C765 CAP_P 32 D25 DIODE 34 Q41 TRA_2N7002DW 22 R123 RES 8 R297 RES 34
C93 CAP 35 C261 CAP 16 C430 CAP_P 34 C598 CAP 33 C766 CAP 19 D26 DIODE_DUAL_6P 29 Q42 TRA_2N3904 22 R124 RES 13 R298 RES 33
C94 CAP 16 C262 CAP 16 C431 CAP_P 34 C599 CAP 32 C767 CAP 25 D27 DIODE_SCHOT 32 Q43 TRA_SI3443DV 33 R125 RES 14 R299 RES 21
C95 CAP 16 C263 CAP 16 C432 CAP_P 34 C600 CAP 31 C768 CAP 34 D28 DIODE_DUAL_6P 29 Q44 TRA_2N3904 22 R126 RES 18 R300 RES 33
C96 CAP 16 C264 CAP 16 C433 CAP 14 C601 CAP 11 C769 CAP_P 32 D29 DIODE_SCHOT 29 Q45 TRA_TP0610 22 R127 RES 18 R301 RES 34
C99 CAP 16 C267 CAP 16 C436 CAP 21 C604 CAP 32 C772 CAP 31 D34 DIODE_SCHOT 33 Q48 TRA_SI7892DP 19 R130 RES 5 R304 RES 34
C100 CAP 16 C268 CAP 16 C437 CAP 21 C605 CAP 28 C773 CAP 17 DP1 DPAK3P 19 Q49 TRA_SI7860DP 34 R131 RES 8 R305 RES 34
C103 CAP 5 C271 CAP 19 C440 CAP 22 C608 CAP 31 C776 CAP 17 DP4 DPAK3P 31 Q52 TRA_SI4888DY 33 R134 RES 8 R308 RES 33
B C104
C105
C106
CAP
CAP
CAP
5
5
5
C272
C273
C274
CAP
CAP
CAP
5
5
34
C441
C442
C443
CAP_P
CAP
CAP_P
34
27
34
C609
C610
C611
CAP
CAP
CAP
33
33
33
C777
C778
C779
CAP
CAP
CAP
28
28
33
DP5
DP6
DP7
DPAK3P
DPAK3P
DPAK3P
29
19
21
Q53
Q54
Q55
TRA_IRF7832 34
TRA_IRF7832 34
TRA_IRF7832 34
R135
R136
R137
RES
RES
RES
8
8
8
R309
R310
R311
RES
RES
RES
33
33
19
B
C107 CAP 5 C275 CAP 5 C444 CAP_P 34 C612 CAP 33 C780 CAP_P 35 F1 FUSE 22 Q56 TRA_IRF7811W 35 R138 RES 18 R312 RES 34
C108 CAP 16 C276 CAP 35 C445 CAP_P 34 C613 CAP 32 C781 CAP 29 F2 FUSE 29 Q57 TRA_IRF7805 35 R139 RES 5 R313 RES 34
C109 CAP 16 C277 CAP 16 C446 CAP 21 C614 CAP 28 C782 CAP_P 35 F3 FUSE 31 Q58 TRA_2N7002DW 29 R140 RES 8 R314 RES 34
C110 CAP 5 C278 CAP 16 C447 CAP 21 C615 CAP 31 C783 CAP 17 F4 FUSE 31 Q59 TRA_IRF7805 32 R141 RES 8 R315 RES 34
C111 CAP 5 C279 CAP 16 C448 CAP 19 C616 CAP 31 C784 CAP 29 F5 FUSE 29 Q60 TRA_IRF7811W 32 R142 RES 8 R316 RES 19
C112 CAP 5 C280 CAP 16 C449 CAP 22 C617 CAP 31 C785 CAP 33 FL1 FILTER_LC 22 Q61 TRA_SI4888DY 33 R143 RES 8 R317 RES 22
C113 CAP 5 C281 CAP 16 C450 CAP 21 C618 CAP 31 C786 CAP 29 FL2 FILTER_LC 22 Q62 TRA_2N3904 25 R144 RES 8 R318 RES 34
C114 CAP 5 C282 CAP 19 C451 CAP 19 C619 CAP 31 C787 CAP 32 FL3 FILTER_LC 22 Q63 TRA_IRF7805 31 R145 RES 13 R319 RES 27
C115 CAP 5 C284 CAP 20 C452 CAP 22 C620 CAP 33 C788 CAP_P 35 G1 OSC 28 Q64 TRA_IRF7811W 31 R146 RES 12 R320 RES 22
C116 CAP 34 C285 CAP 34 C453 CAP 27 C621 CAP 31 C789 CAP 17 G2 OSC 18 Q65 TRA_2N7002DW 31 R147 RES 12 R321 RES 34
C117 CAP 16 C286 CAP 16 C454 CAP 27 C622 CAP 31 C790 CAP 17 J1 CON_F1ST_S2MT_SM 14 Q66 TRA_2N3904 25 R148 RES 5 R322 RES 34
C118 CAP 16 C287 CAP 16 C455 CAP 34 C623 CAP 33 C791 CAP 17 J2 CON_3RTSM_125 25 Q67 TRA_NDS9407 29 R149 RES 7 R323 RES 34
C119 CAP 16 C288 CAP 16 C456 CAP 33 C624 CAP 31 C792 CAP 29 J3 CON_F14RT_S2MT_SM 24 Q68 TRA_IRF7811W 35 R150 RES 8 R324 RES 34
C120 CAP 16 C289 CAP 16 C457 CAP 27 C625 CAP 32 C793 CAP_P 32 J4 CON_3RTSM_125 25 Q69 TRA_IRF7805 35 R151 RES 8 R325 RES 34
C121 CAP 16 C290 CAP 16 C458 CAP 31 C626 CAP 32 C794 CAP_P 32 J5 CON_12 34 Q71 TRA_SI4888DY 33 R152 RES 8 R326 RES 34
C122 CAP 16 C291 CAP 16 C459 CAP 34 C627 CAP 28 C795 CAP 17 J6 CON_F30RT_S2MT_SM 22 Q72 TRA_SI4888DY 33 R153 RES 8 R327 RES 34
C123 CAP 16 C292 CAP 16 C460 CAP 9 C628 CAP 28 C796 CAP 17 J7 CON_4RT_WRIB 22 Q73 TRA_2N3906 23 R154 RES 13 R328 RES 34
C124 CAP 16 C293 CAP 16 C461 CAP 32 C629 CAP 28 C797 CAP 17 J8 CON_F16ST_D_SMA 25 Q74 TRA_2N3906 23 R155 RES 14 R329 RES 34
C125 CAP 16 C294 CAP 16 C462 CAP 32 C630 CAP 31 C798 CAP 17 J9 CON_M80ST_D4MT_SM 17 Q75 TRA_2N7002DW 23 R156 RES 14 R330 RES 34
C126 CAP 16 C295 CAP 16 C463 CAP 32 C631 CAP 31 C799 CAP_P 32 J10 CON_M50SM_5MM 24 Q76 TRA_SUD45P03 31 R157 RES 12 R331 RES 34
C127 CAP 16 C296 CAP 16 C464 CAP 27 C632 CAP 31 C800 CAP 33 J11 CON_F14RT_S2MT_SM 32 Q77 TRA_SI3446DV 19 R158 RES 18 R332 RES 19
C128 CAP 16 C297 CAP 16 C465 CAP 27 C633 CAP 31 C801 CAP 32 J12 CON_F30ST_D_SM 25 Q78 TRA_2N7002DW 25 R159 RES 18 R333 RES 27
C129 CAP 20 C298 CAP 16 C466 CAP 27 C634 CAP 28 C802 CAP 31 J13 CON_M50SM_5MM 24 Q79 TRA_2N7002DW 33 R160 RES 5 R334 RES 27
C130 CAP 20 C299 CAP 19 C467 CAP 17 C635 CAP 28 C803 CAP 29 J14 CON_F30RT_T6MT_TH1 22 Q80 TRA_2N7002DW 19 R161 RES 8 R335 RES 27
C131 CAP 20 C300 CAP 19 C468 CAP 31 C636 CAP 23 C804 CAP 28 J15 CON_F5RT_MINIDIN_TH 22 Q81 TRA_2N7002DW 33 R162 RES 8 R336 RES 34
C132 CAP 20 C301 CAP 19 C469 CAP 25 C637 CAP 23 C805 CAP 29 J16 CON_10STSM_5087 25 Q82 TRA_2N7002DW 35 R163 RES 8 R337 RES 34
C133 CAP 20 C302 CAP 19 C470 CAP 9 C638 CAP 23 C806 CAP 33 J17 CON_RJ45_SHORT_4MT_TH 27 Q83 TRA_2N7002DW 35 R164 RES 8 R338 RES 9
C134 CAP 25 C303 CAP 19 C471 CAP 27 C639 CAP 33 C807 CAP 29 J18 CON_M8RT_S_SM 31 Q84 TRA_SI6467BDQ 35 R165 RES 8 R339 RES 19
C135 CAP 25 C304 CAP 21 C472 CAP 27 C640 CAP 28 C808 CAP 28 J19 CON_F200RT_DDRDIMM_SM1 11 Q85 TRA_SI6467BDQ 35 R166 RES 8 R340 RES 19
C136 CAP 5 C305 CAP 19 C473 CAP 19 C641 CAP 28 C809 CAP 35 J20 CON_F80ST_D4MT_SM 24 Q86 TRA_2N7002DW 34 R167 RES 8 R341 RES 19
C137 CAP 5 C306 CAP 19 C474 CAP 22 C642 CAP 28 C810 CAP 28 J22 CON_F200RT_DDRDIMM_SM2 11 Q87 TRA_2N7002DW 25 R168 RES 14 R342 RES 22
C138 CAP 5 C307 CAP 19 C475 CAP 27 C643 CAP 30 C811 CAP 33 J23 CON_F6RT_S4MT_TH1 29 R1 RES 22 R169 RES 12 R343 RES 27
C139 CAP 5 C308 CAP 8 C476 CAP 27 C644 CAP 32 C812 CAP 30 J24 CON_F40RT_S2MT_SM 23 R2 RES 7 R170 RES 12 R344 RES 27
C140 CAP 14 C309 CAP 16 C477 CAP 27 C645 CAP 28 C813 CAP 17 J25 CON_M8RT_S_SM 31 R3 RES 7 R171 RES 12 R345 RES 27
C141 CAP 16 C310 CAP 16 C478 CAP 25 C646 CAP 28 C814 CAP 23 J26 CON_F9RT_1394B_S6MT_SMA 29 R4 RES 7 R172 RES 18 R346 RES 27
C142 CAP 16 C311 CAP 19 C479 CAP 9 C647 CAP 21 C815 CAP 23 L1 IND 14 R5 RES 7 R173 RES 18 R347 RES 27
C145 CAP 16 C314 CAP 16 C482 CAP 11 C650 CAP 28 C818 CAP_P 28 L4 IND 18 R8 RES 24 R176 RES 8 R350 RES 33
A C147
C148
C149
CAP
CAP
CAP
16
14
5
C316
C317
C318
CAP
CAP
CAP
16
16
16
C484
C485
C486
CAP
CAP
CAP
22
32
27
C652
C653
C654
CAP
CAP
CAP
31
28
23
C820
C821
C822
CAP_P
CAP_P
CAP_P
32
32
32
L6
L7
L8
IND
IND
IND
22
28
31
R10
R11
R12
RES
RES
RES
7
7
7
R178
R179
R180
RES
RES
RES
8
8
12
R352
R353
R354
RES
RES
RES
19
27
27
A
C159 CAP 16 C328 CAP 19 C496 CAP 27 C664 CAP 30 C832 CAP 30 L21 FILTER_4P 22 R22 RES 7 R190 RES 35 R364 RES 31
43
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
R371 RES 27 R539 RES 33 R716 RES 25 U2 SN74AUC1G08 23
R372 RES 27 R540 RES 26 R717 RES 25 U3 ADT7460 25
R373 RES 17 R541 RES 32 R718 RES 22 U4 SN74AUC1G08 23
R374 RES 31 R542 RES 31 R719 RES 25 U5 SIL1162 20
R375 RES 31 R543 RES 31 R720 RES 14 U7 VREG_LT1962 14
R376 RES 34 R544 RES 30 R721 RES 21 U9 CBTV4020 10
R378 RES 33 R546 RES 28 R723 RES 25 U11 PI3B3257 34
R381 RES 27 R549 RES 31 R726 RES 25 U14 LTC3405 27
R382 RES 27 R550 RES 23 R727 RES 35 U15 COMPARATOR_LMC7211 31
R384 RES 34 R552 RES 23 R729 RES 21 U17 FEPR_1MX8 9
R386 RES 9 R554 RES 26 R731 RES 33 U19 PWR_CNTRL_TPS2211 17
R387 RES 9 R555 RES 28 R732 RES 34 U20 MAX1717 34
D
R389
R390
R391
RES
RES
RES
19
19
22
R557
R558
R559
RES
RES
RES
28
31
31
R734
R735
R736
RES
RES
RES
31
27
29
U22
U23
U24
MAX1715 35
AMP_MAX4172 31
7432 22 30
D
R392 RES 32 R560 RES 31 R737 RES 29 U25 VREG_LP2951 32
R393 RES 27 R561 RES 31 R738 RES 31 U26 PCI1510GGU 17
R396 RES 31 R564 RES 28 R741 RES 29 U29 TSB81BA3A 28
R397 RES 34 R565 RES 31 R742 RES 31 U30 VREG_LP2951 32
R399 RES 15 R567 RES 31 R744 RES 31 U32 EEPROM_16KX8_M24128B 23
R400 RES 22 R568 RES 23 R745 RES 24 U33 M16C62 30
R401 RES 32 R569 RES 30 R746 RES 31 U34 VREG_LM2594 28
R404 RES 27 R572 RES 30 R749 RES 31 U37 VREG_LT1962 28
R406 RES 27 R574 RES 28 R751 RES 29 U39 UPD720101_FBGA 26
R407 RES 34 R575 RES 28 R752 RES 29 U40 OPAMP_MAX4236EUTT 23
R408 RES 34 R576 RES 28 R753 RES 17 U42 CLK_GEN_CY28512 14
R409 RES 9 R577 RES 28 R754 RES 31 U43 APOLLO_MPC7445_360 5 6
R410 RES 19 R578 RES 31 R755 RES 31 U44 RAGE_MBLTY_M10_CSP64_667 18 19 21
R411 RES 24 R579 RES 31 R756 RES 17 U45 INTREPID 8 9 12 13 14 15
R413 RES 27 R581 RES 23 R758 RES 28 U47 CLK_GEN_CY25811 18
R414 RES 31 R582 RES 23 R759 RES 28 U49 TRANSCEIVER_88E1111 27
R415 RES 34 R583 RES 30 R760 RES 28 U50 OPAMP_LMC7111 31
R417 RES 35 R585 RES 30 R762 RES 17 U52 FEPR_256KX8_ST72264_BGA 23
R418 RES 35 R586 RES 26 R763 RES 31 U54 VREG_MM1571J 21
R419 RES 35 R587 RES 23 R764 RES 17 U55 VREG_MM1571J 21
R420 RES 35 R588 RES 31 R765 RES 30 U56 741G32 22
R421 RES 35 R589 RES 33 R766 RES 17 U57 741G32 22
R423 RES 35 R591 RES 26 R768 RES 30 XW1 SHORT 35
R432 RES 32 R600 RES 26 R777 RES 23 XW11 JUMPER 35
C R433
R434
R435
RES
RES
RES
32
34
27
R601
R602
R603
RES
RES
RES
24
24
24
R778
R779
R781
RES
RES
RES
30
29
28
XW12
XW13
XW15
SHORT
SHORT
SHORT
22
22
34
C
R447 RES 28 R617 RES 23 R793 RES 26 Y1 CRYSTAL 14
R452 RES 24 R623 RES 25 R798 RES 35 Y7 CRYSTAL_4PIN 30
R453 RES 29 R624 RES 13 R799 RES 35 ZT1 HOLE_VIA 4
R454 RES 31 R625 RES 14 R800 RES 35 ZT2 MTGHOLE 4
R469 RES 28 R644 RES 8 RP1 RPAK4P 14 ZT17 HOLE_VIA 4
B R477
R478
R479
RES
RES
RES
33
28
35
R653
R654
R655
RES
RES
RES
8
8
22
RP9
RP10
RP11
RPAK4P
RPAK4P
RPAK4P
24
24
24
ZT25
ZT26
ZT27
HOLE_VIA 4
HOLE_VIA 4
HOLE_VIA 4
B
R492 RES 30 R668 RES 8 RP24 RPAK4P 8 14 ZT40 HOLE_VIA 4
R507 RES 33 R683 RES 8 RP39 RPAK10P2C 17 ZT55 HOLE_VIA 4
A R520
R521
R522
RES
RES
RES
33
32
28
R697
R698
R699
RES
RES
RES
33
14
14
RP52
RP53
RP54
RPAK4P
RPAK4P
RPAK4P
23 26
23
26
ZT68
ZT69
ZT70
HOLE_VIA
HOLE_VIA
HOLE_VIA
4
4
4
A
R530 RES 26 R707 RES 14 SH1 SHLD_3P_EMI 4 ZT78 HOLE_VIA 4
R531 RES 26 R708 RES 14 SP1 SPKR_CLIP_P84 4 ZT79 HOLE_VIA 4
R535 RES 30 R712 RES 35 SP5 SPKR_CLIP_P84 4 ZT83 MTGHOLE 4
R536 RES 30 R713 RES 25 SP6 SPKR_CLIP_P84 4
R537 RES 25 R714 RES 22 T1 XFR_ENET_1000BT 27
R538 RES 33 R715 RES 35 U1 SN74AUC1G04 7
44
8 7 6 5 4 3 2 1

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8 7 6 5 4 3 2 1

A 285476 PRODUCTION RELEASED 07/28/03 ?

D PAGE CONTENTS PAGE CONTENTS D

SYSTEM BLOCK DIAGRAM

6 MPC7450 DATA 27 FIREWIRE A/B PHY GPU_SS

19 M10 LVDS/TMDS/VGA/GPIO & GPU VCORE 40-41 SIGNAL NAMES

20 M10 ANALOG, POWER, GND 42-43 COMPONENT LOCATIONS

VIDEO CONNECTORS - INVERTER, DVI, S-VIDEO

DIMENSIONS ARE IN MILLIMETERS

METRIC Apple Computer Inc.

SO-DIMM Connector I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

P.12 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

APPLE COMPUTER INC.

POWER SYSTEM ARCHITECTURE

SLEEP: RUNNING GPU_VCORE RUN/SS

BATTERY TURNS ON AT >1V

NO INRUSH PROTECTION +1_5V_SLEEP

BATTERY VOLTAGE 1_5V_2_5V_OK POWER BLOCK DIAGRAM

PG 31 (D3COLD) I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

APPLE COMPUTER INC.

OMIT BS1 CHGND2

LAYER COUNT: 12 CONDUCTIVE MOUNTS

SIGNAL TRACE WIDTH: 4 MILS OMIT

SEE PCB CAD FILES FOR MORE SPECIFIC INFO.

20R10 TH VIA OR VIA IN PAD

ZT24 ZT44 ZT72 ZT80 ZT3

3 SIGNAL (1/2 OZ) ZT36 ZT67 ZT29 ZT75 ZT31

ZT37 ZT71 ZT68 ZT51

ZT28 ZT78 ZT60 ZT42

ZT30 ZT69 ZT58 ZT64

ZT34 ZT65 ZT41 ZT76

ZT33 ZT47 ZT9 HOLE-VIA-20R10 ZT14

NOTICE OF PROPRIETARY PROPERTY

SIZE DRAWING NUMBER REV.

APPLE COMPUTER INC.

GND III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

APPLE COMPUTER INC.

BOOT BANGER - LMU PERORMS THIS FUNCTION IF NEEDED

36 8 CPU_DATA<25> N9 D25 NC M15

APPLE COMPUTER INC.

CPU FREQUENCY CONFIGURATION

CPU CONFIGURATION 13.5X

CPU_HRESET_L 2.5V INTERFACE II NOT TO REPRODUCE OR COPY IT

CPU_BUS_VSEL III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

10K 10K 10K 10K 10K 10K 10K 10K 5%

0: PLL5 (NO SPREAD)

0: PLL5 (NO SPREAD)

B MODE A (2.5X) IS FOR STATIC OPERATION

1: 60x bus (G3)

36 8 6 CPU_DATA<55> 1/16W NO BUS KEEPER - PU TEA E28 CPU_TEA_L 5 8 36

BIT2 BIT1 BIT0

0 0 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DDR_A_0 H35 MEM_ADDR<0> 9 36

D 36 10 MEM_DATA<2> AK31 DDR_DATA_2

36 10 MEM_DATA<58> DDR_DATA_58 36 9 MEM_ADDR<6> RAM_ADDR<6> 11 36