QP CODE: 21103239

B.Sc DEGREE (CBCS) REGULAR / REAPPEARANCE EXAMINATIONS,

DECEMBER 2021
Second Semester

Core Course - EL2CRT05 - DIGIT AL ELECTRONICS

(Common for B.Sc Electronics and Computer Maintenance Model III, B.Sc Electronics
Model III)

SCHEME IS PREPERAD FOR VAUTION OF REGULAR STUDENTS

For all other students distribute marks as per given in question paper. Answer keys are same.
 Part A
1.(a) 16 (b) 1/8
2.

3. This property tells us we can associate groups of added or multiplied variables together with
parentheses without altering the truth of the equations.

4. An open collector is a common type of output found on many integrated circuits (IC), which
behaves like a switch that is either connected to ground or disconnected. Instead of outputting a signal
of a specific voltage or current, the output signal is applied to the base of an internal NPN transistor
whose collector is externalized (open) on a pin of the IC. The emitter of the NPN transistor is
connected internally to the ground pin.

5. Fan-in refers to the maximum number of input signals that feed the input equations of a logic cell.
Fan-out refers to the maximum number of output signals that are fed by the output equations of a
logic cell.

6. A half subtractor is a combinational circuit that subtracts two bits and produces their difference. It
also has an output to specify if a 1 has been borrowed. Let us designate minuend bit as A and the
subtrahend bit as B. A Full Subtractor Circuit is a combinational circuit that performs a subtraction
between two bits, taking into account borrow of the lower significant stage. This circuit has three
inputs and two outputs. The three inputs are A, B and Bin, denote the minuend, subtrahend, and
previous borrow, respectively. The two outputs, D and Bout represent the difference and output
borrow, respectively.

7.
8. An encoder is a combinational circuit that converts binary information in the form of a 2 N input
lines into N output lines, which represent N bit code for the input. For simple encoders, it is assumed
that only one input line is active at a time. Example, : Octal to Binary encoder.

9. Set-Reset (SR) flip-flop or Latch. / JK flip-flop / D (Data or Delay) flip-flop. /T (Toggle) flip-flop.
10. Shift registers / Flip flops / Counters / Clocks / Used as registers inside microprocessors and
controllers to store temporary information.

11. Counter is a sequential circuit. A digital circuit which is used for a counting pulses is known
counter. Counter is the widest application of flip-flops. It is a group of flip-flops with a clock signal
applied. Counters are of two types. asynchronous or ripple counters and synchronous counters.

12. In a sequential circuit, the output changes depending on the triggering. There are two types of
triggering as edge and level triggering. There are two levels in a clock pulse or a signal.The main
difference between edge and level triggering is that in edge triggering, the output of the sequential
circuit changes during the high voltage period or low voltage period while, in level triggering, the
output of the sequential circuit changes during transits from the high voltage to low voltage or low
voltage to high voltage.

Part B
13. The key feature of the Excess-3 code is . that it is self-complementing. In other words, the l's
complement of an Excess- 3 number is the Excess- 3 code for the 9's complement of the
corresponding decimal number. Excess-3 codes are unweighted and can be obtained by adding 3 to
each decimal digit then it can be represented by using 4 bit binary number for each digit.

For example, the Excess- 3 code for decimal 6 is 1001.

Excess 3 code for decimal 2 is ….

For explanation 4 marks + for example 4 marks

14. Sum of Products (SOP): It is one of the ways of writing a boolean expression. As the name
suggests, it is formed by adding (OR operation) the product terms. These product terms are also called
as „min-terms‟. Min-terms are represented with „m‟, they are the product(AND operation) of boolean
variables either in normal form or complemented form.

X = A‟.B‟.C + A‟.B.C + A.B.C‟

Explanation 3 marks + SOP expression 1 mark + Any similar Logic diagram 4 marks
15. Emitter Coupled Logic or simply ECL, is another type of digital logic gate that uses bipolar
transistor logic where the transistors are not operated in the saturation region, as they are with the
standard TTL digital logic gate. Instead the input and output circuits are push-pull connected
transistors with the supply voltage negative with respect to ground. This has the effect of increasing
the speed of operation of the emitter coupled logic gates up to the Gigahertz range compared with the
standard TTL types, but noise has a greater effect in ECL logic, because the unsaturated transistors
operate within their active region and amplify as well as switch signals.
Give full mark for same or any similar explanation.
16. For logic diagram give 3 marks + for proper expiation with an example or explanation of TT give
5 marks

17. For block diagram 1 mark + circuit diagram 3 marks +TT 2 marks + Explanation 2 marks

18. For logic diagram 3 marks + TT 2 marks + Explanation 3 marks

19. Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit at a time, with the
stored data being available at the output in parallel form. If a logic “1” is connected to the DATA
input pin of FFA then on the first clock pulse the output of FFA and therefore the resulting QA will be
set HIGH to logic “1” with all the other outputs still remaining LOW at logic “0”. Assume now that
the DATA input pin of FFA has returned LOW again to logic “0” giving us one data pulse or 0-1-0.

For logic diagram 3 marks + truth table 2 marks + explanation 3 marks

20. For circuit diagram 3 marks + wave form 3 marks + explanation 2 marks

21. For circuit diagram 3 marks + wave form 3 marks + explanation 2 marks

Part C
22. De Morgan's First Theorem:- Statement - The complement of a logical sum equals the logical
product of the complements.
De Morgan's Second Theorem:- Statement - The complement of a logical product equals the logical
sum of the complements.

For both staemnets 3 marks + proof using logic gates 6 marks{3+3} + proof using truth table 6
marks (3+3)
23. Emitter-coupled logic (ECL) is the fastest logic circuit family available for conventional logic-
system design. 4 High speed is achieved by operating all bipolar transistors out of saturation, thus
avoiding storage-time delays, and by keeping the logic signal swings relatively small (about 0.8 V or
less), thus reducing the time required to charge and discharge the various load and parasitic
capacitances. Saturation in ECL is avoided by using the BJT differential pair as a current switch.
Explanation regarding ECL gate 5 marks + comparison with TTL and CMOS 5 mark each

24. The parity generator and parity checker‟s main function is to detect errors in data transmission.
The parity bit is an extra bit that is set at the transmission side to either „0‟ or „1‟, it is used to detect
only single bit error and it is the easiest method for detecting errors. There are different types of error
detection codes used to detect the errors they are parity, ring counter, block parity code, Hamming
code, biquinary, etc. The parity generator is a combination circuit at the transmitter, it takes an
original message as input and generates the parity bit for that message and the transmitter in this
generator transmits messages along with its parity bit. The parity bit or check bit are the bits added to
the binary code to check whether the particular code is in parity or not, for example, whether the code
is in even parity or odd parity is checked by this check bit or parity bit. The parity is nothing but
number of 1‟s and there are two types of parity bits they are even bit and odd bit.

For same or similar circuit diagrams 4 [parity checker] + 4 [parity generator] + for explanation 7 marks

25. To design a circuit diagram of decade asynchronous counter initially we draw the circuit
for MOD 16 asynchronous counter that counts from 0 to 15 by using four flip-flop (JK or T flipflop).
This must count from 0 to 9 and then come to 0. The initial state to be skipped is 1010 (10) here Q3
and Q1 are 1 and Q2 and Q0 are 0 if we obtain Q3 and Q1 and applied these to a NAND gate after
that the output of the NAND gate will be low only where Q3 and Q1 are high. Such signal can be
utilized to asynchronously clear all flipflops to make the counting state 0000. In this method MOD 16
counter will be limited to count 10 states i.e. from 0 to 9.
For circuit diagram 4 marks + timing diagram 4marks + truth table 2 marks +
Explanation 5 marks