ECE 3153:

MICROPROCESSORS
Dr. Anu Shaju Areeckal,
Asst. Professor, Dept of E&C, MIT Manipal

This ppt is for reference only. Use the referred textbooks as the main study material.
ARM Data Processing
Instructions

Credits: Dr. Bore Gowda, ECE, MIT

Introduction
There are certain attributes that all instructions have in common
All instructions are 32-bits long (i.e. they occupy one word) and
must lie on word boundaries
A 32-bit instruction enables 232 or about 4 billion possible
instructions
Obviously the ARM would not be much of a reduced instruction set
computer if it used all of these for wildly differing instructions
Different ARM architecture revisions support different instructions
However, new revisions usually add instructions and remain
backwardly compatible
Introduction
Features of ARM instructions
 Load-store architecture
 3-address instructions
 Conditional execution of every instruction
 Possible to load/store multiple registers at once
 Possible to combine shift and ALU operations in a single
instruction
 Most instructions execute in a single cycle
 Most instructions can be conditionally executed
 FLAGS AND THEIR USE
• Program Status Registers format

Q flag is used in Cortex-M4

 FLAGS AND THEIR USE
• CPSR-Current Program Status Register
• It contains condition code flags, interrupt enable flags, the current mode, and the
current state
• Allowing programs to recover from exceptions or branch on the results of an operation.

• SPSR-Saved Program Status Register

• Used to preserve the value of the CPSR when an exception occurs in each privileged
mode (except System mode).
• Since User mode and System mode are not entered on any exception, they do not have
an SPSR, and a register to preserve the CPSR is not required.
• In User mode or System mode, if you attempt to read the SPSR, you will get an
unpredictable value back
• If you attempt to write to the SPSR in one of these modes, the data will be ignored.
 FLAGS AND THEIR USE
• Current Program Status Register format
• Condition code flags(4-bit) - N, Z, C, and V
• Helps to determine whether or not an instruction will be conditionally executed.
• The flags are set and cleared based on one of four things:
i. Instructions that are specifically used for setting and clearing
flags, such TST or CMP
ii. Instructions that are told to set the flags by appending an “S”
to the mnemonic.
iii.A direct write to the Program Status Register, where you
explicitly set or clear flags
iv.A 16-bit Thumb ALU instruction
• ARM7TDMI the processor can conditionally execute an instruction using these bits to
improve in code density and speed.
 FLAGS AND THEIR USE
• N Flag
• useful when checking for a negative result.
• a two’s complement number is considered to be negative if the MSB bit is set.
• Example 1 : Adding two negative numbers (say -1(0xFFFFFFFF) and -2(0xFFFFFFFE))

• Example 2: Adding two positive numbers (say 0x7B000000 and 0x30000000)

• Here, the addends are positive in two’s complement notation, but the sum is negative
• Since MSB of result is set, this causes N bit to be set
• Value of the N bit does not matter for unsigned operation
 FLAGS AND THEIR USE
• V Flag
• indicates a signed overflow
• Overflow occurs if the result of an add, subtract, or compare is greater than or equal to
231, or less than –231.
• V flag status determined as an EX-OR of the carry bit going into the MSB of the result
with the carry bit coming out of the MSB
• Example 1: 0xA1234567 + 0xB0000000
• Two signed values (in 2’s complement)
are added to produce the sum, which
does not fit into 32 bits.

• Example 2: 0x7B000000 + 0x30000000 • The result fits into 32 bits. But, the result
would be interpreted as a negative
number.
• Both N and V bits would be set in CPSR.
 FLAGS AND THEIR USE
• Z Flag
• Set i.e. 1 when the result of an operation produces zero, meaning all 32 bits must be
zero.
• This might be the result of a counter expiring, or a routine might need to examine an
operand before performing some other kind of arithmetic routine, such as division.

• Example 1: 0x23004500 – 0x12345678

• Example 2: 0x23004500 – 0x23004500

 FLAGS AND THEIR USE
• C Flag
• set if:
i. the result of an addition is greater than or equal to 232
ii. the result of a subtraction is positive, or
iii. as the result of an inline barrel shifter operation in a move or
logical instruction.
LDR r3, =0x7B000000
LDR r7, =0xF0000000
• Example 1: 0x7B000000 + 0xF0000000
ADDS r4, r7, r3
; value exceeds 32 bits, C bit will be set

• Example 2: 0xC0000000 - 0x80000000 ; Result is positive, No borrow, C flag =1

 FLAGS AND THEIR USE
• C Flag
• allows us to build operations with greater precision, e.g., creating routines to add 64-bit
numbers
 eg. To add two 64-bit numbers
 eg. To subtract two 64-bit numbers
 FLAGS AND THEIR USE
• C Flag
• allows us to build operations with greater precision, e.g., creating routines to add 64-bit
numbers
 To subtract two 64-bit numbers:
0x7000BEEFC0000000
− 0x3000BABE80000000
Ans = 0x4000043140000000

 The first subtraction operation will set the C flag, since result is positive.
 The second subtraction is a subtract with carry (SBC) operation, using the carry bit to
perform a normal subtraction.
 If the carry bit had been clear, the SBC instruction would have subtracted one more
from its result.
Data Processing
Instructions
ARM Instruction Set
Instruction classes
1. Data processing instructions
• Group does most of the work
• Sixteen instructions, and they have very similar formats
• Examples - ADD and CMP, which add and compare two numbers respectively
• Operands of these instructions are always in registers (or an immediate
number stored in the instruction itself), never in memory
2. Data transfer instructions
• This is a smaller group of two instructions: load a register and save a register.
Variations include whether bytes or words are transferred, and how the
memory location to be used is obtained.
3. Branching
• Although the PC may be altered using the data operations to cause a change
in the program counter, the branch instruction provides a convenient way of
reaching any part of the 64M byte address space in a single instruction. It
causes a displacement to be added to the current value of the PC. The
displacement is stored in the instruction itself.
 DATA PROCESSING INSTRUCTIONS
An ARM instruction is 32 bits long, so there are around 4 billion different binary
machine instructions
Hexadecimal numbers are represented with prefix 0x
Binary numbers with the prefix 0b.
The examples follow the format shown below:
PRE <pre-conditions>
<instruction/s>
POST <post-condition>
In the pre- and post-conditions, memory is denoted as
Mem<data_size>[address]
Example: mem32[1024] is 32-bit value starting at address 1024.
ARM instructions process data held in registers and only access memory with load and
store instructions.
ARM instructions commonly take two or three operands.
 DATA PROCESSING INSTRUCTIONS
The data processing instructions manipulate data within registers.
• Data movement instructions
• MOV, MVN
• <opcode>{cond}{S} Rd, <Op2>
• single operand instructions
• Arithmetic instructions
• ADD, ADC, SUB, SBC, RSB, RSC
• <opcode>{cond}{S} Rd, Rn, <Op2>
• Logical instructions
• AND, ORR, EOR, BIC
• <opcode>{cond}{S} Rd, Rn, <Op2>
• Comparison instructions
• CMP, CMN, TST, TEQ
• <opcode>{cond} Rn, <Op2>
• instructions which do not produce a result; only updates flags
• Multiply instructions
• MUL, MLA
 DATA PROCESSING INSTRUCTIONS
Most data processing instructions can process one of their operands using the barrel
shifter.
If the S suffix in a data processing instruction is used then it updates the flags in the
CPSR.
Move and logical operations update the carry flag C, negative flag N and zero flag Z.
carry flag = 1, when the result of the barrel shift as the last bit shifted out.
N flag = 1, when the bit 31 of the result is 1.
Z flag is set if the result is zero.

{cond} is a two-character condition mnemonic

Data Processing Instructions
 Data Processing Instructions: Move Instructions
MOV
MOV{cond}{S} Rd, Operand2
MVN
MVN{cond}{S} Rd, Operand2
 Data Processing Instructions:
Barrel Shifter
N can be register or immediate value or a register Rm that has been
preprocessed by the barrel shifter prior to being used by a data
processing instruction.
Data processing instructions are processed within the ALU.
A unique and powerful feature of the ARM processor is the ability to
shift the 32-bit binary pattern in one of the source registers left/right
by a specific number of positions before it enters the ALU.
This shift increases the power and flexibility of many data processing
operations.
All data processing instructions do not use the barrel shifter (ex:
MUL).
Pre-processing or shift occurs within the cycle time of instruction.
This is particularly useful for loading constants into a register and
achieving fast multiplies or division by a power of 2.
 Data Processing Instructions: Barrel Shifter
Shift and Rotates in ARM
 Data Processing Instructions: Barrel Shifter
Barrel shifter operations

25
 Data Processing Instructions: Barrel Shifter
• Barrel shifter operation syntax for data processing instructions

The second operand N can be an immediate constant preceded by #, a register

value Rm or the value of Rm processed by a shift.
Data Processing Instructions: Barrel Shifter

Example
ARITHMETIC
INSTRUCTIONS
 Data Processing Instructions: Arithmetic Instructions
The arithmetic instructions perform addition and subtraction of 32-bit signed and unsigned values.
N is the result of the shifter operation. The syntax of shifter operation is shown previously.
 Data Processing Instructions:
Arithmetic Instructions

Examples:
• ADD r1, r2, r3 ; r1 = r2 + r3
• ADC r1, r2, r3 ; r1 = r2 + r3 + C
• SUB r1, r2, r3 ; r1 = r2 - r3
• SUBC r1, r2, r3 ; r1 = r2 - r3 + C - 1
• RSB r1, r2, r3 ; r1 = r3 - r2
• RSC r1, r2, r3 ; r1 = r3 - r2 + C - 1
 Data Processing Instructions: Arithmetic Instructions
Example - subtraction
PRE r0 = 0x00000000
r1 = 0x00000002
r2 = 0x00000001
SUB r0, r1, r2
POST r0 = 0x00000001

Example – reverse subtraction

PRE r0 = 0x00000000
r1 = 0x00000077
RSB r0, r1, #0 ; Rd = 0x0 - r1
POST r0 = -r1 = 0xFFFFFF89
 Data Processing Instructions:
Arithmetic Instructions
Example - The SUBS instruction is useful for decrementing loop counters. In this
example the immediate value #1 is subtracted from the value 1 stored in register r1.
The result value 0 is written to register r1. The cpsr is updated with the Z flag being
set.

PRE cpsr = nzcvqiFt_USER

r1 = 0x00000001
SUBS r1, r1, #1
POST cpsr = nZcvqiFt_USER
r1 = 0x00000000
 Data Processing Instructions: Arithmetic Instructions
• Inline barrel shifter is very useful for arithmetic and logical instructions.
• Example - Register r1 is first shifted one location to the left to give the value of twice r1.
• The ADD instruction then adds the result of the barrel shift operation to register r1.
• The final result transferred into register r0 is equal to three times the value stored in
register r1.

PRE r0 = 0x00000000
r1 = 0x00000005
ADD r0, r1, r1, LSL #1
POST r0 = 0x0000000f
r1 = 0x00000005
 Data Processing Instructions: Arithmetic Instructions
 The second operand can make use of the barrel shifter when performing addition and
subtraction, such as:

• SUB r0, r0, r2, LSL #2 ; r0 = r0 − (r2 <<2) = r0 – r2*4

• ADD r1, r1, r3, LSR #3 ; r1 = r1 + (r3 >>3)

 SUB r0, r2, r3, LSL #2 ; r0 = r2 – r3*4

 RSB r0, r3, r2, LSL #2 ; r0 = r2*4 – r3 ; reverse subtraction
 Data Processing Instructions: Arithmetic Instructions
• Addition of 64-bit numbers:
• For a 64-bit addition, since the registers are only 32 bits wide, we must store the two
addends in two registers each, and the sum would have to be stored in two registers.
 Example: The following two instructions add a 64-bit integer contained in registers r2
and r3 to another 64-bit integer contained in registers r0 and r1, and place the result in
registers r4 and r5.
• ADDS r4,r0,r2 ; adding the least significant words
• ADC r5,r1,r3 ; adding the most significant words
Exercise program- Homework
3. Write an ALP to load any two 32 bit numbers. Find the
greater of the two numbers and subtract the lesser
number from the greater number.
• Hint: Use SUB and RSB

4. WAP to add two 64-bit numbers from memory and

store the result into data memory.
• Hint: Use ADD and ADC

5. WAP to subtract two 64-bit numbers.

• Hint: Use SUB and SBC

38
 To subtract two 64-bit numbers:
0x7000BEEFC0000000
− 0x3000BABE80000000
Ans = 0x4000043140000000

 The first subtraction operation will set the C flag, since result is positive.
 The second subtraction is a subtract with carry (SBC) operation, using the carry bit to
perform a normal subtraction.
 If the carry bit had been clear, the SBC instruction would have subtracted one more
from its result.
 Data Processing Instructions: Arithmetic Instructions
Example: Write an ARM7TDMI assembly program to perform
the function of absolute value. Register r0 will contain the
initial value, and r1 will contain the absolute value.
• Solution:
AREA Prog7a, CODE, READONLY
ENTRY
MOVS r1, r0
RSBLT r1, r1, #0
• done B done
END
LOGICAL INSTRUCTIONS
 Data Processing Instructions: Logical Instructions
Logical instructions perform bitwise logical operations on the two source registers.
Syntax: <instruction>{<cond>}{S} Rd, Rn, N

Example - This example shows a logical OR operation between registers r1 and r2. r0 holds the
result.
PRE r0 = 0x00000000
r1 = 0x02040608
r2 = 0x10305070
ORR r0, r1, r2
POST r0 = 0x12345678
 Data Processing Instructions: Logical Instructions
Example - Logical instruction BIC carries out a logical bit clear.
PRE r1 = 0b1111, r2 = 0b0101 ;(0b indicates binary number)
BIC r0, r1, r2
POST r0 = 0b1010
In this example, register r2 contains a binary pattern where every binary 1 in r2 clears a
corresponding bit location in register r1.
This instruction is particularly useful when clearing status bits and is frequently used to
change interrupt masks in the cpsr.
The logical instructions update the cpsr flags only if the S suffix is present.
These instructions can use barrel-shifted second operands in the same way as the
arithmetic instructions.
This is equivalent to Rd = Rn AND NOT(N).
COMPARISON
INSTRUCTIONS
 Data Processing Instructions: Comparison instructions
• There are four instructions that do nothing except set the condition codes or
test for a particular bit in a register: CMP, CMN, TST, TEQ
• CMP—Compare
 CMP subtracts a register or an immediate value from a register value and updates the
condition codes.
 You can use CMP to quickly check the contents of a register for a particular value, such
as at the beginning or end of a loop.
• CMN—Compare negative
 CMN adds a register or an immediate value to another register and updates the
condition codes.
 This instruction is actually the inverse of CMP, and the assembler will replace a CMP
instruction when appropriate. For example, if you typed
• CMP r0, #-20
• the assembler will instead generate
• CMN r0, #0x14
 Data Processing Instructions: Comparison instructions
• Example:

• Another example:
CMP r0,r1
SUBGT r2,r0,r1
SUBLT r2,r1,r0 ;or RSBLT r2,r0,r1
 Data Processing Instructions: Comparison instructions
• TST—Test
 TST logically ANDs an arithmetic value with a register value and updates
the condition codes without affecting the V flag.
 TST can be used to determine if many bits of a register are all clear or if
at least one bit of a register is set.
• TEQ—Test equivalence
 TEQ logically XORs an arithmetic value with a register value and updates
the condition codes without affecting the V flag.
 TEQ can be used to determine if two values are the same.
• The syntax for these instructions is
• instruction{<cond>} <Rn>, <operand2>
• where {<cond>} is one of the optional conditions, and
<operand2> can be a register with an optional shift, or an
immediate value.
 Data Processing Instructions: Comparison instructions
• Example:
MULTIPLY INSTRUCTIONS
 Data Processing Instructions: Multiply
 MUL multiplies the values in two registers, truncates the result
to 32 bits, and stores the product in a third register.
• MUL r4, r2, r1 ; r4 = r2 * r1
• MULS r4, r2, r1 ; r4 = r2 * r1, then set the flags
MLA multiplies two registers, truncates the results to 32 bits,
adds the value of a third register to the product, and stores the
result in a fourth register
• MLA r7, r8, r9, r3 ; r7 = r8 * r9 + r3
 Both MUL and MLA can optionally set the N and Z condition
code flags.
 For multiplications that produce only 32 bits of result, there is
no distinction between signed and unsigned multiplication. Only
the least significant 32 bits of the result are stored in the
destination register, and the sign of the operands does not affect
this value.
 Data Processing Instructions: Multiply
 Multiply long instructions produce 64-bit results. They multiply the
values of two registers and store the 64-bit result in a third and fourth
register.
 SMULL and UMULL are signed and unsigned multiply long
instructions:
• SMULL r4, r8, r2, r3 ; r4 = bits 31-0 of (r2*r3)
; r8 = bits 63-32 of (r2*r3)
• UMULL r6, r8, r0, r1 ; {r8,r6} = r0*r1
 The instructions below multiply the values of two registers, add the
64-bit value from a 3rd and 4th register, and store the 64-bit result in
the 3rd and 4th registers:
• SMLAL r4, r8, r2, r3 ; {r8,r4} = r2*r3 + {r8,r4}
• UMLAL r5, r8, r0, r1 ; {r8,r5} = r0*r1 + {r8,r5}
 All four multiply long instructions can optionally set N and Z condition
flags.
 Data Processing Instructions: Multiply
 The inline barrel shifter can be used in conjunction with other
instructions, such as ADD or SUB, in effect getting a multiplication.
 This feature is used to its full advantage when certain multiplications
are done using the barrel shifter instead of the multiplier array.
 Consider the case of multiplying a number by a power of two. This
can be written using only an LSL instruction, i.e.,
• LSL r0, r1, #2 ; r0 = r1*4
 But what if we wanted to multiply two numbers, one of which is not a
power of two, like 5? Examine the following instruction:
• ADD r0, r1, r1, LSL #2 ; r0 = r1 + r1*4 = r1*5
 By using only the 32-bit adder and a barrel shifter,
𝑛 𝑛
the ARM 𝑛
processors can generate multiplications by 2 , 2 − 1 and 2 + 1 in a
single cycle, without having to use a multiplier array. This saves some
execution time.
 Data Processing Instructions: Multiply
• Example for multiplication by 2𝑛 − 1 :
• RSB r0, r2, r2, LSL #3 ; r0 = r2*8 - r2 = r2*7
• will perform a multiplication by 7 by taking register r2, shifting it left by 3
bits, yielding a multiplication by 8, and then subtracting register r2 from the
product.
 Note that the reverse subtract instruction was used here, since an
ordinary subtraction will produce the wrong result.
 By chaining together multiplications, for example, multiplying by 5
and then by 7, larger constants can be created.
 Examine the following code to see that you can create multiplier
arguments that are not powers of two, say 115:
• ADD r0, r1, r1, LSL #1 ; r0 = r1*3
• SUB r0, r0, r1, LSL #4 ; r0 = (r1*3) − (r1*16) = r1* (− 13)
• ADD r0, r0, r1, LSL #7 ; r0 = (r1* (− 13)) + (r1*128) = r1*115
 Homework Exercise:
Read and understand the example on
Hamming codes (given as Example 7.7 in
Reference book by William Hohl)

55
Data processing
instruction- Bit format
Data processing instruction format
31 28 27 26 25 24 21 20 19 16 15 12 11 0

cond 00 # opcode S Rn Rd operand 2

destination register
first operand register

set condition codes

arithmetic/logic function

25 11 8 7 0

1 #rot 8-bit immediate

immediate alignment
11 7 6 5 4 3 0

#shift Sh 0 Rm

25 immediate shift length

0 shift type
second operand register
11 8 7 6 5 4 3 0

Rs 0 Sh 1 Rm

register shift length

57
Data processing instruction format
Bits [31-28] Condition

58
Data processing instruction format
Bits [27-26] – 00
Bit 25- Immediate bit
Bits [24 – 21] - Opcode bits, specifies the type of the operation
31 28 2726 25 24 21 20 19 1615 12 11 0
cond 0 0 # opcode S Rn Rd operand 2

destination register
first operand register
set condition codes
arithmetic/logic function

25 11 8 7 0
1 #rot 8-bit immediate

immediate alignment
11 7 6 5 4 3 0
#shift Sh 0 Rm

25 immediate shift length

0 shift type
second operand register
11 8 7 6 5 4 3 0
Rs 0 Sh 1 Rm

register shift length 59

 Data processing instructions
Bits [24 – 21] - Opcode bits
Opcode (binary) Opcode Function Description
0000 AND Logical bit wise AND Rd=op1 AND op2
0001 EOR Logical bit wise Exclusive or Rd=op1 EOR op2
0010 SUB Subtract Rd=op1 – op2
0011 RSB Reverse Subtract Rd=op2 – op1
0100 ADD Add Rd=op1+op2
0101 ADC Add with carry Rd=op1+op2+C
0110 SBC Subtract with carry Rd=op1 – op2 +C – 1
0111 RSC Reverse subtract with carry Rd = op2 – op1 +C – 1
1000 TST Test Set condition code on op1 AND op2.
1001 TEQ Test Equivalence Set condition code on op1 EOR op2.
1010 CMP Compare Set condition code op1 – op2.
1011 CMN Compare Negated Set condition code on op2+op1.
1100 ORR Logical bit wise OR Rd= op1 OR op2.
1101 MOV Move Rd = op2
1110 BIC Bit clear Rd= op1 AND NOT op2.
1111 MVN Move negated Rd = NOT op2. 60
Data processing instruction format
Bits [20] – Set condition codes
◦ 1 – set condition codes according to results
◦ 0 – do not alter condition codes
Bit [19 – 16] Rn – 1st operand register
Bits [15 –12] Rd – Destination register
31 28 2726 25 24 21 20 19 1615 12 11 0
cond 0 0 # opcode S Rn Rd operand 2

destination register
first operand register
set condition codes
arithmetic/logic function

25 11 8 7 0
1 #rot 8-bit immediate

immediate alignment
11 7 6 5 4 3 0
#shift Sh 0 Rm

25 immediate shift length

0 shift type
second operand register
11 8 7 6 5 4 3 0
Rs 0 Sh 1 Rm
61
register shift length
 Data processing instruction format
31 28 27 26 25 24 21 20 19 16 15 12 11 0

cond 00 # opcode S Rn Rd operand 2 4-bit rotate value (0-

15) is multiplied by
two to give range 0-
destination register
30 in steps of 2
first operand register
Rule to remember is
set condition codes “8-bits rotated right
arithmetic/logic function by an even number of
25 11 8 7 0
bit positions”
1 #rot 8-bit immediate

immediate alignment
11 7 6 5 4 3 0

#shift Sh 0 Rm

25 immediate shift length

0 shift type
second operand register
11 8 7 6 5 4 3 0

Rs 0 Sh 1 Rm

register shift length

62
Data processing instructions
Barrel Shifter
The ARM does not have actual shift instructions
Instead it has a barrel shifter which provides a mechanism to carry out shifts as part
•
of other instructions
So what operations does the barrel shifter support?

63
REFERENCE TEXTBOOKS
• William Hohl, “ARM assembly language
fundamentals and techniques”, CRC press, 2009
• Andrew N Sloss, “ARM System developer’s guide,
designing and optimizing system software”,
Elsevier, 2004
• J. R. Gibson, “ARM Assembly Language-an
Introduction”, Dept. of Electrical Engineering and
Electronics, The University of Liverpool, 2007