Compiler Design (CSE 335)

Intermediate Code Representation

Papia Akter
Lecturer, Dept. of CSE
Prime University
 Intermediate Code Representation

Q: A source code can directly be translated into its target machine code, then why at all we need to
translate the source code into an intermediate code which is then translated to its target code?

 If a compiler translates the source language to its target machine language without having the option
for generating intermediate code, then for each new machine, a full native compiler is required.
 Intermediate code eliminates the need of a new full compiler for every unique machine by keeping the
analysis portion same for all the compilers.
 The second part of compiler, synthesis, is changed according to the target machine.
 It becomes easier to apply the source code modifications to improve code performance by applying
code optimization techniques on the intermediate code.
 Intermediate Representation (IR)
Intermediate codes can be represented in a variety of ways and they have their own benefits.
 High Level IR - High-level intermediate code representation is very close to the source language
itself. They can be easily generated from the source code and we can easily apply code
modifications to enhance performance. But for target machine optimization, it is less preferred.
 Low Level IR - This one is close to the target machine, which makes it suitable for register and
memory allocation, instruction set selection, etc. It is good for machine-dependent optimizations.
Intermediate code can be either language specific (e.g., Byte Code for Java) or language independent
(three-address code).
 Three-Address Code
Intermediate code generator receives input from its predecessor phase, semantic analyzer, in the
form of an annotated syntax tree. That syntax tree then can be converted into a linear representation,
e.g., postfix notation. Intermediate code tends to be machine independent code. Therefore, code
generator assumes to have unlimited number of memory storage (register) to generate code.
For example:
a = b + c * d;
The intermediate code generator will try to divide this expression into sub-expressions and then
generate the corresponding code.
r1 = c * d;
r2 = b + r1;
a = r2
r being used as registers in the target program.
 Practice Problems Based on Three Address Code

Problem-01:
Write Three Address Code for the following expression:
a=b+c+d
Solution:
The given expression will be solved as-

Three Address Code for the given expression is:

(1) T1 = b + c
(2) T2 = T1 + d
(3) a = T2
Problem-02:

Write Three Address Code for the following expression:

-(a x b) + (c + d) – (a + b + c + d)
Solution:

Three Address Code for the given expression is:

(1) T1 = a x b
(2) T2 = uminus T1
(3) T3 = c + d
(4) T4 = T2 + T3
(5) T5 = a + b
(6) T6 = T3 + T5
(7) T7 = T4 – T6
 Three Address Code Representation

A three-address code has at most three address locations to calculate the expression. A three-address code
can be represented in two forms :
• Quadruples and
• Triples.

Quadruples
Each instruction in quadruples presentation is divided into four fields: operator, arg1, arg2, and result.
The example (a = b+c*d) is represented below in quadruples format:

Op arg1 arg2 result

* c d r1
+ b r1 r2
= r2 a
Triples
Each instruction in triples presentation has three fields: op, arg1, and arg2.

Op arg1 arg2
* c d
+ b (0)
= (1)

Practice Problems Based on Quadruples &Triples

Problem-01:
Translate the following expression to quadruple, and triple
a+bxc/e↑f+bxa
Solution:
Three Address Code for the given expression is:
T1 = e ↑ f
T2 = b x c
T3 = T2 / T1
 T4 = b x a
T5 = a + T3
T6 = T5 + T4

Quadruple Representation: Triple Representation:

Location Op Arg1 Arg2 Result

Location Op Arg1 Arg2
(0) ↑ e f
(0) ↑ e f T1
(1) x b c
(1) x b c T2
(2) / (1) (0)
(2) / T2 T1 T3
(3) x b a T4 (3) x b a

(4) + a T3 T5 (4) + a (2)

(5) + T5 T4 T6 (5) + (4) (3)
Problem-02:
Translate the following expression to quadruple, and triple.
a=bx–c+bx–c
Solution:
Three Address Code for the given expression is:
T1 = uminus c
T2 = b x T1
T3 = uminus c
T4 = b x T3
T5 = T2 + T4
a = T5
 Quadruple Representation: Triple Representation:

Location Op Arg1 Arg2

Location Op Arg1 Arg2 Result
(0) uminus c
(1) uminus c T1
(1) x b (0)
(2) x b T1 T2
(2) uminus c
(3) uminus c T3
(3) x b (2)
(4) x b T3 T4
(5) + T2 T4 T5 (4) + (1) (3)

(6) = T5 a (5) = a (4)