UNIT 3

Combination Logic Realization

3.1 Introduction:
A combinational circuit consists of input variables, logic gates, and output variables. The logic gates
accept signals from the inputs and generates to the output. Both input and output data are represented by
binary signals i.e. They exist in two possible values logic-1 and logic -0.
Each input variable to a combinational circuit may have one or two wires. One wire available
may represent either in normal form (unprimed) or in complement form (prime) with inverter for each
literal not available input wire. On the other hand, input variable may appear in two wires with both
normal and complement form to input of the circuit.

3.1.1 Karnaugh Map or K-Map

The complexity of digital logic gates that implement a Boolean function is directly related to algebraic
expression, represented in truth table in different forms. Map method provides a simple, straight forward
procedure for minimizing Boolean functions with either a pictorial form of truth table or an extension of
Venn diagram. This method was first proposed by Veitch(1) and slightly modified by Karnaugh(2), also
known as “Veitch diagram” or the “Karnaugh Map”.
 The k-map is a diagram made up of grid of squares.
 Each square represents one minterm.
 The minterms are ordered according to Gray code (only one variable changes between adjacent
squares).
 Squares on edges are considered adjacent to squares on opposite edges.
 Karnaugh maps become awkward to use with more than 4 variables.
By recognizing various patterns, the user can derive alternative algebraic expression for same functions,
selecting the simplest one with minimum number of literals.
Two variable maps
For n-variable k-map 2n cells are required. Therefore for two variables k-map; 22=4 squares, one for each
minterm, as shown in Figure will be required. There are four minterms for a Boolean function with two
variables.
A B 0 1 A B B B
A’B’ A’B
00 01 A’
10 11
AB’ AB
A
Fig: Two-variable map
Three variable map
To construct 3-variable k-map 23=8 cells are required. Therefore, a three-variable map consists of eight
squares, as shown in Figure. There are eight minterms for three binary variables.
A BC 00 01 11 10 AB C 0 1
00 000 001 011 010 000 001

100 101 111 110 010 011

110 111
Fig: Three-variable map
100 101

Four variable K-Map

To construct 4-variable k-map 24=16 cells are required. Therefore, a four-variable map consists of sixteen
squares, as shown in Figure. There are sixteen minterms for four binary variables.
AB CD 00 01 11 10
00 0000 0001 0011 0010

01 0100 0101 0111 0110

1100 1101 1111 1110

11

10 1000 1001 1011 1010

Example: Plot the Boolean Expression:

Y=A’BC’D’+AB’CD’+A’BCD’+ABC’D
Y= 0100 + 1010 + 0110 + 1101
m4 m10 m6 m13
Y=∑m(4,6,10,13)
Other way to fill.
AB CD 00 01 11 10 AB CD C’D’ C’D CD CD’
0000 0001 0011 0010
00
01 0100 0101 0111 0110

11 1100 1101 1111 1110

10 1000 1001 1011 1010

3.2 Analysis of SOP and POS expression

An arbitrary logic function can be expressed in the following forms:
I) Sum of Product (SOP)
II) Product of Sum (POS)
Product term: The AND function is referred to as a product. The variable is a product term that can appear
either in complemented or uncomplemented (normal) form. For example AB’C or ABC is a product form.
Sum term: The OR function is generally used to refer as sum. For example; A+B+C’ is a sum term.

3.2.1 Sum of Products (SoP)

The logical sum of two or more product term is called a “Sum of Product” expression. It is basically an
OR operation of AND operational variables such as F=A’B+B’C+A’BC
This expression has three sums of two and three literals. SOP can have the term ABC but not
ABC.

3.2.1.1 AND/OR implementation of an SoP expression

It simply requires ORing the outputs of two or more AND gates. For expression AB+BCD+AC, the
output X of the R gate equal to SOP expression.
A
B
B X=AB+BCD+AC
C
D
A
C

3.2.1.2 NAND/NAND implementation of a SOP expression

NAND gates can be used to implement SOP expression. By using only NAND gates, an
AND/OR function can be accomplished.
A
B
B X=AB+BCD+AC
C
D
A
C
Fig: NAND/NAND implementation of AND/OR.
3.2.2 Conversion of general expression to SOP form.
Any logic expression can be changed into SOP form by applying Boolean algebra techniques.
e.g. A(B+CD)=AB+ACD (using distributive law)
The standard SOP form
It is one in which all the variables in domain (Boolean expression with set of variables) appear in each
product term in the expression. It is important in constructing truth tables.
SOP form
Total number combinations = 2n, number of variables (n)
There are two ways to express function in Boolean algebra i.e. SOP form (minterms-m) and POS (max
terms-M) form. SOP form is written when the function is high (1).
Minterms - m0 A B C F
m1 0 0 0 0
m2 0 0 1 0
m3 0 1 0 1
m4 0 1 1 0 F(A,B,C) = m2+m4+m5+m6+m7
1 0 0 1
m5 = ∑m(2,4,5,6,7)
1 0 1 1
m6 1 1 0 1 F = ABC+ABC+ABC+ABC+ABC
m7 1 1 1 1 (standard/canonical form- since it is written directly
from the truth table)
Also, we can use laws of Boolean algebra to find minimal SoP form.
3.2.2 Products of Sum (PoS)
The logical product of two or more sums is called “Product of Sum” expression. It is basically an
AND operation of OR operated variables. Such as F=(A’+B).(B’+C).(A’+B+C)
A POS expression can contain a single variable term as in A(A+B+C)(B+C+D). In POS expression, a
single over bar cannot extend over more than one variable.
3.2.2.1 Implementation of a PoS expression
It simply requires ANDing the outputs two or more OR gates. For expression (A+B)(B+C+D)(A+C). The
output X of the AND gate equals to POS expression.
A
B
A X=(A+B)(A+B+C)(A+C)
B
C
A
C

The standard PoS form

It is one in which all the variables in the domain appears in each sum term in the expression. Any non
standard PoS expression (simply PoS) can be converted to standard form using Boolean algebra. PoS
form is used (written) when the function is low.
Maxterms - M0 A B C F
M1 0 0 0 0
M2 0 0 1 0
M3 0 1 0 1
M4 0 1 1 0
1 0 0 1
M5
1 0 1 1
M6 1 1 0 1 F = (A+B+C).(A+B+C).(A+B+C)
M7 1 1 1 1 (Standard/Canonical POS form with maxterms)

In SOP form: F=A.B.C+A.BC+A.B.C

Complementing both sides, we get.
( F)= (A.B.C+A.B.C+A.B.C)
= (A.B.C)’.(A.B.C)’.(A.B.C)’
F = (A+B+C).(A+B+C).(A+B+C)
In standard POS form, each maxterm will have all the variables in normal or complemented form.
Boolean algebra can be used to reduce standard/canonical PoS form to minimal PoS form.
F=(A+B+C)(A+B+C)(A+B+C)
Assuming A+B as X, we get
F=(X+C.C).(A+B+C)
F=(A+B)(A+B+C)
F=A+B(B+C)
Y=A+B.B+BC
Y =A+BC
Y=(A+B)(A+C) – minimal SoP form

3.3 Combinational analysis procedure:

It starts with a given logic diagram and culminates with a set of Boolean functions, a truth table, or a
verbal explanation of the circuit operation.
Obtaining Boolean functions from logic diagram
Steps in analysis:
1. The first step in the analysis is to make sure that the given circuit is combinational and not sequential.
2. Assign symbols to all gate outputs that are a function of the input variables. Obtain the Boolean
functions for each gate.
3. Label with other arbitrary symbols those gates that are a function of input variables and/or previously
labeled gates. Find the Boolean functions for these gates.
4. Repeat step 3 until the outputs of the circuit are obtained.
5. By repeated substitution of previously defined functions, obtain the output Boolean functions in terms
of input variables only.
Analysis of the combinational circuit below illustrates the proposed procedure:

We note that the circuit has three binary inputs, A, B, and C, and two binary outputs, F1 and F2. The
outputs of various gates are labeled with intermediate symbols. The outputs of gates that are a function of
input variables only are F2, T1 and T2. The Boolean functions for these three outputs are
F2 = AB + AC + BC
T1=A+B+C
T2 = ABC
Next we consider outputs of gates that are a function of already defined symbols:
T3 = F2’T1
 F1 = T3 + T2
The output Boolean function F2 just expressed is already given as a function of the inputs only. To obtain
F1 as a function of A, B, and C, forms a series of substitutions as follows:
T3 = F2’T1
F1 = T3 + T2

3.4 Combinational design procedure

The design of combinational logic circuits starts from verbal outline of the problem and ends in a logic
circuit diagram, or a set of Boolean functions. The procedure involves following steps:
1. The problem is stated.
2. The number of available input variables and required output variable is determined.
3. The input and output variables are assigned symbols.
4. The truth table defines the required relationship between input and output.
5. The simplified Boolean function for each output is obtained.
6. The logic diagram is drawn.

3.5 Binary Adder

This circuit sums up two binary numbers A and B of n-bits using full-adders to add each bit-pair & carry
from previous bit position. The sum of A and B can be generated in two ways: either in a serial fashion
or in parallel.
 The serial addition method uses only one full-adder circuit and a storage device to hold the
generated output carry. The pair of bits in A and B are transferred serially, one at a time, through
the single full-adder to produce a string of output bits for the sum. The stored output carry from one
pair of bits is used as an input carry for the next pair of bits.
 The parallel method uses n full-adder circuits, and all bits of A and B are applied simultaneously. The
outputs carry from one full-adder is connected to the input carry of the full-adder one position to its
left. As soon as the carries are generated, the correct sum bits emerge from the sum outputs of all
full-adders.
(Half adder and full adder must be included)
Binary Parallel adder
A binary parallel adder is a digital circuit that produces the arithmetic sum of two binary numbers in
parallel. It consists of full-adders connected in a chain, with the output carry from each full-adder
connected to the input carry of the next full-adder in the chain.
Diagram below shows the interconnection of four full-adder (FA) circuits to provide a 4-bit binary
parallel adder. The augend bits of A and the addend bits of B are designated by subscript numbers from
right to left. The carries are connected in a chain through the full-adders. The S outputs generate the
required sum bits. The input carry to the adder is C0 and the output carry is C4.
When the 4-bit full-adder circuit is enclosed within an IC package, it has four terminals for the augend
bits, four terminals for the addend bits, four terminals for the sum bits, and two terminals for the input
and output carries.
 Fig: 4-bit parallel binary adder
An n-bit address requires n-full adder with each output carry connected to next higher order full adder.

E.g. Consider two binary adder A=1011 and B=0011

Subscript 3 2 1 0
Input carry 1 1 0 Ci
Augend 1 0 1 1 Ai
Addend 0 0 1 1 Bi
Sum 1 1 1 0 Si
Output carry 0 0 1 1 Ci+1

Result is obtained from c4, s3, s2, s1, s0 is =01110(decimal value=14).

3.6 Binary Subtractor

It is opposite of binary adder. It subtracts two binary numbers from each other. The outputs are
difference (D) and borrow (B).
The subtraction of binary numbers can be obtained by means o complements.

Consider A= 1111(15) and B= 0111(7), the resulting difference of two binary numbers is C4S3S2S1S0 and
so is =11000 (Decimal value=8).

3.7 Decimal Adder

It is computer or calculator that performs arithmetic operation directly in decimal number system. It
uses BCD adder internally which accept binary coded form of decimal numbers. Decimal adder requires
a minimum of nine inputs and five outputs, since 4 bits are required to code each decimal digit and the
circuit must have an input carry and output carry.
 See the table for designing BCD adder.
 It is obvious from table that a correction is needed when the binary sum has output carry K=1.
 The other six combinations from 1010 to 1111 that need a correction have a 1 in position Z8.
 To distinguish them from binary 1000 and 1001, which also have a=1 in position Z8, we specify
further that either Z4 or Z2 must have 1.
 The condition for a correction and output carry can be expressed by Boolean function.
C=K+Z8Z4+Z8Z2.

Fig: block diagram of BCD code.

3.8 Binary multiplier
A binary multiplier is a combinational logic circuit or digital device used for multiplying two binary
numbers. The two numbers are more specifically known as multiplicand and multiplier and the result is
known as a product. The multiplicand & multiplier can be of various bit size. It uses binary multiplier
circuit to multiply numbers.

3.9 Magnitude comparator

It compares two input variables and produce output signal based on condition.
1 bit comparator
A B G(A>B) L(A<B) E(A=B) Equations from the truth table
0 0 0 0 1 G=A.B
0 1 0 1 0 L=A.B
1 0 1 0 0 E= A.B+A.B
1 1 0 0 1
A B

2 bit magnitude comparator

A A1A0
B B1B0
Decoder
Decoder is a combinational circuit that converts binary information from n input lines to a maximum of
2n unique output lines.
 If the n-bit decoded information has unused or don't-care combinations, the decoder output will
have fewer than 2n outputs.

A1 A0 B1 B0 G(A>B) L(A<B) E(A=B)

0 0 0 0 0 0 1
0 0 0 1 0 1 0
0 0 1 0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
 n-to-m-line decoders have m <= 2n. 1 0 0 1
I0 O0 1 0 1 0
O1 1 0 1 1
I1 O2 1 1 0 0
O3 1 1 0 1
1 1 1 0
Truth table of 2 bit magnitude comparator
1 1 1 1
G=A1B1+(A1ʘb1).A0B0
L=A1B1+(A1ʘB1).A0B0
E=(A1B1).(A0ʘB0)

D0 D1 D2 D3 D4 D5 D6 D7 X Y Z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1

3.10 Encoders
It is a digital circuit that performs the inverse operation of a decoder. A decoder has 2n input line and n
output lines. The output lines generate the corresponding binary numbers.
Types of encoders are a) priority encoder b) decimal to BCD encoder c) Octal to binary
encoder d) Hexadecimal to binary encoder

The octal to binary encoder consists of eight inputs, one for each of eight digits, and three outputs that
generate the corresponding binary numbers. The encoder assumes that only one input line can be equal
to 1 any times, only eight of these combinations have one meaning. The other input combinations are
don’t care conditions.
 0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

D0 is not connected to any OR gate; the binary output must be zero in all case.

3.11 Multiplexers
A digital Multiplexer (MUX) is a combinational circuit that selects binary information from one of many
input lines and directs it to a single output line.
A multiplexer is also called a data selector, since it selects one of many inputs and steers the
binary information to the output line. It may be 2:1, 4:1, 8:1, 16:1 MUX types.
 The selection of a particular input line is controlled by a set of selection lines.
 Normally, there are 2n input lines and n selection lines whose bit combinations determine which
input is selected.

Inputs Select line Output (Y) Minterms

S1 S0
I0 0 0 I0 I0S1S0

I1 0 1 I1 I1S1S0

I2 1 0 I2 I2S1S0

I3 1 1 I3 I3S1S0

Expression:
Y= I0S1S0+I1S1S0+I2S1S0+I3S1S0
Fig: logical diagram for the expression given above.