Unit 6

MEMORY AND PROGRAMMABLE LOGIC

6.1 Introduction
A memory unit is a collection of storage cells together with associated circuits needed to transfer
information in and out of the device. Memory cells can be accessed for information transfer to or
from any desired random location and hence the name random access memory, abbreviated
RAM.
A memory unit stores binary information in groups of bits called words. A word in
memory is an entity of bits that move in and out of storage as a unit. A memory word is a group
of 1's and 0's and may represent a number, an instruction, one or more alphanumeric characters,
or any other binary-coded information.

6.1.1 Random access memory

The communication between a memory and its environment is

achieved through:
 n data input lines : provide information to be stored in
memory
 n data output lines: supply the information coming out of
memory.
 k address lines: specify particular word chosen among the
many available.
 two control inputs: specify the direction of transfer
desired.
 Each word in memory is assigned an identification
number, called an address, starting from 0 and continuing
with 1, 2, 3, up to 2k - I, where k is the number of address
lines.
 Computer memories may range from 1024 words,
requiring an address of 10 bits, to 232 words, requiring 32
address bits.

Write and Read Operations

The two operations that a random-access memory can perform are the write and read operations.
The write signal specifies a transfer-in operation and the read signal specifies a transfer-out
operation. On accepting one of these control signals, the internal circuits inside the memory
provide the desired function.

Write Operation: transferring a new word to be stored into memory

1. Transfer the binary address of the desired word to the address lines.
2. Transfer the data bits that must be stored in memory to the data input lines.
3. Activate the write input.

Read Operation: transferring a stored word out of memory

1. Transfer the binary address of the desired word to the address lines.
2. Activate the read input.
Commercial memory components available in IC chips sometimes provide the two control inputs
for reading and writing in a somewhat different configuration. The memory operations that result
from these control inputs are specified in Table below.

The memory enable (sometimes called the chip select) is used to enable the particular memory
chip in a multichip implementation of a large memory. When the memory enable is inactive,
memory chip is not selected and no operation is performed. When the memory enable input is
active, the read/write input determines the operation to be performed.

IC memory (Binary Cell- BC)

The internal construction of a random-access memory of m words with n bits per word consists
of m x n binary storage cells and associated decoding circuits for selecting individual words. The
binary storage cell is the basic building block of a memory unit.

Fig: memory cell.

6.2 Memory decoding

The storage part of the cell is modeled by an SR latch with associated gates to form a D latch.
Actually, the cell is an electronic circuit with four to six transistors. The select input enables the
cell for reading or writing and the read/write input determines the operation of the cell when it is
selected. A 1 in the read/write input provides the read operation by fanning a path from the latch
to the output terminal. A 0 in the read/write input provides the write operation by forming a path
from the input terminal to the latch.
The logical construction of a small RAM consists of four words of four bits each and has a total
of 16 binary cells. The small blocks labeled BC represent the binary cell with its three inputs and
one output. A memory with four words needs two address lines. The two address inputs go
through a 2X4 Decoder to select one of the four words. The decoder is enabled with the
memory-enable input.
When the memory enable is 0, all outputs of the decoder are 0 and none of the memory
words are selected. With the memory select at 1, one of the four words is selected, dictated by
the value in the two address lines.
Once a word has been selected, the read/write input determines the operation. During the
read operation the four bits of the selected word go through OR gates to the output terminals.
During the write operation, the data available in the input lines arc transferred into the
four binary cells of the selected word. The binary cells that are not selected are disabled and their
previous binary values remain unchanged.
When the memory select input that goes into the decoder is equal to 0 none of the words
are selected and the contents of all cells remain unchanged regardless of the value of the
read/write input.

 Coincident Decoding
A decoder with k inputs and 2k outputs requires 2k AND gates with k inputs per gate. The total
number of gates and the number of inputs per gate can be reduced by employing two decoders in
a two - dimensional selection scheme.
 Input decoders are used instead of one k-input decoder. One decoder performs the row
selection and the other the column selection in a two-dimensional matrix configuration.

For example, instead of using a single 10 x 1,024 decoder, we use two 5 x 32 decoders. With the
single decoder, we would need 1,024 AND gates with 10 inputs in each. The five most
significant bits of the address go to input X and the five least significant bits go to input Y. Each
word within the memory array is selected by the coincidence of one X line and one Y line. Thus
each word in memory is selected by the coincidence between 1 of 32 rows and 1 of 32 columns,
for a total of 1,024 words.

6.3 Error detection and correction

When digital information in binary form is transmitted from one circuit or system to another
circuit or system an error may occur. Any external noise introduced in to physical
communication medium changes bit values from0 to 1 or vice versa.
In complex digital system it is desired to have high data integrity, or at least a violation of
data integrity must be detectable. A simple process of improving data integrity is by adding
additional bit either in beginning or in the end is known as parity bit. Any group of bits contain
either an even or an odd number of 1’s, a parity bit is added to total number of 1’s in group be
always either even or odd.

Even parity generator adds 1 or 0 to maintain number of 1’s in odd number. Similarly odd parity
generator also adds 1 or 0 to maintain number of 1 in even number.
Even parity Odd parity
P BCD P BCD
0 0000 1 0000
1 0001 0 0001
1 0010 0 0010
 0 0011
1 0100
0 0101
0 0110
1 0111
1 1000
0 1001
1 0011
0 0100
1 0101
1 0110
0 0111
0 1000
1 1001

Parity checker uses even parity checker circuit and odd parity checker circuit to check the
received bits. C=0 when received bits are correct and C=1 when incorrect and vice-versa for odd
parity checker. It then sends signal to transmitter if error detected so that resending of data is
done. The parity check circuitry only detects single bit error in a group of bits. Logic diagrams
for parity generator and Parity checker are shown below:

6.4 Read only Memory

A read-only memory (ROM) is a device that includes both the decoder and the OR gates within a single
IC package. The connections between the outputs of the decoder and the inputs of the OR gates can be
specified for each particular configuration. The ROM is used to implement complex combinational
circuits within one IC package or as permanent storage for binary information.
A ROM is essentially a memory (or storage) device in which permanent binary information is stored. The
binary information must be specified by the designer and is then embedded in the unit to form the
required interconnection pattern. ROMs come with special internal electronic fuses that can be
"programmed" for a specific configuration. Once the pattern is established, it stays within the unit even
when power is turned off and on again.
 It consists of n input lines and m output lines. Each bit combination
of the input variables is called an address. Each bit combination that
comes out of the output lines is called a word. The number of bits
per word is equal to the number of output lines, m. An address is
essentially a binary number that denotes one of the minterm of n
variables. The number of distinct addresses possible with n input
variables is 2n.

The five input variables are decoded

into 32 lines. Each output of the
decoder represents one of the
minterms of a function of five
variables. Each one of the 32
addresses selects one and only one
output from the decoder. The address
is a 5-bit number applied to the inputs,
and the selected minterm out of the
decoder is the one marked with the
equivalent decimal number. The 32
outputs of the decoder are connected
through fuses to each OR gate. Only
four of these fuses are shown in the
diagram, but actually each OR gate
has 32 inputs and each input goes
through a fuse that can be blown as
desired.

Fig: logic construction of a 32 x 4 ROM.

6.5 Programmable Array Logic
It is a programmable logic device with a fixed OR array and a programmable AND array. It can
be programmed one time and is commonly used PLD. PAL structure allows SOP logic
expression with a defined number of variables to be implemented. With a PROM programmer,
we can burn in the desired fundamental products, which are ORed by the fixed output
connections.
 When designing with a PAL, Boolean function must be simplified to fit into each section
 Unlike PLA, a product term cannot be shared among two or more OR gates. Therefore, each
function cannot be simplified by itself without regard to common product terms.
 The output terminals are sometimes driven by three state buffers or inverters.
Example:
X(A,B,C)=∑(2,3,5,7) A’B+AC
Y(A,B,C)= ∑(0,1,5) A’B’+B’C
Z(A,B,C)= ∑(0,2,3,5) A’B+A’C+AB’C
Fig: Fuse map for PAL as specified in expression above.

6.6 Programmable logic array (PLA)

It is a logic device that can be programmed to implement various kinds of combinational logic
circuits. The input AND-gate array used in PROM is fixed and cannot be altered, while the
output OR gate is fusible linked, and thus can be programmed. It is more versatile than PROM or
PAL since AND and OR gates which are linked together to give output or further combined with
more gates or logic circuits.
Simply PLA is LSI component that can be used economically as an alternative to ROM
where don’t care condition is excessive.

A PLA having 3 input variables (ABC) and 3 output variables (XYZ) are illustrated below.