Course : .

, Microelectronics, 2023
Email : mohit.0211996@gmail.com
Mobile: 9413375766

PG Microelectronics BITS Pilani, Pilani Campus BITS Pilani 8.31 2023

Electrical & Electronics Jai Narain Vyas

UG MBM Engineering College,Jodhpur 72.07 % 2018
Engineering University,Jodhpur

CLASS Emmanuel Senior Secondary School ,

SCIENCE CBSE 80.2 % 2013
XII Tonk

Emmanuel Senior Secondary 9.6

CLASS X CBSE 2011
School,Tonk CGPA

VLSI Design, VLSI Architecture, CAD for IC Design, Reconfigurable Computing, IC Fabrication Technology

Cadence Virtuoso, Verilog, Vivado - Xilinx, Soc Encounter, LTSpice, Python

Designed different Architectures of a High-Resolution Time to Digital Converter circuit in cadence virtuoso using 180nm technology.
Time to Digital Converter circuit various parameters like Resolution, Dead-Time, Delay comparison done under PVT variations.
Basic Building blocks utilized in circuit simulation are D Flip-Flop, Buffers & Thermometer to binary code converter.
I
Implemented a basic pipelined RISC V ISA based RV32I processor in Verilog HDL that supports integer operations for R-type, I-type,
B- type, S-type, U-type, J-type instructions.
Data and control hazards were detected and avoided using the stall method.

Implemented 16-bit pipelined cordic processor which is used for calculation of sine & cosine value of given angle.
Synthesis was done using RTL Compiler at 90nm technology.
Backend steps of design flow were carried out using SOC encounter.
I
Implemented a Minimum CISC instruction set architecture also called as MIN ISA in Verilog HDL.
MIN ISA performs Arithmetic & Logic instructions, Stack Operation instructions ,Conditional Branch instructions, Load & Store instructions

Designed a hierarchical Memory system with direct mapped cache with write back with write allocate in Verilog .
Verified the same for matrix multiplication & observed the different parameters of memory system in continuous allocation & random
allocation of data in matrix.

Currently working as Verification intern in DRAM & Emerging Group at Micron ,Hyderabad.
W orking on Dynamic Timing Analysis of LPDDR5.

W orked as a Junior Manager in E&A Department of Blast Furnace-1.

Worked on PLC upgradation of Gas Cleaning Plant in Blast Furnace-1.
Used predictive maintenance techniques to improve the MTBF of plant & achieved target MTBF.
Planning & Procurement of Spares done for the Blast Furnace-1.

Designed a project capable of measuring Environment parameter like Temperature, Humidity using Arduino.

This is awarded for the contribution in digital transformation journey of JSW Steel.
Under this project all equipment's related data like PM,MTBF,MTTR updated on the Data Dash Board, which ease the different teams to take
corrective action using that data.