EE 781 IC Design for Sensor Systems

Course Project
Aayush Shrivastava | 19D070002
Sanket J Hanamashetti | 190070057

OTA
We attempted to improve the OTA by redesigning it for a stricter set of specifications. The
AC specifications were met but the transient response was poor. Hence, we decided to use the
previous OTA design (Assignment 3).

Matlab Simulations
We modeled Fig. 6 (shown in Fig.1√ here) from (Jiang, H., Nihtianov, S. and Makinwa, K.A.,
2018. An Energy-Efficient 3.7-nV/ Hz Bridge Readout IC With a Stable Bridge Offset Com-
pensation Scheme. IEEE Journal of Solid-State Circuits, 54(3), pp.856-864.), except the CDAC
and ripple reduction loop (RRL) on Simulink. It should be noted that implementing the PFL
on Simulink would amount to nothing as the simulation doesn’t have currents flowing through
the connections. The Simulink Model is shown in Fig. 2

Figure 1: CCIA

A sine wave of 100 Hz and 4 mVpp amplitude was used as an input. An offset of 5 mV was
added at the input of the OTA. As seen in Fig.3, we get a sine wave of 2 Vpp as the output
without any offset. Its frequency content is shown in Fig.4
Course Project Aayush Shrivastava, 19D070002 & Sanket J Hanamashetti, 190070057

Figure 2: Simulink Model

Figure 3: ADC (10-bit) output

Circuit Implementation
Due to GLADE frequently crashing, interchanging the source-drain terminals, and messing up
the body connections, we decided to work with netlists and use Spice Opus for simulations. A
circuit similar to Fig.1 was constructed, except the RRL, ADC and CDACs.

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Course Project Aayush Shrivastava, 19D070002 & Sanket J Hanamashetti, 190070057

Figure 4: ADC (10-bit) frequency content

Spice Simulation Results

OTA Simulations:
DC Simulations
The output common mode voltage of the OTA design is shown below-

V outCM (ttt) = 2.5085 V V outCM (sss) = 2.8803 V V outCM (fff) = 2.209 V

So we incoporated trimming across the corners to get the desired output common mode voltage,
after trimming the results are-

V outCM (ttt) = 2.5085 V V outCM (sss) = 2.509 V V outCM (fff) = 2.505 V

AC Simulations
The bode plots of the ac simulations of the OTA is shown in Fig. 5. We get a DC gain of 93dB,
unity gain frequency of 250KHz and a phase margin of 64 degrees.

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Course Project Aayush Shrivastava, 19D070002 & Sanket J Hanamashetti, 190070057

Figure 5: Bode Plot for OTA ac simulation

CMRR Simulation
The circuit used for simulating CMRR is shown in Fig. 6. The 10mV DC sources are for
modelling the mismatches in threshold voltage of the input transistors. We get a CMRR of
156dB at DC.

Figure 6: CMRR Measurement Setup

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Course Project Aayush Shrivastava, 19D070002 & Sanket J Hanamashetti, 190070057

Noise Simulation
We tried to simulate the noise using the netlist shared. However, we were not able to generate
a plot with that. We used a netlist that spiceopus provides for simulating noise of an Op-Amp,
using that we get the following spectrum plot shown in Fig. 7.

Figure 7: Input Noise spectrum

CCIA Simulations
The Vout and IinP plots (without PFL) are shown in Fig.?? and in Fig.?? (with PFL).

Figure 8: Output Voltage(without PFL)

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Course Project Aayush Shrivastava, 19D070002 & Sanket J Hanamashetti, 190070057

Figure 9: Positive Input Current (without PFL)

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Course Project Aayush Shrivastava, 19D070002 & Sanket J Hanamashetti, 190070057

Figure 10: Output Voltage(with PFL)

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Course Project Aayush Shrivastava, 19D070002 & Sanket J Hanamashetti, 190070057

Figure 11: Positive Input Current (with PFL)

An offset of 1 mV was introduced at the input of gm1. The output for this case is shown in
Fig.12 from which it can be seen that it gets eliminated.

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Course Project Aayush Shrivastava, 19D070002 & Sanket J Hanamashetti, 190070057

Figure 12: Vout in presence of offset