Topic 3: ARM

Part 5: Instruction Format

 Format of instructions

 Recall we said earlier that every

instruction in ARM is just 32-bits long
 Our goal here is to explain how this is
achieved for ADD and other instructions

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 The 32-bit format

 An instruction like
ADD r5, r1, r2
is represented as the string of binary
numbers
1110 00 0 0100 0 0001 0101 000000000010

This is called as the instruction format

Specific meanings are assigned to each
3 “segment”. Each segment is called a field
 Dissecting the 32-bit string

 1110 00 0 0100 0 0001 0101 000000000010

↕ ↕ ↕ ↕ ↕ ↕ ↕ ↕
14 0 0 4 0 1 5 2
Here the fourth field containing 4 (or 0100) tells the
ARM processor that this instruction performs
addition. Sixth field gives the no. of the register
that is the first source operand (1 = r1). The last
field gives the other source operand for addition
(2 = r2)
The seventh field contains the number of the
4
register that is to receive the sum (5 = r5)
What about the remaining fields ?

 We have eight fields altogether – only four

of these were used in the addition
instruction
 The remaining fields are for conditional
branch instructions, specifying whether
we have an operand which is a constant
and so on
 What is the general form ?
 General Format of an Instruction

Cond F I Opcode S Rn Rd Operand2

4 bits 2 bits 1 bit 4 bits 1 bit 4 bits 4 bits 12 bits

– Opcode : Basic operation of the instruction

– Rd: The destination register operand
– Rn: The first register source operand
– Operand2: The second source operand
– I:Immediate. If I is 0, the second source operand is
a register, else the second source is a 12-bit
immediate.
– S: Set Condition Code (related to conditional
branch instructions)
– Cond: Condition; F: Instruction Format.
Another Data Processing Example

Cond F I Opcode S Rn Rd Operand2

4 bits 2 bits 1 bit 4 bits 1 bit 4 bits 4 bits 12 bits

ADD r3,r3,#4 ; r3 = r3 + 4

14 0 1 4 0 3 3 4
4 bits 2 bits 1 bit 4 bits 1 bit 4 bits 4 bits 12 bits

Will see that 14 in the first field will remain as such for a data transfer
instruction like LDR too

1110 00 1 0100 0 0011 0011 0000000001002

Explanation for r3 = r3 + 4

 Constant 4 is placed in the Operand2 field

 The I field is set to 1 since we have an
immediate operand
 The Opcode is 4 as before since the
operation remains the same (addition)
 The Rn and Rd fields give numbers of the
register that is the first source operand (3)
and the register to receive the sum (also
3)
 Some points to note

 We have only 16 registers to handle so 4

bits are adequate
 12 bits for operand2 and implications:
Values you can include with # … (in the
immediate mode) for ADD cannot be
arbitrarily large
 This extends also to the MOV command
(try MOV r0, #4097)
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 Are we going to read and write
long 32-bit strings ?

 No, we will use the hexadecimal

representation
 Hexadecimal allows for compact
representation
 Example: eca8 6420
1110 1100 1010 1000 0110 0100 0010 0000

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 What about format for other types
of instructions ?

 Is the format the same for data transfer

instructions ?

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 ARM Data Transfer Instruction Format

Cond F Opcode Rn Rd Offset12

4 bits 2 bits 6 bits 4 bits 4 bits 12 bits

Let base address of array named Buffer be in r3

LDR r5, [r3, #8] ; reg r5 gets Buffer[2]

14 1 24 3 5 8
4 bits 2 bits 6 bits 4 bits 4 bits 12 bits

WILL SEE AN EXAMPLE PROGRAM NEXT …

 Example

AREA Reset, CODE, READONLY

ENTRY
Main
ADR R3 , Buffer
LDR R5, [R3, #08]
SWI &11
Buffer DCD &12A2E640 ,&F2100123, &001019BF ,&40023F51

END
WHAT WILL R5
HAVE ?
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 R5 will have 001019BF

 Note a few other points here: The ARM assembly

language declaration
Buffer DCD 12A2E640 ,&F2100123,
&001019BF ,&40023F51
allocates four 32-bit words in memory and
defines the symbol Buffer to have as its value
the starting address of the first word.
Since each word is 4 bytes in length, the second
element Buffer[1] is at address Buffer+4 while
the third at Buffer +8 and the fourth at Buffer+12
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 More on the program

 To reference any element in an array, we need

the starting address (base address) and the
index of the desired element
 In ARM, the base address of an array must be in
a register and one way to make this happen is
using the ADR instruction
 The instruction

ADR R3 , Buffer
places the address of Buffer in register R3

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 How are the numbers for LDR obtained ?

 It is clear that Rn field has 3 for the base

register, Offset 12 field has 08 as the
offset to add to the base register and Rd
field has 5 for the destination register
 Note that the F field now has 1 meaning
that this is data transfer instruction
format
 Opcode field has 24 showing that this
instruction is load word
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 Format for Control Flow Instructions

 Since ARM designers chose to keep all

instructions the same length, different
kinds of instructions have different
formats
 We already saw this in data transfer (its
format is different from data processing
instructions)
 For control flow, the format is different
again !
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 Branch Instruction format

Condition 101 L address

4 bits 24 bits
 Encoding of options for Condition field

L stands for link bit; it is 0 for branch (B) and 1 for NV: stands for
branch with link (BL; used for subroutine call) Never (do not use)
 Example 1

AREA Reset, CODE, READONLY

ENTRY
Main
MOV R0, #5
MOV R1, #4 What does R2
ADD R2, R0, R1, LSL #2
have now ?
stop b stop
END

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 R2 will be 0x00000015

 Why ?

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 Example 2

AREA Reset, CODE, READONLY

ENTRY
Main
ADR R3 , Buffer
LDR R5, [R3]
SWI &11
Buffer DCD &12A2E640 ,&F2100123, &001019BF ,&40023F51

END
What will R5 have ?
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 Solution

 R5 will get 0x12A2E640

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 Exercise

 Verify the solution via Keil microvision5

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