Link Budget Parametrs

LiU-ITN-TEK-A--19/051--SE
Construction of RF-link budget

template for transceiver
modelling
David Frykskog
Hjalmar Jonsson
2019-10-07
Department of Science and Technology Institutionen för teknik och naturvetenskap

Linköping University Linköpings universitet
SE- 6 0 1 7 4 No r r köping , Sw ed en 6 0 1 7 4 No r r köping
LiU-ITN-TEK-A--19/051--SE
Construction of RF-link budget

template for transceiver
modelling
Examensarbete utfört i Elektroteknik
vid Tekniska högskolan vid
Linköpings universitet
David Frykskog
Hjalmar Jonsson
Handledare Anna Lombardi

Examinator Adriana Serban
Norrköping 2019-10-07
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Abstract
This report presents the development of a simulation platform for radio receiver sys-
tem design. The simulation platform is implemented in the AWR VSS environment. The
report goes through the underlying theory of radio receivers and the methodology of im-
plementing the receiver and receiver impairments in the simulation platform. The purpose
of the project is to evaluate the AWR VSS environment for developing a simulation plat-
form for RF budget analysis and to take advantage of built in functionality as well as its
graphical interface. The project results in two simulation platform templates for receivers
that uses different simulation types. It is demonstrated that these simulation platforms
can have much of the specified requirements implemented. Some of the listed functional-
ity requirements turns out difficult or impractical to implement however. It is concluded
that VSS can be used for developing simulation platforms with the specified requirements.
Some of the functionality that is not natively supported by the software is implemented
using calculations post simulation and VBA scripting. These methods are proposed as a
solution for adding functions to the template in future work.
Acknowledgments
This work would not be possible if not for the great support and guidance of our supervisors
at Ericsson. With the help and expertise of our main supervisor, Peter Pääkkönen, our work
was made substantially easier and the quality of the results would not be the same without
him. We would also give out thanks to the head of our team at the analog design depart-
ment, Jörgen Johansson, for pitching the idea of the master thesis and for helping us getting
started with our work. We have been fortunate to have great support from many people at
Ericsson, who has lent their time and knowledge to make sure we got all the help we needed
to complete the work.
We have also had great support from our supervisors at Linköping University who has
managed the administrative tasks and helped the work flow smoothly as well as made sure
the project did not get out of hand.
Finally we would like to extend our gratitude to our families who has supported our
efforts in all the ways possible. Thanks to their unrelenting support, we have managed to
finish our electrical engineering education and this master thesis project.
ii
Contents
Abstract i
Acknowledgments ii
Contents iii
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Aim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Research questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Delimitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.5 State of the art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Theory 5
2.1 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Non linearity in RF devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Selectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Degradation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 Analog circuits in RF receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6 Process variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.7 Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.8 I/Q Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.9 Receiver architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.10 Digital Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Development 20
3.1 NI AWR Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2 Receiver impairments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 Receiver model implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4 Simulation platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4 Results 34
4.1 Simulation platform results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.2 Budget simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.3 Time domain simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5 Discussion 49
5.1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.2 Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.3 Improvements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6 Conclusion 53
iii
Bibliography 55
iv
Nomenclature
In order of appearance
RF Radio Frequency FIR Finite Impulse Response

RX Receiver/Receiving system IIR Infinite Impulse Response
NI National Instruments EDA Electronic Design Automation
AWR Applied Wave Research EM Electromagnetic
VSS Visual System Simulations API Application Programming Interface
LNA Low Noise Amplifier ADS Advanced Design Systems
PA Power Amplifier BER Bit Error Rate
IP3 3:rd order Interception Point SNR Signal to Noise Ration
NF Noise Figure PID Product, Integrator, Derivative
P1dB Compression Point RMS Root Mean Square
HDx x:th Harmonic Distortion DUT Device Under Test
LO Local Oscillator
PLL Phase Locked Loop
ADC Analog to Digital Converter
IM[N] Nth Intermodulation product
AGC Automatic Gain Control
RFFE Radio Frequency Front End
DSP Digital Signal Processing
VGA Variable Gain Amplifier
PGA Programmable Gain Amplifier
LPF Low Pass Filter
BPF Band Pass Filter
BSF Band Stop Filter
HPF High Pass Filter
IL Insertion Loss
DC Zero Hz Frequency Component
IC Integrated Circuit
AM Amplitude Modulation
FM Frequency Modulation
PM Phase Modulation
ASK Amplitude Shift Keying
FSK Frequency Shift Keying
PSK Phase Shift Keying
QPSK Quadrature Phase Shift Keying
QAM Quadrature Amplitude Modulation
IF Intermediate Frequency
SDR Software Defined Radio
DFT Discrete Fourier Transform
1 Introduction
Ericsson is a company which mainly focuses on the development of Radio Infrastructure for
cellular, wireless connectivity. Their mobile solutions are installed all over the world in all
environments and conditions. This requires high tolerances, high precision engineering and
therefor high precision tools in the design phase. The push towards a more mobile society
with 5G connectivity on the horizon calls for these tools to be more complex, precise and
comprehensive than ever before.
1.1 Motivation
Current simulation platforms and tools used for transceiver link budget simulations in RF
design at Ericsson are often Matlab or Microsoft Excel based. These custom tools are ver-
satile and detailed, but complex and thus they require knowledge and competence in both
these tools, and in specific transceiver systems. In the hands of an expert with knowledge in
transceiver systems and the tools themselves, the tools are efficient. However for a person in
the field with less experience in either area, the threshold to start using these tools is high.
The companies developing software for electronic design are with every edition of re-
leases including more advanced solutions in their system simulation tools. This, along with
a relatively low entry bar and a visual interface, makes for an intuitive and efficient work
interface for system simulation. In addition, the system simulation tools can already include
built in functionality similar to that of the tools in Matlab and Microsoft Excel. One major
drawback of these software tools is that they might not include options and possibilities of
customization for specific needs, such as specific impairments and functionalities. However,
with the release of simulation tools such as Applied Wave Research (AWR) system Simu-
lation tool Visual System Simulations (VSS), these customization options have however been
improved upon.
For engineers, ease of use, versatility and improved customization makes VSS competitive
towards existing link budget simulation tools made in Matlab and Microsoft Excel.
1
1.2. Aim
1.2 Aim
The project aims to implement an RF link budget model in AWR VSS environment. Specifi-
cally the RX and TX chains of a homodyne transceiver should be modelled for budget analysis
purposes. The work includes analog and digital transceiver from antenna to the digital inter-
face, but not any further. In comparison to present link budget tools in Matlab and Microsoft
Excel, the tool should include frequency spectrum at each component (block) in VSS and RF
budget parameters such as gain, noise figure and compression point.
In addition, the work aims to clarify the drawbacks of the present tools in Matlab and Mi-
crosoft Excel regarding ease of use. The link budget tool in VSS should address these issues.
As mentioned in Section 1.1, the tool should be targeted towards users, i.e., RF engineers not
working with the present, more complex tools on a daily basis.
Functionality and parameters

The link budget tool should include the following functionality with associated parameters:
Analog blocks
Analog blocks include analog filters, amplifiers (LNA, PA), attenuators (including cable
losses), mixers and passive components. They have a lot of different properties and parame-
ters to be taken into account when making accurate models.
• Gain
• Noise Figure
• IP3
• P1dB
• HDx
IQ modulator and demodulator

• Spurious response
• IQ-imbalance
• LO leakage
• PLL including reference clock
• DC offset
• Reciprocal mixing
• LO phase noise
ADC
• Sampling rate
• Aliasing
• Jitter
2
1.3. Research questions
Filters, channel filters

• Rejection
• Decimation
Blockers and interfering signals

• Blocking
• IM blocking
Other functionality
• Automatic Gain Control (AGC)
• Gain calibration
Optional functionality
If the scope of the project allows for further modelling, the following proposals are to be
investigated:
Statistical simulation
• Yield analysis
Digital blocks
• Channel filtering
• Ripple estimation and handling
1.3 Research questions

The simulation platform will be implemented in the VSS environment in AWR. When con-
verting functionality and adding new ones to a new platform, the natural question to ask is
what functionality can be implemented and what compromises have to be made in order to
have these functions work in the new environment. The research questions that this project
aims to answer are:
• What functionalities and parameters can be implemented in VSS using built in func-
tionality and what have to be implemented using ad hoc means?
• What compromises needs to be made when implementing the different functionalities?
1.4 Delimitation
The scope of the project is limited to existing radio links. It aims to include functions already
in use in excel-based budget tools with addition of VSS functionality such as time-domain.
Contrasting the existing Excel-based link budget, the VSS tool will remain on system-level
complexity.
The tool aims to be practical in the sense that user experience should be prioritized over
complexity and customization. In a scientific sense, this feature is hard to define and to mea-
sure. An example of a so called "practical" aspect of the tool could be simulation time. This
limits the project to certain design choices based on this philosophy. If a model is considered
accurate but slow, it might be discarded.
3
1.5. State of the art
While VSS includes functionality to implement many of the listed requirements of the
tool, it might not include others in the sense that they are either considered "impractical" or
do not exist. An example of an impracticality is long simulation times. The limitations will
be considered at the end of the project for evaluating VSS as a software for RF system level
simulations and for implementing budget-like tools.
1.5 State of the art

Developing radio receivers and transmitters while optimizing all relevant circuit and system
parameters is often pushing the limits of what is possible. High frequency transceivers are
some of the most complex systems widley in use in the world today and require extreme
precision in all steps of development.
Since the complexity and performance of radio systems increase, it is getting harder for
legacy tools to meet the demands of engineers. Adding functionalities continuously over time
eventually makes these tools slow and difficult to get to learn and to use. This pushes compa-
nies to innovate and find alternative tools that have the ability to handle complex workloads
in an easy to understand manner.
4
2 Theory
This chapter covers the theoretical background considered related to the functionality of the
link budget tool in VSS. What we mean by functionality is the set of parameters listed in
Section 1.2.
We will cover the baseline components of an RF front end (RFFE) receiver. These include
amplifiers, filters and mixers. Other components and functionality covered in this section
include Analog-Digital-Converter (ADC), Automatic Gain Control (AGC) and channel filter-
ing. There are many other aspects of RF system modelling such as antenna characterization,
DSP and the transmitting part of the system. But for the sake of narrowing the scope of the
project, we will focus mainly on the analog front end, and theory related to the link budget
tool.
We will also cover non-ideal aspects of RF system design. When designing and evaluating
RF system performance and characteristics, we must take into consideration these aspects.
These include noise and distortion, process variations and nonlinear behavior of RF compo-
nents. It is worth noting that all non-ideal phenomena mentioned above are not necessarily
independent. This will be clarified.
2.1 Noise
Noise can be described as a random process which is present in RF systems. Noise present in
RF systems is introduced by the antenna from the external environment to the system, and is
also generated internally by active components within the system itself.
One type of noise important to radio systems is thermal noise. It is caused by random
motion of charges and is generated by anything lossy in radio systems. It can also be gen-
erated outside the system e.g., in the atmosphere from thermally excited charges. Thermal
noise can be characterized as frequency independent, noise, i.e., white Noise. When measuring
noise power in the frequency domain, we can view the thermal noise as a constant power
spectrum. across all measured frequencies due to this characteristic [11].
When measuring a signal in the time domain, we will observe the noise as a random
process on top of the signal. If the noise power in the system is stronger than the power of
the desired signal, we will not be able to observe the desired signal. Therefore, it is necessary
to minimize the amount of noise generated by any RF system.
5
2.2. Non linearity in RF devices
A simple example of a noise source is a resistor of value R in an environment with tem-

perature T. Charges in the resistor are thermally excited and so we will be able to measure a
voltage across it. Since thermal noise is a type of white noise, the mean voltage is 0. However,
the root mean square value (rms) is non-zero and is given by (2.1).
?
Vn = 4kTBR (2.1)
where B is the system bandwidth and k is the Boltzmann constant. In a system where the
resistor acts a noise source with impedance R, the available noise power Pn delivered to a
matched load can be derived with elementary circuit theory as in 2.2.
2
V2

Vn 1
Pn = = n = kTB (2.2)
2 R 4R
It can be seen that both the temperature and the system bandwidth play a crucial role
when characterizing system noise power.
Noise figure
In RF systems, the increase of noise can be characterized by noise figure, which is the mea-
surement of degradation in signal-to-noise ratio (SNR) from a point to another in a system (for
example input and output). Noise figure is defined as [11]
S1 /N1
F= (2.3)
S2 /N2
where terms with notation 1 refers to port 1 and notation 2 to port 2. Single components often
have noise figure specified in their data sheets in the units of decibels as F (dB) = 10log10 ( F ).
As systems consists of many components, independently produced and tested, in order
to characterize a system by its total noise figure, Friis formula for noise can be used: [11]
F2 ´ 1 F ´1
F = F1 + + 3 + ..., (2.4)
G1 G1 G2
In order to minimize noise figure, we can derive from (2.4) that components with a large
gain (G) such as amplifiers should be put close to the input.
2.2 Non linearity in RF devices

In many cases, system modelling can be approximately made assuming linear dependency
between input and output signals. However, this linear assumption is never true and espe-
cially not for RF devices and networks. This section covers the basics of nonlinear systems.
Given a nonlinear network, the output signal can be expressed as
so = a0 + a1 si + a2 s2i + a3 s3i ..., (2.5)

where si is the input signal and so the output signal. Whereas for a linear network, the
output can simply be expressed as so = a0 + a1 si . A system with an input signal given by a
tone si = V0 cos(ω0 t) results in an output
so = a0 + a1 V0 cos(ω0 t) + a2 V02 cos2 (ω0 t) + a3 V03 cos3 (ω0 t) + ...,
1 3 1 1
= ( a0 + a2 V02 ) + ( a1 V0 + a3 V03 ) cos(ω0 t) + a2 V02 cos(2ω0 t) + a3 V03 cos(3ω0 t) + ..., (2.6)
2 4 2 4
From (2.6), it can be seen that harmonic components are present at the output of a nonlin-
ear system, [11].
6
2.2. Non linearity in RF devices
As signals in RF systems are rarely a single tone, it might be of interest to investigate the
case when the input signal consists of many tones. Lets say si = V0 (cos(ω1 t) + cos(ω2 t)),
then the output becomes
so = a0 + a1 V0 (cos(ω1 t) + cos(ω2 t)) + a2 V02 (cos(ω1 t) + cos(ω2 t))2 + a3 V03 (cos(ω1 t) + cos(ω2 t))3 + ...,
(2.7)
The output spectrum will consist of harmonics given by
mω1 + nω2 (2.8)

where m and n are arbitrary integers. These combinations are what is called intermodula-
tion products [11].
Gain compression
Looking back at the output signal of an nonlinear system (2.6), we can derive the voltage gain
of the fundamental frequency as:
a1 V0 + 43 a3 V03 3
Gω0 = (so /si )ω0 = = a1 + a3 V02 (2.9)
V0 4
Since a3 is negative for amplifiers, it can be seen that the voltage gain decreases as the
amplitude of the input signal V0 increases. The gain becomes saturated as signal strength
increases at the fundamental frequency, hence the name gain compression. For nonlinear RF
components, the gain compression is quantified as P1 , usually in decibels. P1 is the point
where the gain has decreased 1 decibel with respect to the linear case, either referred to the
input or the output [11]. Fig. 2.1 shows a typical nonlinear amplifier with output compression
point at 15 dB.
Figure 2.1: Input versus output signal strength of a typical nonlinear amplifier simulated in
VSS
7
2.3. Selectivity
Third-Order Interception Point

When the input signal consists of two tones, the output, is given by (2.7). It can be seen that
third order intermodulation products are increasing with the cube of the input voltage. As
the signal voltage is increased, the output power of the fundamental tone and the third order
tones approach one another. The hypothetical point where these two lines cross is called P3
and is either referred to the input or the output. Solving the system of equations for the two
lines, we find
2a31
P3 = (2.10)
3a3
where P3 is referred to the output. This characteristic is of interest in RF systems since
these intermodulation products can cause distortion in the received signal This can in turn
affect performance.
Fig. 2.2, shows the signal strength of fundamental tone (in blue) and the signal strength
of the third order intermodulation tone (in pink). The intersection of the two dotted lines is
referred to as P3 . In contrast to the dotted lines, the solid lines take into account the nonlinear
contribution in both the fundamental tone (in blue) and the third order intermodulation tone
(in pink).
Figure 2.2: VSS simulations of input versus output signal strength of a typical nonlinear
amplifier. Fundamental tone (in blue) and third order intermodulation tone (in pink).
2.3 Selectivity
An RF receiver must provide certain requirements for desired performance. RF receivers
have to be able to receive a signal in a specific channel within the band of operation, while
rejecting signals and distortions from adjacent channels. This specific requirement is referred
to as selectivity [11].
8
2.4. Degradation
2.4 Degradation
Degradation is a measurement of how well a radio channel performs with interference. The
degradation can be calculated using (2.11).
Degradation[dB] = [ POUT+ I NT ´ G+ I NT ] ´ [ POUT ´ G ] (2.11)
2.5 Analog circuits in RF receivers

Along the receiver chain, several types of amplifiers are used. They have all different pur-
poses besides the main purpose of amplifying the signal.
Low Noise Amplifier

According to the Friis formula (2.4) it is important for the total noise figure of the system, to
have high gain components close to the antenna of an RX lineup. The earlier the component
lies in this chain, the more its noise figure contributes to the over all noise figure. The solution
is the low noise amplifier or "LNA".
When designing an amplifier a, trade-off is made between the amplifiers gain and its noise
figure. The LNA is an amplifier that is optimized for low noise instead of maximum gain, in
order to keep the total noise figure of the lineup low.
For any two port amplifier, the noise figure can be described as in (2.12) [11].
RN
F = Fmin + |Y ´ Yopt |2 (2.12)
GS S
Where YS : Source admittance, Yopt : source admittance that results in the lowest possi-
ble noise figure, Fmin : Minimum noise Figure of transistor, R N : Equivalent noise figure of
transistor and GS : The real part of the source admittance [11].
Variable Gain Amplifier and Programmable Gain Amplifier

Variable Gain Amplifiers (VGA) and Programmable Gain Amplifiers (PGA) are as the names
suggest, configurable amplifiers. Their purposes vary depending on design and application,
but in receivers they can act as gain control and gain calibration. Gain control can be used
to compensate for nonlinear behavior at high received power in order to improve dynamic
range. Gain calibration can be used to compensate for process variations and temperature
variations in components. These are examples of how VGA/PGA technologies were used in
this project.
Filters
Analog passive filters are used to attenuate undesired frequency content of an incoming sig-
nal, while retaining desired frequencies. There are four basic types of passive filters; Low-
pass filters (LPF), bandpass filters (BPF), bandstop filters (BSF) and high-pass filters (HPF).
In RF applications, these types of filters can be implemented using a variety of techniques.
These include lumped component filters, microstrip filters and cavity resonators.
Lumped component filters are implemented with lumped elements such as capacitors,
inductors and resistors. Microstrip filters are implemented using microstrip transmission
lines utilizing stubs and coupled lines as filtering elements [10].
Cavity filters are filters constructed from a cavity resonator i.e. a wave guide with its in-
ternal dimensions tuned to create a standing wave for certain frequencies while frequencies
outside the passband get attenuated by not being able to propagate through the cavity. Be-
cause the filter is a cavity, it attenuates unwanted signals hard, which is why it is commonly
9
2.5. Analog circuits in RF receivers
used as the bandpass filter at the antenna of RF systems to prevent interferance from reaching
the components of the receiver. [17].
There are some parameters of importance when analyzing filters. Insertion loss (IL) de-
scribes how much power that is lost between input and output. Ripple describes the flatness
of the filter frequency response in the passband. Rejection describes how the filter attenuates
frequencies in the stopband [10].
Mixers
The RF mixer is an essential component in any RF system. It is a two-input, one-output
component that combines the two input signals by adding together their two frequency com-
ponents as: ω1 + ω2 or ω1 ´ ω2 . This can be done to either up- or down-convert a signal
depending weather the mixer is used in a transmitter or receiver. Since the mixer is a non-
linear device, its characteristics can be described as a series of Taylor polynomials according
to (2.7).
Up-conversion is used in the transmission link: Intermediate frequency (IF) signal is
mixed with a signal from a Local Oscillator (LO) that acts as a carrier for the information
contained in the IF signal. The mixed signal is then sent to the RF port. Given the two input
signals
VLO (t) = cos(ω LO t) (2.13)
VIF (t) = cos(ω IF t) (2.14)

The resulting RF waveform from Up-conversion can be approximated as in (2.15).
K
VRF (t) = [cos(ω LO t ´ ω IF t) + cos(ω LO t + ω IF t)] (2.15)
2
where K is the voltage conversion loss constant of the mixer.
At the receiver end, the RF and LO signals will act as input and IF the output. The output
of the Down-converting mixer can be approximated as in (2.16).
K
VIF (t) = [cos(ω RF t ´ ω LO t) + cos(ω RF t + ω LO t)] (2.16)
2
A simple mixer can be implemented with a single diode. However, simple mixers have the
general disadvantage of having a high LO- and RF-leakage. There are two types of balanced
mixers designed to handle this problem; single and double balanced mixers.
The single balanced mixer is used to suppress the level of either the RF or LO input signal
while the double balanced mixer is used to suppress both. The advantages of using a single
balanced mixer is that it does not require high LO drive levels, it is also cheaper and less
complex. The advantages of the double balanced mixer are that all ports are isolated, This
preventing leakage, increases the linearity of the mixing and has a better spurious response
since all even order products are suppressed. This is why the double balanced mixer is in
wider use today than its single counterpart.
Mixers can be used to detect phase differences in the two input signals. Mixers however
often display some non ideal functionality such as DC-offsets when used in this configuration
[11].
Phase noise
Phase noise are random fluctuations in phase that are ever present in real signals. Since the
phase noise is generated from the uncertainty of the phase of the signal, the effect it generates
"propagates" outwards from the signal in the frequency spectrum as shown in Fig. 2.3 [8].
10
2.5. Analog circuits in RF receivers
Figure 2.3: Two systems using different oscillators showing the effect of phase noise Red:
noisy oscillator, Blue: system with ideal oscillator [8].
ADC
ADC stands for Analog-to-digital converter and is the component responsible for sampling an
analog signal and converting it into digital information. The basic idea of ADC functionality
will be described and some of the implementation types will be discussed. The reader is
referred to [7] for further theory regarding the implementation types of ADC’s.
Flash ADC
Flash ADC uses parallel connected comparators with different reference signals. The signal
is sampled one symbol at a time. Each comparator outputs one bit. They are simple in their
principle of operation and fast, but suffer from a large number of reference voltages and
relatively high power consumption.
Pipeline ADC
Pipeline ADC architectures perform conversion using multiple cascaded stages of low-
resolution ADCs. Each stage outputs the quantization error of the ADC, amplifies it and
sends it to the input of the next stage. This operation is performed until the last stage which
only consists of an ADC without quantization error output. It is slower than flash ADCs but
power consumption is not as high.
Delta-Sigma ADC
Delta-Sigma ADC utilizes a feedback loop to force input and output to similar levels, while
at the same time making use of low resolution (can be as low as 1 bit) ADC quantizers. The
quantization error (noise) is added to the output signal and shaped with the help of an inte-
grator within the delta-sigma loop. The integrator loop filter has the effect of a LPF for the
input signal and HPF to the quantization noise. We can therefore filter out the quantization
noise and keep the input signal.
AGC
AGC stands for Automatic Gain Control and is a control feature which is particularly used in
RF systems. It is used to actively adjust power levels in a system. For receivers, it is often
times used as automatic attenuation for keeping linearity and to extend dynamic range of the
ADC. In real time, we cannot know what the received signal strength will be, and we have to
take that uncertainty into account when designing a system.
11
2.6. Process variations
In the case of a signal weak enough not to be detected, an AGC will not be able to do
anything to improve performance. In the case of signal strong enough to either compress
gain in the system (destroying linearity) or being outside the dynamic range of the ADC, we
can actively adjust system gain to attenuate this signal.
Aspects of stability, noise figure and linearity all have to be taken into account for in order
to design AGC systems. By attenuating the signal for example, we will inevitably increase
noise figure as derived from (2.4).
There are many ways of implementing AGC functionality for receivers, but the one archi-
tecture focused on in this project has similarities to [14].
2.6 Process variations

When fabricating physical components for any system, there will be slight deviations in their
properties due to imperfections in the manufacturing and/or the materials being used. This
is referred to as the process variation of the component. In high performance RF systems,
the component parameters needs to be accurate to very high degree to ensure reliability of
operation. When designing RF-systems, these variations need to be taken into account to
make sure the variation can be compensated for or have narrow enough margin of error not
to disturb the larger system.
E.g., a filter can have a process variation in the pass-band attenuation that can attenuate
a signal more than what is acceptable. Moreover, the signal propagating through the filter
can be affected by attenuation ripple. These effects must be predicted in the design phase
through simulations that include parameters emulating process variations.
One way to compensate for variations in component properties is to do a "worst case
analysis" where all the different factors that determine system’s performance are taken into
consideration and are assumed to be at "worst case" scenario. Then one can evaluate and/or
estimate the performance of the system at in a "worst case-scenario". This method is effec-
tive but has the flaw of assuming all of these factors are independently affecting the system.
This is a rough estimation for performance evaluation since these factors are not necessarily
independent.
In order to determine a more accurate model of the absolute range of component per-
formance variation, IC-manufacturers use statistical tools. One of these tools is the Monte
Carlo analysis which can be used to determine the components statistical variation based on
a function of random number generation [6].
2.7 Modulation
This section aims to introduce the reader to the basic theory of RF modulation.
Modulation of a signal is the process of varying certain properties of a periodic waveform
(carrier signal) with another signal (modulating signal). A general way of thinking about
this scheme is that the modulating signal contains information and the carrier signal controls
where the radiated spectrum is located in frequency.
There are various ways to modulate a carrier wave using properties of waves. For a gen-
eral signal in time
S(t) = Acos(ωt + φ) (2.17)

There are 3 degrees of freedom to modulate the signal. Amplitude A, frequency ω and phase
φ. The analog modulation schemes are properly called Amplitude Modulation (AM), Frequency
Modulation (FM) and Phase Modulation (PM).
Digital modulation schemes use the same degrees of freedom as analog modulation, but
uses it to encode digital bits of information. The digital counterpart to the analog modulation
12
2.8. I/Q Data
schemes AM, FM and PM are Amplitude Shift Keying (ASK), Frequency Shift Keying (FSK) and
Phase Shift Keying (PSK).
Using the basic principles of modulation presented in this section, more advanced meth-
ods of modulation can be derived. For example, both amplitude and phase modulation can
simultaneously be utilized in the same modulation technique. [11].
2.8 I/Q Data

I/Q data is a form of data representation using the so-called in-phase and quadrature-phase
components of a sine wave. Using the trigonometric identity
cos( x + y) = cos( x )cos(y) ´ sin( x )sin(y) (2.18)

and applying it to a waveform
S(t) = Acos(ω0 t + φ(t)) (2.19)
it gives
Acos(ω0 t + φ(t)) = A[cos(φ(t))cos(ω0 t) ´ sin(φ(t))sin(ω0 t)] (2.20)
where
S I (t) = Acos(φ(t))cos(ω0 t) (2.21)
and
SQ (t) = ´Asin(φ(t))sin(ω0 t) (2.22)
are the in-phase and quadrature phase components of S(t).
For RF application this result can be applied for modulating a single waveform (2.19) with
information contained in its I and Q components. It also means that the data stored in I and
Q can be independently set and the resulting waveform is still in the form as in (2.19) [5].
In PSK, the most simple case is storing information with two states, where φ can store
either binary 0 or binary 1. For this, the advantage of having information stored in I and Q
components does not even need to be utilized if φ0 and φ1 are 0 and π respectively.
This idea can be expanded by introducing more states. QPSK (or Quadrature Phase Shift
Keying) utilizes 4 states of φ while holding amplitude is constant. Each state can store two
bits utilizing I/Q data. These states are φ11 = π4 , φ01 = 3π π π
4 , φ00 = ´ 4 and φ10 = ´ 4 [11].
Introducing amplitude as a degree of freedom to the modulation scheme, more than 2
bits per state as in QPSK can be utilized. An example of a I/Q modulation scheme using
both amplitude and phase modulation is QAM (Quadrature Amplitude Modulation). QAM
modulation has number of states on the form as in (2.23).
M = 2n (2.23)
QAM modulation schemes are referred to by their number of states on the form M-QAM.
For example, we have 4-QAM, 16-QAM, 32-QAM, 64-QAM and so on where the number of
bits per states is
n = log2 ( M ) (2.24)
By this result we can conclude that QPSK and 4-QAM are identical modulation schemes
even though the theoretical background is different [11].
A graphical representation of the states encoded in I/Q data is the constellation diagram. A
constellation diagram of QPSK states and 64-QAM states is presented in Fig. 2.4. X-axis data
is the in phase component I, and the y-axis data the quadrature phase component Q.
13
2.9. Receiver architectures
Figure 2.4: Left: QPSK, Right: 64-QAM. Simulated in VSS
2.9 Receiver architectures

This section introduces two types of receiver architectures, i.e., the superheterodyne and ho-
modyne receivers.
General receiver architecture

The types of receivers which this thesis covers consist of the following parts: Receiving an-
tenna, filtering, amplification, down-conversion, sampling, channel filtering and decoding.
Superheterodyne Receiver
The main functionality which identifies superheterodyne receivers is the use of an interme-
diate frequency (IF). Superheterodyne receivers might use more than one down-conversion
to overcome problems due to LO stability at high frequency RF. After each down-conversion,
image frequencies created by the mixing process and ideally intermodulation products are
filtered out [7, 11]. A general schematic of a so called dual superheterodyne receiver, which uses
two down-conversion stages is presented in Fig. 2.5 and Fig. 2.6
Talking about superheterodyne receivers, one issue that appears is so called image rejection.
The problem is characterized by a trade off between image rejection and adjacent channel
suppression. The problem of image rejection appears since the mixer outputs two dominant
signals of frequencies |ω1 ´ ω2 | and |ω1 + ω2 |. Since we have two cases where we can mix to
a desired IF, this means RF frequencies of distance 2ω IF in frequency will mix to the same IF
[12].
14
Figure 2.5: Superheterodyne receiver architecture [13]
Figure 2.6: Superheterodyne receiver architecture with I and Q data [13]
Homodyne Receiver
Homodyne, Direct-conversion or Zero-IF receivers directly convert the RF signal into baseband
without any IF stage. Down-conversion is achieved with a quadrature down-converter split-
ting up in-phase (I) and quadrature-phase (Q) components of a signal, which is then filtered
and sampled. The reasons for quadrature down-conversion of the signal in I and Q com-
ponents is to avoid so called "folding" from the negative frequencies and in case of phase
modulated signals. In case of IQ modulated signals, the different sidebands of the RF signal
contains different information and splitting up these into two different phases at demodula-
tion avoids folding since the different sidebands fall on each side of baseband [12].
The main difference here from a super heterodyne receiver is that channel selection is
achieved with a low pass filter instead of a bandpass filter since the signal is already down-
converted to baseband. The LO signal is tuned to the incoming RF frequency for achieving
zero-IF [7].
Homodyne receivers come with some technical challenges. LO leakage from the mixers
result in so called self mixing which has the effect of adding a DC offset to the output of the
mixer. IQ imbalance is also an issue when talking about homodyne receivers, although this
is not necessarily unique to this type of receiver.
Two types of homodyne receivers are presented in Figures 2.7 and 2.8.
15
Figure 2.7: Homodyne receiver architecture [13]
Figure 2.8: Homodyne receiver architecture with I and Q data [13]
Discrete-Time Receivers
In certain applications, the use of direct RF sampling can be used to advantage. One sim-
ple case is to enable multi standard radio on one single front end architecture. This leaves
more design space for software defined radios (SDR), which have the possibility to increase
versatility and reduce bill of materials since a lot of the functionality lies in integrated digital
circuits. However, RF sampling of various kinds comes with a new set of challenges. Remov-
ing analog RF devices from the design puts high performance requirements on sampling and
signal processing in order to compete with established and well understood technologies.
A few different RF sampling architectures which have been reported on over the years are
presented here.
The so called analog processing receiver, uses analog filters and decimation instead of a
mixer after the LNA in order for the ADC to sample the signal at a reasonable rate. Interfering
signals and blocker signals are therefore not mixed down with LO harmonics as IM products,
but instead aliased when sampled unless filtered. To tackle this problem, anti-aliasing filters
can be implemented or the sample rate of the ADC must be increased. The first reported
implemented receiver of this type was presented in [15].
Direct digitization receivers apply ADC functionality directly after LNA without adding any
extra analog hardware. There are various types of these receivers depending on sampling
method and of ADC [7].
16
2.10. Digital Signal Processing
Another discrete-time receiver well worth mentioning but not discussed any further are
Hybrid-filter bank receivers [16] which use the principle of decomposing the signal in the fre-
quency domain using a bank of analog filters. There are various other kinds of discrete-time
receivers and it is an active topic of research.
2.10 Digital Signal Processing

Digital signal processing deals with how the signal is handled from the ADC to the eventual
recreation or storage of the analog information. The first step of any digital processing is the
sampling of the analog signal.
Sampling
Sampling is the act of measuring a signal value at certain points in time. How often these
measurements are done is called the "sampling rate" or "sampling frequency" [ Fs ]. How this
sampling frequency relates to the signal frequency being measured dictates if the information
of the original signal will be preserved or not. Sampling frequency is derived through the
time between measurements, i.e, samples. It is the measurement of how many samples per
second that are performed.
The Nyqvist theorem states that any signal needs to be sampled for at least twice its fre-
quency or simply put:
Fs
Fsignal,max ă (2.25)
2
A signal that has a frequency higher than the Nyqvist frequency will naturally form a
mirror signal on the opposite side of the Nyqvist frequency due to having the samples fall on
the same places on the signal. The mirror signal will fall on Fs ´ FSignal as shown in Fig 2.9.
This is also known as aliasing [9].
Figure 2.9: Signal mirroring (aliasing) around the Nyquist frequency [9]
Spectrum analysis
Spectrum analysis is a tool used when conducting measurements and analyzing signals.
Fourier transformation of a signal decomposes it into its spectral components. In the case of
signal in time, the transformed signal will be a function of frequency.
The discrete version of the Fourier Transform is called Discrete Fourier Transform (DFT)
and is widely used to analyze sampled signals. The more samples analyzed, the higher the
frequency resolution will be on the Fourier Transformed signal.
As signals are sampled, some things need to be taken into account for when performing
spectrum analysis using DFT. A finite frequency means aliasing will occur when measuring
frequencies above the Nyquist frequency.
17
Another problem that arises with analyzing finite data is that we cannot assume first and
last sample continuously connect with perfect periodicity. This gives rise to uncertainty in the
frequency spectrum as the signals will appear to contain information far out from the center.
One way to tackle this issue is to apply so called Window functions to the spectrum to
mitigate some of these effects. Windowing does this by applying different functions in time
domain that minimizes the amplitude of the discontinuos area of the signal that would other-
wise cause high frequency spikes in the frequency domain. In Fig. 2.10 the difference between
a spectrum with applied window and one without is presented where the difference can be
seen clearly.
Figure 2.10: VSS simulation of a QPSK signal spectrum with Hanning window (Blue) and
without window function (pink)
Digital filtering
In order to minimize the risk of aliasing, the signal cannot contain frequencies above the
Nyquist frequency. This can be achieved by applying a low pass filter with a cut off frequency
at the Nyquist limit i.e., an anti-aliasing filter. However, because there is no filter with an
instant transition band, the cut off frequency needs to be slightly below the Nyquist limit in
order to ensure that the stop band attenuates the higher frequencies enough for the aliasing
to be negligible [2].
A filter that is especially well suited for this is the Finite Impulse Response or FIR-filter,
which is a type of digital filter. The FIR filter is finite because it settles to zero in a finite time.
An IIR (Infinite Impulse Response) filter however can decay towards zero for an infinite time.
FIR filters are based on a N-number of parallel "taps" as seen in Fig. 2.11.
18
Figure 2.11: Transposed direct form FIR filter [2]
The mathematical expression of the output signal y given an input signal x through a FIR
filter with filter coefficients h is given by (2.26).
Nÿ
´1
y[n] = h [i ] x [ n ´ i ] (2.26)
i =0
In order to reduce the processing required if the sample rate is a lot higher than the signal
frequency, downsampling reduces the amount of samples that has to be processed. By ap-
plying Half-band FIR filter and then downsampling (decimating) the signal, we can keep the
information within the boundaries of the Nyquist frequency while minimizing effects from
aliasing.
19
3 Development
This chapter presents the detailed approach to create a simulation platform with focus on
the budget analysis simulation tool. After some consideration about the complexity of a
communication system in terms in RF circuit design when non-idealities of the real-world
components, process variations etc. must be considered, the receiver model is introduced
along with the added functionality as required by project description. The way temperature-
and frequency-dependency are implemented in the model is detailed. Models for simulat-
ing the effect of LO phase noise, mixer M x N products and IQ-imbalance are described as
well as models for gain calibration and automatic gain control. The receiver model includes
also aspects of digital signal processing (DSP) for complete characterization of the receiver
performance. Finally, the simulation platform and the developed templates for link budget
simulations and time-domain simulation are presented in detail.
3.1 NI AWR Design Environment

In order to construct a simulation platform, a development platform is needed. One of the
purposes of the project, as mentioned, is to examine how well National Instruments AWR
Design Environment environment can handle such tasks. The NI AWR Design Environment
is an Electronic Design Automation (EDA) software tool dedicated to RF/microwave system
design [3]. The platform allows complex high-frequency systems to be modelled, simulated
and verified. Software segments like Microwave Office and Visual System Simulator (VSS)
are included. Microwave Office is dedicated to the RF/microwave circuit design on compo-
nent level and allows nonlinear, frequency- and time-domain analysis, as well as electromag-
netic (EM) analysis [4]. VSS is dedicated to system design based on behavioral models.
The advantage of the AWR development platform is that it allows customization of codes
(scripts) for desired tasks and functionality. This customization is enabled by the application
programming interface (API). The programming languages are popular ones, e.g., C++. This
leads to AWR being able to get new functions implemented faster as well as having fewer
persistent bugs. Their main competitor, Advanced Design System (ADS), Keysight Technolo-
gies, uses their own proprietary language for coding. This has some advantages but put a
limitation in the possible grade of customization.
20
3.2. Receiver impairments
Visual System Simulator

Visual System Simulator (VSS) is the system-level simulation environment included in the
AWR software. VSS is dedicated to wireless communication and radar design. It supports
measurements of system parameters for cascaded RF blocks, nonlinear behavior and spu-
rious effects analysis, and measurement of metrics specific to communication applications,
e.g., the Bit Error Rate (BER), [4]. It also supports signal processing in complex, real and dig-
ital domain and a combination of these, [4]. As introduced in Chapter 1, the main goal of
this project - a practical, user-friendly simulation platform for receiver budget analysis – will
make use of the VSS tool due to the customization possibilities that the software allows more
than other equivalent tools on the market.
3.2 Receiver impairments

Given the complexity of a communication system and of the signal processing performed
within it, a series of non-idealities of the real-world component and design faults may affect
the performance of the entire system. A part of these non-idealities were mentioned in Chap-
ter 2. Their effects on the signals to be processed should be identified and predicted through
simulations. A few of these effects are listed:
• Non-linearity: compression, intermodulation, spectral regrowth
• LO-leakage: self-mixing, M x N harmonics
• Noise figure, not optimized: sensitivity, SNR at the output
• Process variations affecting all components in their electrical parameters, matching, etc.
• Temperature effects etc.
3.3 Receiver model implementation

This section describes the implementation method of the receiver model and the different
features listed in list of requirements in Section 1.2.
As shown in Chapter 1, the main goal of the project is to create a simulation platform
with focus on the budget analysis simulation tool for wireless applications. This tool should
be user friendly and easily adapted to the company requirements, e.g., allowing parameter
simulations of the component models. Budget analysis is a powerful method frequently used
in top-level system design. Through system budget simulations, linear and non-linear char-
acteristics of the overall system can be determined as a function of the characteristics of the
components in the chain. A typical design cycle includes:
• Receiver modelling as a chain of components (filters, LNA, mixers, etc) according to the
actual receiver architecture
• First-hand estimation of the component characteristics that are in parameter form,(gain,

compression, noise figure, etc.)
• Budget simulation on top-level, e.g., on receiver level
• Compare the simulation results to the required specifications of the system (receiver)
• If specification not met, modify/optimize some components parameters and conduct

simulation loops until the system specifications are met
21
3.3. Receiver model implementation
From this pseudo flow-chart the results of how important top-level simulations are in the
design of complex, wireless systems. Since they comprise of a multitude of circuits operat-
ing under different circumstances, e.g., signal levels, frequency etc., and performing signal
processing of high complexity, these system level simulations are necessary to make sure the
system is working as intended.
Homodyne RX
The basic receiver lineup is based on a general homodyne receiver model presented in Fig.
2.8. A system diagram of the receiver lineup is presented in Fig. 3.1 with a few differences.
Since VSS supports the use of complex signals on the form S(t) = I (t) + jQ(t) a single mixer
acts as an IQ demodulator by itself with the right settings. Another difference is that there is
no Variable Gain Amplifier (VGA) in Fig. 3.1. The reason for this design choice was that this
feature was not assessed as "basic". This feature will be presented in the next lineup used for
the project.
Figure 3.1: Basic homodyne receiver lineup
The receiver lineup implementation for this project however has a few more features in-
cluded for a more detailed model. This lineup is constructed based on some of the specifica-
tions of an existing 5G radio receiver and the implementation is presented in Fig. 3.2. It uses
features such as temperature dependent parameters, losses and VGA’s.
22
Figure 3.2: Homodyne receiver lineup with features
Temperature dependency
In order to approximate real system performance, the temperature dependency of certain
component parameters needs to be taken into account and subsequently modelled. In a lot of
cases, when temperature is static, component properties such as gain/loss behaves the same
independent of temperature and can be modelled easily. However, when there is a system
that will operate in a wide range of temperatures and the system itself is prone to self heating,
the physical structure of the components causes the performance to drift.
In order to ensure correct performance and that the system meets regulatory and/or in-
ternally set requirements, the temperature dependency needs to be taken into account.
Temperature variation is implemented with respect to a nominal temperature. The nomi-
nal temperature is defined as the arithmetic average of the maximum and minimum temper-
ature given in 3.1.
Tmin + Tmax
Tnom = (3.1)
2
where temperatures are defined as either Celsius or Kelvin. For a temperature varying
parameter Q, the value is modelled as a function of T
T ´ Tnom
Q( T ) = Qnom + Qtemp (3.2)
Tmax ´ Tnom
where Qtemp is the user specified parameter for temperature variation. To give an example
of how this works, lets say we have an amplifier with nominal gain Gnom = 10 dB and a
temperature varying parameter Qtemp = ´1.2. At T = Tmax , G = 8.8 dB and at T = Tmin ,
G = 11.2 dB.
The gain/loss variation due to temperature can be compensated for by using a variable
gain amplifier that can attenuate/amplify a signal depending on what temperature is in the
system. This behaviour can be modelled in AWR by knowing the target gain for two different
temperatures and interpolate the gain linearly between these two temperature values. The
drift in gain/loss can thereby be compensated for in the model for static (time independent)
simulations.
For time domain simulations, it is convenient to use a look up table of pre-measured gains
at different temperatures while sweeping temperature values for the system.
23
Frequency dependency
As well as in the case above with temperature, components tend to vary in performance
depending on frequency. This is can be modelled in various ways in AWR depending on what
simulations are being done and what components are being used. Frequency dependency
can be modelled linearly, like temperature dependency is modelled in this project, but since
temperature dependent data for the different components may be difficult to obtain, it is
instead made part of the AGC system by taking the frequency dependent attenuation of the
system blocks in S-parameter files. A number of points are placed on the S-parameter curves
and then an interpolation is made between these. The power measurement for the AGC is
made with regard to S21.
Frequency dependency could be implemented in this way for the entire lineup, but it
would require a complete redesign of the lineup as well as lose a lot of what makes VSS
simple to perform simulations in due to that the component properties would be complex to
change and would have to be specified in non-intuitive ways.
The various filters implemented in the model are also a way of representing the frequency
dependency of the system. Frequencies are attenuated differently depending on where on the
spectrum they fall while still being propagated through the system.
Process variation
There are two types of process variations implemented. One for each of the simulation plat-
forms respectively. This was done because of how the component parameters for the analog
lineup are specified in the different platforms. The budget document can perform yield anal-
ysis as part of VSS built in functionality, where the user can specify the type of distribution
and how much the chosen component parameter should vary Fig. 3.3.
Figure 3.3: Process variation for Gain, P1dB and IP3 for a component in the analog lineup in
the budget platform
When performing a yield analysis in VSS, a random number is generated in the specified
interval and used as the parameter value. This can be done multiple times as a sweep, leading
to a different approach being used in the time domain platform to reduce simulation time.
In the time domain platform, the process variation is specified alongside the other com-
ponent values in the "Global Definitions"-folder as seen in Fig. 3.4.
Figure 3.4: Process variation as specified in the Time Domain platform
24
Table 3.1: LO phase noise text file format

(,Hz) (,dB)
100 -80
1e3 -90
10e3 -95
100e3 -100
1e6 -125
10e6 -145
The process variation is then multiplied with a factor K_[...] indicating the maximum, min
and normal case for the parameter. This is then added in turn to the component parameter
in the analog lineup. This is suitable for the time domain platform since there are no sweeps
involved and the most interesting cases of i.e. maximum, minimum or normal gain can be
simulated with the manual input of the K_[...] factor. This can be seen in detail in Fig. 3.5.
Figure 3.5: Factor determining max, min and nominal case for process variation.
LO phase noise
Phase noise is modelled in AWR with a text file, a phase noise mask, attached to the LO input
tone of the mixer. The text data file contains frequency offset-dBc/Hz data in a format as
Table 3.1.
The text file is then applied to a tone source as phase noise as shown in Fig. 3.6.
Figure 3.6: LO phase noise
Mixer M x N products
The mixers inside the IQ modulator outputs a signal on the form (2.7). However, to model
the specific behavior of the mixer, the user needs to specify the output levels (dBc) of the
intermodulation products on the form (2.8), where m and n are indices in a resulting matrix.
In AWR, the user needs to input this matrix in the mixer model as a text file. The AWR
implementation of this feature is presented in Fig. 3.7. This example shows a matrix with
indices 0x0 to 4x4.
25
Figure 3.7: M x X text file as implemented in in the VSS mixer block
IQ imbalance
IQ imbalance models non ideal aspects of the IQ demodulator. It is implemented as a block,
containing parameters DC offset, amplitude imbalance and phase imbalance. Units are volts,
dB and radians.
Gain calibration
Gain calibration is used as to compensate for process variations and temperature variations
in the system. It is also vital for the system to estimate its gain for DSP operations. It uses
VGA blocks as variable attenuators. It is therefore important that the "Target gain" is not set
to high since we only compensate by attenuation.
Two different gain calibration methods were implemented in AWR. The first model calcu-
lates the sum of gain parameters from the RX lineups (3.3) and the total temperature varying
parameter (3.4).
N
ÿ
Gnom = Gn (3.3)
n =1
N
ÿ
Gtemp = Gtempn (3.4)
n =1
Process variations are modelled by adding together the statistical gain variations in each
element in the RX lineup as in (3.5).
N
ÿ
G process = G processn (3.5)
n =1
Adding together nominal gain, temperature varying gain and statistical gain variations
we can determine the total gain by (3.6).
T ´ Tnom
Gtot = Gnom + Gtemp + G process (3.6)
Tmax ´ Tnom
Gain calibration was then applied as an attenuation block attenuating the signal as in (3.7).
#
Gtot ´ GTarget , if Gtot ą GTarget
Lcal = (3.7)
0, otherwise
Implementation of this method in AWR is presented in Fig. 3.8.
26
Figure 3.8: Gain calibration implementation using equations
The second implementation method of gain calibration uses a PID (Product, Integrator,
Derivative) controlled gain calibration loop to calculates attenuation by gain compensation
before the main simulation starts. The AWR implementation method is presented in Fig. 3.9.
Figure 3.9: Gain calibration implementation using PID controller
Receiver AGC models

Two types of AGC functions were implemented, one equation based feed forward model and
one feedback model. The feedback model works exclusively for time domain simulations
since it operates on previous samples while the feed forward model was designed to operate
in any type of simulations utilizing equations and boundary conditions.
As discussed in Section 2.5, AGC is used to limit signal power going to the ADC utilize
higher dynamic range for linear gain. As components exhibit nonlinear behavior to a higher
degree with stronger signal power, AGC can be implemented to mitigate some of these ef-
fects.
AGC functionality however comes with some inherent problems itself. Looking back at
Friis formula for noise (see (2.4) ), we find attenuating the signal in the system increases noise
27
figure. In the moment we attenuate the signal, we also generate discontinuity in the data
stream.
There are other problems that arise with control systems. Stability is one aspect that has
to be taken into account since we rely on negative feedback with added delays.
VGA placement in the receiver lineup along with power measurement placement also
matter for optimal control.
Feed forward AGC

The feed forward model was implemented using estimation of the output signal power given
boundary conditions such as input signal power, frequency and linear gain. This model has
the advantage of relieving computational power from simulation run-time but the disadvan-
tage of guessing output conditions, giving room for inaccurate behavior. Simulation settings
and equations for this model are presented if Fig. 3.10.
Figure 3.10: AGC Feed forward model
The estimated output power is given by 3.8.
Pout = Pin + GTarget + H ( f c ) (3.8)

H ( f c ) is the filter response of the system at the center frequency input signal and GTarget
the target gain of the system from antenna to ADC. The power is given in RMS. The disad-
vantage of this AGC model is that it is difficult to estimate RMS output power from multiple
signals with different properties. This AGC does not include hysteresis functionality unlike
the feedback AGC.
Feedback AGC
In order to model AGC functionality in the system for time-domain simulations, feedback
control can be used instead of manual control.
The receiver feedback AGC model implemented in AWR utilized comparators with hys-
teresis built in. In contrast to the regular logical comparator which outputs either True or
False depending on if input passes the condition, the comparator with hysteresis utilizes two
conditions, one condition for initial state and when the first condition was passed. The elec-
trical analog to this behavior is the well known Schmitt trigger design which is described in
[1]. The comparator with hysteresis implemented in AWR is presented in Fig. 3.11.
28
Figure 3.11: Comparator with hysteresis implementation in AWR
For an AGC, we are interested in power measurement in order to control VGA’s. An AGC
controller consisting of four comparators with different threshold levels was implemented in
order to control a maximum of four VGA’s. This can be extended to any number of compara-
tors. The AGC controller implemented in AWR is presented in Fig. 3.12.
29
Figure 3.12: AGC Controller implementation in AWR
Power measurement is important for implementing AGC functionality. In the case for the
AGC implementation for the project, the running average of N samples of the incoming RMS
power is utilized, where N is user specified. Other user specified parameters for the AGC are
hysteresis levels, delay between triggering VGA’s and a start delay for simulation purposes.
The power measurement AWR implementation is presented in Fig. 3.13.
30
Figure 3.13: Power measurement for AGC controller
ADC model
The Delta-Sigma (∆-Σ) ADC implemented and tested in VSS was a 2:nd order ∆-Σ as indi-
cated by the number of integrators and/or the number of feedback loops in Fig. 3.14.
Figure 3.14: VSS schematic of the tested delta sigma ADC
This ADC model was not implemented due to the drastically increased simulation times
when included in the receiver lineup for time domain simulations. It was also not compatible
with budget simulations and was therefore not used for that platform either.
Digital interface
The digital interface was modelled using frequency transformation, frequency decimation
along with FIR filters and a channel filter. A simple model of this is presented in Fig. 3.15.
31
3.4. Simulation platforms
Figure 3.15: Digital interface with FIR filters
FIR filter implementation

FIR filters were implemented with the help of coefficient based FIR filters. These coefficients
were generated in Matlab with the help of built in FIR functions. The resulting coefficients
were then exported to the AWR project.
3.4 Simulation platforms

In Section 1.2, the requirements for the simulation tool are presented. In order to cover these
requirements, different simulation platforms in the form of system diagrams were imple-
mented in AWR, where different aspects of the RF lineups were analyzed. For example, one
document was created for analyzing budget parameter, while another had the purpose of
analyzing AGC behavior. All these documents are presented below.
Impairment implementation for link budget simulation platform

In order to simulate blocking scenarios, i.e. when undesired signals are received by the sys-
tem using budget simulations, functionality not native to VSS had to be implemented. One
measurement interesting for this simulation type is degradation. To accurately model degra-
dation of a channel in a system, as many receiver impairments as possible needs to be taken
into account.
Increase in noise figure due to AGC attenuation can be implemented using available mea-
surements built in to VSS. Estimation of phase noise can also be implemented with the help of
built in measurements using the values in Table 3.1. IM3 signals generated from two signals
can also be estimated using built in measurements of IP3. Undesired spurious response from
the IQ demodulator was not as easily implemented however. With the help of scripting using
VSS scripting editor, these mixer products can be estimated and taken into account for when
measuring Degradation.
ADC impairments such as sampling, aliasing and jitter were not implemented in the link
budget simulation platform since these parameters only makes sense in a time domain sim-
ulation. The exception being jitter which could be implemented using some more advanced
scripting.
Impairment implementation for the time domain simulation platform

Unlike the budget simulation, the resulting degradation can be calculated with the help of
power measurements in each channel. The time domain engine takes all impairments into
account listed in Section 1.2 except for ADC jitter since a simpler version of the ADC was
implemented. This was due to simulation times being affected by the delta-sigma ADC.
32
3.4. Simulation platforms
ADC sampling and aliasing are all taken into account for since finite sampling frequency and
decimation are used.
33
4 Results
The results of the project are presented in this chapter. This includes implemented function-
ality along with simulation examples from the AWR project documents.
4.1 Simulation platform results
Functionality
The AWR project ended up containing two different simulation platforms. The core function-
ality includes:
• Temperature dependency
• Frequency dependency
• Gain calibration
• AGC
• IQ imbalance
• User specified M x N mixer behavior
• User specified phase noise
• Budget simulation platform
– Gain, Noise Figure, P1dB and IP3 measurements

– Blocking scenarios
– Yield analysis
• Time domain simulation platform
– Digital interface for channel filtering

– Blocking scenarios
– Spectrum analysis
34
4.1. Simulation platform results
The project aimed to implement PLL functionality and a proper ADC model as well, but
this was not achieved, however the other goals of the project listed in Section 1.2 were. The
functionality can also be extended to include other types of measurements with the given
simulation platforms.
Link budget simulation platform

The contents of the template document for link budget simulations is presented in Fig. 4.1.
The design philosophy, as in the other template documents to let the user choose receiver
lineup and specify parameters relevant to the simulation in question. In the case of budget
simulations, these are signal, VGA/AGC parameters and gain calibration. Budget simula-
tions are performed between the input and the output of the DUT.
The link budget simulation platform uses yield parameters in each component in the RX
lineup (Fig. 3.2). This means that process variations in each components are modelled with
statistical distributions, for example uniform, Gaussian and log-normal distributions. This
feature can be to simulate statistical variations in system parameters. This is not included in
the time domain simulation platform.
Figure 4.1: Budget setup
The budget simulation compensate for variations in power by a PID-controlled gain cal-
ibration block as shown in Fig. 3.9. The budget simulations use the PID version of the gain
calibration since the VSS PID block simulates steady state when budget simulations are used.
This is suitable for budget simulations since they are time independent and only perform
calculations on the boundary conditions of the system. The PID block also supports time do-
main simulations, but when implemented in those types of systems, the transient time of the
controller causes the simulation time to increase drastically which is undesirable for a real
time simulation platform.
Time domain simulation platform

The time domain simulation platform includes the analog receiver lineup, gain correction
and FIR filter branches to simulate system parameters, and to visualize the spectrum of the
channel. The current system diagram in this platform is a demonstration of blocking signal
scenarios. The user can specify an unwanted signal and see the resulting spectrum in the
channel with and without this signal. Degradation measurements are also performed. The
system diagrams present in the time domain simulation platform are presented in Fig. 4.2
and Fig. 4.3.
35
Figure 4.2: Time domain simulation platform - Blocking signal and noise source
Figure 4.3: Time domain simulation platform - Noise source
Gain correction for AGC is also included for time-domain simulations. Gain correction is
a digital operation used to compensate for attenuation from AGC When a VGA attenuator
is turned on inside the analog RX block, the corresponding amplifier is turned on inside the
gain correction block. In real systems, this operation is performed digitally after the ADC in
order to an extent achieve constant system gain. The system diagram for the gain correction
operation is presented if Fig. 4.4.
Figure 4.4: Time domain simulation platform - Gain correction system diagram
The gain calibration system used in the time domain simulation platform is equation
based as seen in Fig. 3.8. This is an entirely equation based system and is used because
the PID version of the gain calibration was considered too slow when implemented in time
domain simulations.
36
ADC
The ADC model chosen is the same for both simulation platforms. It is a VSS amplifier block
with 0 gain and ADC parameters such as IP3 and NF specified. This results in a simple
general component without the ADC characteristics such as jitter.
Feedback AGC
The power of the signal and the measured power by the AGC is plotted in Fig. 4.5. The power
level of the signal is what the AGC uses to trigger the control signals of the VGAs as shown
in Fig. 4.6.
Figure 4.5: Power measurements of feedback AGC. Blue: Instant power in channel. Pink:
measured power
The power meter block used to measure the power of the channel measures the average
power and outputs it as a voltage for the AGC to use as input. Because it is an average, there
is a slight delay in the measurements, adding to the time it takes to simulate and making it so
that the response is not instant, as seen in Fig. 4.5. In the blue plot, three VGAs are triggered,
reducing the power each time.
37
Figure 4.6: Activation of control signals for the feedback AGC
The control signals are triggered and released dependent on if the measured power ex-
ceeds the user specified trigger and hysteresis levels of the individual VGAs. In the case
of Fig. 4.6, three VGAs are triggered, at the 100 ns, 1100 ns, and 2100 ns respectively. The
corresponding power level can be seen in Fig. 4.5 at the same time stamps.
Simulation times
In Tables 4.1 and 4.2, simulation time results are presented for the budget and the time do-
main platform with a few different settings. In Table 4.1, number of sweeps as well as gain
calibration method are varied. Since there is only one AGC method (Equation based) used
for the budget platform, these are the only parameters that the user can vary for different
results. We find that using equation based gain calibration will improve simulation times,
with the downside that yield analysis using the AWR built in tool cannot be performed in
this configuration.
Table 4.1: Simulation times - Budget platform

Simulation type Gain calibration No. of sweeps Time (s)
Budget (Cascaded) PID block 4 3.29
Budget (Power Sweep) PID block 41 33.10
Budget (Yield) PID block 404 303.18
Budget (Blocking) PID block 41 60.48
Budget (Cascaded) Equation based 4 0.24
Budget (Power Sweep) Equation based 41 1.07
Budget (Yield) Equation based - -
Budget (Blocking) Equation based 41 2.84
38
4.2. Budget simulations
The time domain platform contains more parameters that can be varied unlike the budget
platform such as simulation stop time and sampling rate. For the sake of keeping things sim-
ple, sampling rate is kept constant for all simulations and only one gain calibration method is
used (equation based). Table 4.2 clearly shows that when the feedback loop AGC is included,
simulation times are negatively impacted. The simulation stop time setting is also important
for total simulation time. Having a longer simulation stop time will give a more accurate rep-
resentation of the output spectrum of the signal. The downside is a longer total simulation
time.
Table 4.2: Simulation times - Time Domain platform

Simulation type AGC Simulation stop time (ms) No. of sweeps Time (s)
Time Domain Equation based 1.25 1 37.48
Time Domain Feedback loop 1.25 1 370.77
Time Domain Equation based 0.5 17 362.06
Time Domain Feedback loop 0.5 17 3962.91
These results might vary depending on which computer is running the simulation. Simu-
lation times can also vary from simulation to simulation. The results presented in this section
should therefore be interpreted relative to each other. They should give an idea of how sim-
ulation configuration parameters can impact simulation times.
4.2 Budget simulations

The user is presented with simulations for cascaded parameters and power sweeps. The user
interface for simulated cascaded parameters is presented in Fig. 4.7 and for power sweeps in
Fig. 4.8. The main difference between cascaded simulations and power sweep simulations
is that cascaded simulations plot block contributions as the x-axis, while power sweeps use
input power as x-axis.
Figure 4.7: User interface for cascaded parameter simulations
39
Figure 4.8: User interface for power sweep simulations
Degradation measurements were obtained by adding impairments from gain compres-

sion, AGC attenuation, mixer MxN behavior, IP3 and LO phase noise. Degradation results
with LO phase noise from a blocking signal 20 MHz and 70 MHz from channel center fre-
quency are presented in Fig. 4.9.
Figure 4.9: Degradation simulation with budget simulation platform. Left: Blocking signal 20
MHz from channel. Right: Blocking signal 70 MHz from channel.
Gain calibration
Gain calibration in the budget document uses a PID model to control the attenuation level of
a VGA. The user can set a variable to ON/OFF to control this function. With gain calibration
turned off, the VGA gain level is constantly set to 0 dB. The cascaded gain of the receiver
lineup with gain calibration turned off is presented in Fig. 4.10. Fig. 4.11 shown the results
when gain calibration turned on. Gain calibration target level was set to 28 dB.
40
Figure 4.10: Cascaded gain with gain calibration turned off
Figure 4.11: Cascaded gain with gain calibration turned on
AGC
AGC functionality in budget simulations uses the feed forward model presented in Section
3.3. This function can be toggled by setting a variable to either ON/OFF. When AGC is turned
off, the power sweep of system gain is presented in Fig. 4.12 and with AGC turned on in Fig.
4.13.
41
Figure 4.12: Gain power sweep with AGC turned off
Figure 4.13: Gain power sweep with AGC turned on
Yield analysis
Yield analysis can be performed to emulate process variations in components. If yield anal-
ysis is performed, the result is presented as in Fig. 4.14. The faded blue lines represent the
various yield sweeps and the one darker blue line in each graph is the nominal result.
42
4.3. Time domain simulations
Figure 4.14: Yield analysis for cascaded parameter simulations
4.3 Time domain simulations

Since the time domain simulations was divided into two simulation platforms, the results are
presented alongside its respective simulations. The channel spectrum simulation results con-
tain the in- and out-spectrum of the DUT and the spectrum of each digital channel. This can
be seen in Fig. 4.15. In each of the graphs presented, there is brown and pink spectrum. The
pink spectrum represents the spectrum of each measured point with only the thermal noise,
while the brown spectrum is the measurements taken at the same place but with blocking
signal as well as noise. This is to show how the blocking signal affects each channel. Even
though the signal does not hit the channel, it clearly affects the noise floor as seen in Fig. 4.15
43
Figure 4.15: Time domain channel simulation results. Channels: 10 MHz, 5 MHz, 3 MHz and
the in- and out-spectrum. Blocking signal 20 MHz from channel. Channel at center frequency.
The graphs presented as the results of the degradation simulations are presented in Fig.
4.16, Fig. 4.17, Fig. 4.18 and Fig. 4.19. Degradation is a measurement of how a channel is
affected by interference with respect to the same channel without interference.
Figure 4.16: Output spectrum with blocking signal 70 MHz from channel. Channel at center
frequency.
44
Figure 4.17: Channel degradation with blocking signal 70 MHz from channel. Left: Time
domain simulation. Right: Budget simulation.
Figure 4.18: Output spectrum with blocking signal 20 MHz from channel. Channel at center
frequency, with LO-phase noise on signal and intermodulation spurios interferers.
45
Figure 4.19: Channel degradation with blocking signal 20 MHz from channel. Left: Time
domain simulation. Right: Budget simulation.
If spurious effects from the IQ demodulator land in the channel, the degradation becomes
more evident than in the cases only affected by noise increase from AGC attenuation and
phase noise. This is presented in Fig. 4.20. Here, we see a mixer product falling inside the 10
MHz channel, but not in the 3 MHz and 5 MHz channels.
Figure 4.20: Channel degradation with mixer product in channel. Left: Channel filter spec-
trum with mixer product from blocking signal. Right: Channel degradation with mixer prod-
uct from blocking signal.
Digital interface
The digital interface is the block after the gain correction block in the schematics. In the real
system, the gain correction is done digitally in the digital IC and is therefore everything post
ADC in the DUT. The digital interface consists of three channels with different channel FIR-
filters. The filter lineups are presented in Fig. 3.15.
The resulting spectrum graphs from the filter lineups are presented in Fig. 4.21, Fig. 4.22
and Fig. 4.23. These show the different filter characteristics as well as the resulting channel
filter output marked in black.
46
Figure 4.21: Input spectrum of the digital interface - 3 MHz channel
47
These three spectral graphs above show the narrowing down of the digital filters to the in-
dividual channels, marked in black, and the correct channel widths. each of the three figures
corresponds to a different channel with different widths and the coloured graphs represents
the filters in the filter chain of the channel. the first filter is the widest and the last in the chain
is the most narrow as the signal propagates through the chain and is decimated and filtered
in each step down to the final channel filter.
48
5 Discussion
In the discussion part of the thesis, the result, method and work as a whole is analyzed to see
what compromises and decisions were made. What could be improved or done differently
will also be discussed as well as a reflection on the subject and its wider context, applications
and where it could go from here.
5.1 Results
The results obtained from this project are not necessarily only what is shown in the graphs,
but more the presentation and simulation setups that provide the results. The result is rather
the set of functions included in the VSS project. Using the simulation platforms and models
as a template for further work, a user can test various receiver lineups in this environment
for system-level simulations in a more ”easy to understand” manner compared to previous
simulation tools.
However, not all functionalities from the project description were included in the final
AWR projects. This mainly includes functioning ADC models, which has an effect on the
reliability of the simulation results. There are a number of design choices for modelling
functionality such as gain calibration and AGC that have limitations. This will be further
discussed in Section 5.2.
Since VSS is not a perfect platform, there are some functions that cannot be implemented
that might become possible to do if National Instruments is given feedback on the platform.
For example, the component parameters (such as gain, NF, IP3 etc.) in the lineup are specified
differently in the time domain simulation platforms and in the budget one. This is because of
how yield analysis is implemented in VSS. Since yield analysis is not practically possible in
time domain it is only implemented in the budget platform.
The issue is that component parameter specified with variables rather than numbers can-
not be used for yield analysis. This was one of the reasons why the simulation platform was
split up in two project files, budget and time domain.
Since the project aimed to examine the possibilities to use VSS as a simulation tool for
RF design that could be more user friendly than previous versions, how well the results are
depends not only on the accuracy of the simulations but on the simulation times and the us-
ability of the system. In regards to the accuracy and usability, the platform performs very
well. However the simulation times varies with what version of the implemented gain cali-
49
5.2. Method
bration systems and AGC is being used. This is however the reason there are two version of
each implemented, in order to give options for the designer when performing simulations on
the receiver.
5.2 Method
Part of the process in designing this simulation platforms was the testing of different solutions
to various problems. The methodology was in many regards learning by doing what worked
best in VSS. Some solutions proved more suitable than others in regards to user friendliness
and simulation times. For example, three different AGC implementation methods and two
different gain calibration methods were tested and evaluated.
Compromises and decisions

It became apparent early in the project, that the scope of the project would become too big
if the project would include the TX-part of the radio link as first planed. This caused us to
change the project thesis and some of the research questions and focus more on RX. Because
of the narrowing of the scope, more details in the RX-link were possible without making the
project to big. This shifted the scope slightly, more in the direction of time-domain simula-
tions and higher accuracy in the results.
One of the first decisions made after some time of testing and implementing was that a
fully functional delta-sigma ADC would be more a burden than an asset. We tried different
simple ADC:s and a fully functional feedback 1:st and 2:nd order delta-sigma. We got it
to work, but implementing it with the different ADC impairments, would at best slow the
simulation down into non-usability due to the feedback nature of the ADC. The compromise
made was instead to solve the problem by implement a zero-gain amplifier block with the
ADC’s IP3, P1dB, NF and temperature dependency parameters. Using an amplifier block as
an ADC model is a rough estimation of reality as it does not replicate the behavior of a real
delta-sigma ADC.
A decision regarding the layout of the simulation was reached to split up into two parts;
budget and time domain. At first, the two simulation types were in the same project doc-
ument but as the complexity of the two simulations increased, they were split up in two
project files. The main advantage of the budget simulations are their fast simulation times.
When the time domain simulation grew in complexity, the budget simulation times became
affected due to it having to wait with the next step in the sweep for the time domain to finish
up. More over, since the yield analysis tool built into VSS is only viable in budget simulations
and require the component parameters not specified as variables. This would mean that if
they were to be used in the same document, the user would need to enable and disable a lot
of measurements when doing each new simulation. There would also need to be double sets
of component parameters to change in two different ways. The decision was then made to
separate the simulation types into two documents. Even though two simulation documents
would be an inconvenience, it would be a bigger inconvenience to try to fit everything into a
single document.
AGC functionality was implemented in three versions, with one of them being used in
the end. The first version of the AGC tested was a very simple AGC with four manually
controlled VGAs. This has the advantage of not slowing the simulation down since AGC
state is set manually before simulation run time. The disadvantage however is that it does
not have threshold or hysteresis values and by being ON or OFF at the very start of each
simulation, this AGC does not react dynamically to the signals or distortions propagating
through the system. This makes this version of the AGC to simple and a different version is
needed.
The next version of the AGC tested was a full time domain feedback AGC that measures
the power of the system at the ADC input and triggered any one of the four VGAs. This
50
5.3. Improvements
version contains all the functionality and behaviour needed. However, it is a complicated
system to understand, and most importantly of all, the simulation times become far too long
for any simulations to be practical for a designer as shown in Table. 4.2.
The third and final solution to the AGC problem was the equation based system that
was described in Section 3.3. This version had good performance but lacked hysteresis and
was also relatively easy to use and fast to simulate. The issue with this version of AGC
implementation is that it assumes linear behavior over the full dynamic range of the system.
As input signal strength increases, the system goes into compression and this affects linearity.
This aspect is not taken into account. This version was finally implemented in both projects.
The implementation of the gain calibration was also iterated upon in three steps. The
simplest model implemented was a VGA with a look up table that compensated for the tem-
perature dependent gain shift. The implementation of this version was however not accurate
and flexible enough to make it to the final version.
There were two different solutions implemented after the look up table. These two are
described in Section 3.3. The PID controlled gain calibration system is used in the budget
platform since the VSS PID block instantly goes to a steady state, which is needed for budget
simulations, since they assumes state and only simulates on the boundary condition of the
system. this version is therefore not appropriate for time domain simulations. It is also not
possible to do gain calibration in steps of i.e., 0.1 dB which is desirable to model real system
behavior. For the Time domain platform, the most "real-life" accurate version of the gain
calibration is used. This version is viable because of the VSS function Round( X1 , X2 ) that
enables the gain compensation step size. Both versions work well in their respective platform.
It would be preferable to use the same version in both platform for ease of use and consequent
designing.
5.3 Improvements
Since this simulation platform is brand new, it will act as a demonstration concept for what
a VSS can do in terms of budget simulations. This platform can be iterated and built upon
to achieve new functionality not present current tools. Some of these new improvements
might even lead to new ways of looking at the radio systems and how to approach the design
process of new radio links.
Right now, the resulting simulation platforms have modeled frequency dependency only
with the help S-Parameter filter models and their effect on signals. Frequency dependency
however is an intrinsic part of each and every component, including traces and lines. This
could be modeled with the built in frequency dependency parameters in each blocks. Even
adding S-parameter blocks after the amplifiers and normalizing their gain would greatly in-
crease the accuracy of the AGC. This however could give a higher entry level for usage and
make the gain harder and more time consuming to change if necessary.
While on the subject of the AGC, a more accurate time domain model of the AGC could
be implemented if VSS started supporting that functionality natively.
As of the latest version of the VSS platform, the temperature dependency of the system
is modeled with linear interpolation between two temperature points. This however is not
necessarily accurate for all components and even so, the implementation of the temperature
dependency could be different. The linear interpolation could for example be implemented
using more than two points, to more accurately replicate temperature dependency in real
components.
An improvement to the digital part of the lineup is the addition of more signal types. It
is for example possible to add decimation filters for all LTE-channels of interest instead of
the three general channel bandwidths as seen in this report in Fig. 4.21, Fig. 4.22 and Fig.
4.23. The way filters are handled in the current version of the digital interface could also be
51
5.3. Improvements
improved with more accurate models of the filters. This would increase the accuracy of the
results even further.
In the current version of the project, the ADC at the end of the analog lineup is only
represented as a zero gain amplifier block with noise, IP3, and P1dB impairments. This is
however only the tip of the iceberg when it comes to the types of ADC impairments affecting
an RF receiver, such as jitter due to the sampling clock signal. As mentioned in chapter:
5.2 under compromises and decisions, the implemented delta-sigma ADC was too slow to use,
however with another method of implementation, a more complex ADC could perhaps be
put into place, that more accurately exhibits the true characteristics of an ADC.
52
6 Conclusion
In this project, the possibility of implementation of a simulation platform for radio receiver
development with focus on budget link evaluation was firstly investigated. The commercial
AWR Design Environment with Visual System Simulator (VSS) were chosen to implement
the simulation platform, mainly due the fact that AWR allows customization of codes accord-
ing to company requirements and specifications. The work included modeling of a receiver
lineup with necessary functionalities so that that it would be a powerful tool to design com-
plex systems such as modern receivers. In contrast to the existing simulation platform, the
new one should offer more opportunities to visualize the simulation results concerning differ-
ent receiver impairments while being able to perform complex frequency- and time domain
simulations. The main idea was to utilize as many as possible of the built-in functions in VSS
to create a more user-friendly experience for the radio designers than the current existing
simulation platforms provide, without compromises in complexity and accuracy.
It was shown that the VSS-environment offers the possibilities to create simulation plat-
forms that are easy to understand and work with. Moreover, the VSS and the developed
simulation platform provided the grade of adaptability to the receiver architectures and to re-
ceiver specifications as the company has required. Compromises because of usability turned
out to be few. The functionalities that were not natively supported by AWR VSS, were still
possible to be implemented via a VBA scripting editor that is featured in the AWR envi-
ronment. Making changes to this is not as intuitive as making changes in the VSS system
diagrams, but a user performing simulations in the developed platform it is not required to
make changes to that part of the system in order to perform simulations, once the scripts
were implemented. Some problems were encountered in how the time-domain simulations
affected the budget simulation run times when parameter sweep were performed. This lead
to the decision to split the platform into two separate files that had different strengths and
weaknesses e.g., a lack of yield analysis in time-domain and simpler input signals in the bud-
get file.
Finally, the project clearly demonstrates the strengths of using a simulation environment
such as VSS when designing radio systems. It can provide fast, reliable receiver model imple-
mentation and receiver simulations. Also, it was shown that using VSS and its customization
features, actual receiver specification in terms of receiver architectures, receiver characteris-
tics and individual block specifications can be modelled and simulations can be performed in
an practical way with short run times while simulation results can be graphically presented
53
and hence they can be easily interpreted. The developed receiver model has included the re-
ceiver front-end, from the antenna to the ADC, including the AGC, gain calibration VGA and
down-converter as well as elements after the ADC such as digital gain correction and three
of the filter branches present in the digital signal processing unit of the modeled receiver.
54
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LiU-ITN-TEK-A--19/051--SE

Construction of RF-link budget

Department of Science and Technology Institutionen för teknik och naturvetenskap

Construction of RF-link budget

Handledare Anna Lombardi

Detta dokument hålls tillgängligt på Internet – eller dess framtida ersättare –

© David Frykskog, Hjalmar Jonsson

RF Radio Frequency FIR Finite Impulse Response

Functionality and parameters

IQ modulator and demodulator

• PLL including reference clock

Filters, channel filters

Blockers and interfering signals

• Ripple estimation and handling

1.3 Research questions

• What compromises needs to be made when implementing the different functionalities?

1.5 State of the art

A simple example of a noise source is a resistor of value R in an environment with tem-

2.2 Non linearity in RF devices

so = a0 + a1 si + a2 s2i + a3 s3i ..., (2.5)

so = a0 + a1 V0 cos(ω0 t) + a2 V02 cos2 (ω0 t) + a3 V03 cos3 (ω0 t) + ...,

mω1 + nω2 (2.8)

Third-Order Interception Point

Degradation[dB] = [ POUT+ I NT ´ G+ I NT ] ´ [ POUT ´ G ] (2.11)

2.5 Analog circuits in RF receivers

Low Noise Amplifier

Variable Gain Amplifier and Programmable Gain Amplifier

VLO (t) = cos(ω LO t) (2.13)

VIF (t) = cos(ω IF t) (2.14)

2.6 Process variations

S(t) = Acos(ωt + φ) (2.17)

2.8 I/Q Data

cos( x + y) = cos( x )cos(y) ´ sin( x )sin(y) (2.18)

S(t) = Acos(ω0 t + φ(t)) (2.19)

Figure 2.4: Left: QPSK, Right: 64-QAM. Simulated in VSS

2.9 Receiver architectures

General receiver architecture

Figure 2.5: Superheterodyne receiver architecture [13]

Figure 2.6: Superheterodyne receiver architecture with I and Q data [13]

Figure 2.7: Homodyne receiver architecture [13]

Figure 2.8: Homodyne receiver architecture with I and Q data [13]

2.10 Digital Signal Processing

Figure 2.11: Transposed direct form FIR filter [2]

3.1 NI AWR Design Environment

Visual System Simulator

3.2 Receiver impairments

• Non-linearity: compression, intermodulation, spectral regrowth

• LO-leakage: self-mixing, M x N harmonics

• Noise figure, not optimized: sensitivity, SNR at the output

• Temperature effects etc.

3.3 Receiver model implementation

• First-hand estimation of the component characteristics that are in parameter form,(gain,

• Budget simulation on top-level, e.g., on receiver level

• If specification not met, modify/optimize some components parameters and conduct

Figure 3.1: Basic homodyne receiver lineup

Figure 3.2: Homodyne receiver lineup with features

Figure 3.4: Process variation as specified in the Time Domain platform

Table 3.1: LO phase noise text file format

Figure 3.6: LO phase noise

Figure 3.7: M x X text file as implemented in in the VSS mixer block

Figure 3.8: Gain calibration implementation using equations

Figure 3.9: Gain calibration implementation using PID controller

Receiver AGC models