Resume 2023/05/10 Now

English Name: Benson

Chinese Name: Junbo Chu

Birth Day: 1979/09/03 Male

Email： 527004076@qq.com TEL

Location: Chengdu City, Sichuan Province, China 86−18030410356

Year Month Degree・ Work experience

Degree

Changchun City, Jilin Province, China Changchun

1999 ９ University of Science and Technology Automation

Specialty. Admission

2003 ７ Graduate (Bachelor)

Mianyang City Sichuan Province China Southwest

2005 ９ Institute of Automation, Major in computer application

technology. Admission
2008 ７ Graduate (Master)

Above

Work experience

Chengdu City Sichuan Province China, MAIPU

2003 7 Communication Technology Co., Ltd, Hardware

Development Engineer, Onboarding

Main work： Schematic design, PCB design and

circuit debugging

Chengdu City Sichuan Province China, MAIPU

2005 8 Communication Technology Co., Ltd, Hardware

Development Engineer, Demission

Chengdu City Sichuan Province China, Digital Video

2008 7 Micro Technology Ltd, FPGA design engineer,

Onboarding

Main work： F H264/H264 encode and decode RTL

design, simulation, debugging, and verification work

based on XILINX FPGA platform, using modelsim,

vivado, ise, NCverilog etc.

Main work： Long-wave infrared imaging hardware

scheme design, image acquisition, image

 enhancement, display RTL design, simulation,

debugging and verification work based on Intel FPGA

platform

Chengdu City Sichuan Province China, Digital Video

2016 7 Micro Technology Ltd, FPGA design senior engineer,

Demission

Chengdu City Sichuan Province China,SAIDI

2016 8 Information Technology Corporation Limited. FPGA

design senior engineer, Onboarding

Main work： FPGA based on related imaging product

development design, simulation, verification and

debug

Mainly involved: XILINX 7 series FPGA design and

develop, MATLAB simulation, Digital signal

processing， Image processing(up and down Scaler,

image enhancement, Target identification and

tracking , Image distortion correction， Fogging and

defogging， picture in picture， image filter， image

edge enhancement， motion target detection)， High-

speed signal (SerDes， DDR， PCIE, AURORA , SRIO,

 LVDS, MIPI , SATA controller etc） , AMBA， AXI4, SOC

base on zynq FPGA , Video input and output interface,

Cameralink , CML, SDI, HDMI, DVI, VGA , PAL/NTSC,

Above

Year Month Certification

2023 10 TOEIC Tests Preparing

Japanese-Language Proficiency Test N2 （ 2 Level ）

2023 7
Preparing

Chengdu City Sichuan Province China, Senior engineer ,

2023 7
preparing

Chinese invention patent, Patent number

2022 10
ZL202210983908.3 Got

Chinese invention patent, Patent number

2022 10
ZL202210930958.5 Got

Chinese invention patent, Patent number

2022 11
ZL202211250273.2 Got

2008 3 IELTS（ 5.5） Got

Above

Time About 1 hour

Married Married

Children 2

Interests

Interests : Swimming, Playing Ping-Pong, Playing badminton

Specialty ： Sports

Hobby ： Photography

Above

Motivation and attraction points

I have nearly 10 years of experience in customer demand analysis,

hardware schematic design, FPGA functional design, product deliver y,

and team management. I would like to apply because I want to contribute

to the further growth of your company by utilizing the knowledge and

experience I have got so far.

With 15 years of FPGA design experience, I have the flexibility to meet

the challenges of new technologies. I has extensive experience in image

product design， related product design and development using Xilinx

FPGAs. Years of work experience allow me to analyze problems, solve

them and collaborate in a team.

 I can read, write and communicate in English.

I am studying hard to achieve my goal of better integrating into the

company and residing in Japan with my wife and two children. When I am

hired by your company, I will demonstrate my expertise and do my best

to develop for the company.

Above

Personal preference

Annual salar y ： Negotiate。

Job ： FPGA Design development and related。

Place of work ： US, Canada, Europe, Canada, Japan, Singapore, HK,

Australia 。

Accommodation ： Hope to provide a single dormitor y。

Above