CADENCE DESIGN SYSTEM, INC

Introduction to Low Power concepts &

verification
A Beginner s Guide
This document describes a brief detail on low power
verification, different techniques used and key components of
low power verification.

Author
Manash Ranjan Raiguru

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

©2019 Cadence Design Systems, Inc. All rights reserved.

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 1. 4

2. 4

3. Introduction to CMOS 5

4. What are power reduction techniques. 8

5. Introduction to Power Shutoff (PSO)... 13

6. Introduction to Low Power Verification 21

7. Useful links 24

8. 25

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

This application note explains the basics of Low Power verification. What are CMOS power
dissipation, different techniques to reduce power dissipations, and detailed description of power
shutoff techniques which is most commonly used low power methodology. This documents also
includes pointers to how you can use a power format file (CPF or 1801/UPF) to do your low
power verification using Xcelium simulator.

This document is aimed at verification engineers who are new to Low Power flow and running
Low Power simulations for the first time using any power format either CPF or 1801/UPF and
also for beginners to understand Low Power methodologies better.

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

Every device need power to operate properly. Based on the type of device and technology node
the amount of power it consumes may vary. With the increase in complexity of modern designs
and requirement of minimal area in the silicon, it is a necessity to use lower node CMOS devices
at the same time reduce overall power consumption.

In a CMOS device the total power consumed can be categorized as

a. Dynamic Power
b. Static Power
c. Short Circuit power

So Total Power = Dynamic Power + Static Power + Short Circuit Power

Dynamic power can be termed as sum of switching power and short circuit power. And Static
power is due to leakage in the circuit. So, discuss more on what are these dynamic and
leakage powers are in detail.

Total power is a function of switching activity, capacitance, voltage, and the transistor structure
itself.

This is a basic representation of a MOSFET inverter.

As all static CMOS logic gates are based on stacks of complementary PMOS and NMOS, you
can scale the total power dissipation equations to gates larger than the inverter.
For CMOS systems-on-chip (SoC), leakage power exceeds dynamic power at lower node
technologies.

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

Dynamic power is the sum of two factors: switching power plus short-circuit power.
Switching power is dissipated when charging or discharging internal and net
capacitances.
Short-circuit power is the power dissipated by an instantaneous short-circuit connection
between the supply voltage and the ground at the time the gate switches state.

Pswitching = a.f.Ceff.Vdd2
Where a = switching activity, f = switching frequency, C eff = the effective capacitance and Vdd =
the supply voltage.

Pshort-circuit = Isc.Vdd.f
Where Isc = the short-circuit current during switching, Vdd = the supply voltage and f = switching
frequency.

Dynamic power can be lowered by reducing switching activity and clock frequency, which
affects performance; and, by reducing capacitance and supply voltage. Dynamic power can also
be reduced by cell selection-faster slew cells consume less dynamic power.

Switching activity: The switching activity factor is the probability that an output switches
during a clock cycle. The output of a two-input AND gate switches for 6 of 16 possible
input transitions. For a microprocessor, signals inside instruction RAMs may switch
every 2 cycles, while those inside data RAMs may switch only once in 4 cycles.
Switching probabilities tend to increase as the need for bandwidth increases and
-sharing techniques to save on area.
Capacitance: Technology scaling produces smaller transistors and hence less transistor
capacitance, but also packs more transistors on a chip. Interconnect capacitance does not
scale with the process. More transistors mean more interconnect capacitance.
Interconnect capacitance has become the dominant capacitance component.
Supply voltage: Dynamic power increases quadratically with supply voltage.
Switching frequency: Dynamic power increases linearly with switching frequency.

Leakage power is a function of the supply voltage Vdd, the switching threshold voltage Vth, and
the transistor size.

PLeakage = f (Vdd, Vth, W/L)

Where Vdd = the supply voltage, Vth = the threshold voltage, W = the transistor width and L = the
transistor length.

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

Of the following leakage components, sub-threshold leakage is dominant.
I1: Diode reverse bias current
I2: Sub-threshold current
I3: Gate-induced drain leakage
I4: Gate oxide leakage

Several currents qualify as leakage currents. Process size affects their relative magnitude.
Junction leakage occurs from the source or drain to the substrate when the transistor is
off. This leakage increases with doping density and especially with temperature. At
commercial temperatures it is much smaller than the other leakage currents.
Gate-induced drain leakage occurs from the drain to substrate. This leakage increases
with drain to body and drain to gate voltage, and as gate oxide becomes thinner.
Gate direct tunneling leakage occurs through gate oxide insulator due to quantum-
mechanical tunneling when the transistor is on. This leakage increases exponentially as
supply voltage increases and as gate oxide becomes thinner. Using silicon dioxide
insulator, at 65 nm and below technologies, gate leakage exceeds sub-threshold leakage.
Subthreshold leakage occurs from drain to source when the transistor is off. This leakage
increases linearly with W/L and rapidly in a complex but basically exponential way with
decreasing threshold voltage, mainly due to decreasing process size. Between 130 nm and
65 nm technologies, subthreshold leakage is the largest contributor to leakage power.

While dynamic power is dissipated only when switching, leakage power due to leakage current is
continuous.

As voltages scale downward with technology, threshold voltages must also decrease to gain the
performance advantages of the new technology.
Reduction in threshold voltage causes an exponential increase in subthreshold leakage
Major contributor to leakage between 130 nm and 65 nm technologies
Thinner gate oxide causes an increase in gate direct-tunneling leakage
Exceeds subthreshold leakage at 65 nm and below technologies
Drives search for better dielectrics

Now that we know what the types of power dissipation are, so let us see what are different power
reduction techniques and what is the need of the same.

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

So, power dissipation can be broadly classified as Dynamic Power and Leakage Power.

Ptotal = Pdynamic + Pleakage

Where:
a. Pdynamic - power related to active/switching behavior
b. Pleakage power related to electrons leaking into substrate

4.1 Reducing Dynamic Power dissipation

The fundamental equation for representing the dynamic power is:

Pdynamic = a CV²f
Where:
a = Switching activity (average transitions per clock cycle)
C = Capacitance to charge or discharge a transition
V = The voltage of the device
f = Frequency

To reduce dynamic power, reduce:

activity
capacitance
voltage
frequency

Given Pdynamic = a CV²f, to dissipate Pdynamic

Affect a variable Switching
Clock Gating
Operand Isolation
Affecting V and/or f variables
Multi-Supply Voltage (MSV)
Dynamic Voltage and Frequency Scaling (DVFS)

4.1.1 Clock Gating

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 The clock may be shut off to the registers using a gating circuit, which prevents the clock
from triggering the registers.
The clock gating can result in 30% to 40% of the power savings compared to design
without clock gating

The below diagram explains a basic clock gating technique.

4.1.2 Operand Isolation

Gate the inputs to inactive combinational logic to prevent output transitions.

For ex.

4.1.3 Multi Supply Voltage

Use different voltages for different domain.

In this technique as power is affected by square of voltage so, it can have large impact on power

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

But there are some Con associated with this.
It may require using some special library cell (e.g. level shifter)
It may impact the performance/speed. Lower voltage areas have slower switching

4.1.4 Dynamic Voltage/Frequency Scaling (DVFS)

Reduce power in the chip by scaling down the voltage and frequency under acceptable
conditions
Requirements for DVFS include:
1. A variable power supply capable of generating the required voltage levels with minimal
transition energy losses and a quick voltage transient response
2. A power scheduler that can intelligently compute the appropriate voltage and frequency
levels needed to execute the various applications (tasks or jobs)
3. Hardware to scale frequency in proportion to voltage to accommodate additional
propagation delay

Challenges:
Complicated to implement due to several component considerations such as appropriate
V/f values
Expensive to implement
Clock scheduling issues due to dynamic latency changes

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

4.2 Reducing Leakage Power dissipation

Leakage power is a function of three

variables:
Pleakage = f (Vt, W/L, Vdd)
Where:
Vt = The threshold voltage
W/L = The channel sizing factor
Vdd = The supply voltage of the device

To reduce leakage power:

raise threshold voltage
choose lower size factor
lower or turn off power supply

Given Pleakage = f (Vt, W/L, Vdd), to dissipate Pleakage

Affect Vt variable
Use Multiple Vt cells
Affect Vdd
Power Shutoff (PSO)

4.2.1 Reducing Leakage Power by Multi-Vt Optimization

This technique comes with the dependency on using special types library cells broadly classified
as,
HVT (High Threshold voltage cell or High Vt)
MVT (Medium Threshold voltage cell or medium Vt)
LVT (Low Threshold voltage cell or Low Vt)

Using HVT: High threshold voltage cells (high Vt)

1. Lower leakage
2. Lower sensitivity
3. Lower driving current
4. Lower speed
This can achieve up to 90% leakage reduction with 70% speed reduction.

Using MVT: Medium threshold voltage cells (medium Vt)

1. Trade-off between LVT and HVT

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Using LVT: Low threshold voltage cells (low Vt)
1. Higher leakage
2. Higher sensitivity
3. Higher driving current
4. Higher speed

4.2.2 Reducing Leakage Power by Power Shutoff

Power shutoff is the most effective and efficient way to prevent leakage:
Benefits include relative independence from Vt considerations
Opportunities for challenging solutions include:
Additional power control circuitry
Additional power and control routing
Additional cell library models for state retention/restoration
Increase in area, clock and signal delay, active power consumption
Changes in logical and physical verification

4.2.3 Summary of Power Reduction Techniques

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

Power Shutoff (PSO), also called power gating, is one of the most effective power
management techniques for reducing power. In PSO, selected functional blocks of the chip
are individually powered down when they are not in use to save leakage and dynamic
power.
Logic blocks (hierarchical instances), leaf instances, and pins that use the same main power
supply and that can be simultaneously switched on or off are said to belong to the same
power domain.

Few of the common terminology that we will see in later part are as follows,

Power Domain/Voltage Domain

Isolation Cell
Level Shifter cell
Retention Cell (SRPG)
Power switch cell

5.1 Power Domain/Voltage Domain

A power domain is a collection of instances, pins, and ports that share the same power
distribution network and that either can be simultaneously switched on or off or treated as always
on.
All logic with equal power supply voltage values are considered a voltage domain.
A voltage domain can have multiple power domains, but the reverse is not possible.

Logic blocks (hierarchical instances), leaf instances, and pins that use the same main power
supply and that can be simultaneously switched on or off are said to belong to the same power
domain. The example design in above Figure has three power domains:

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

 The top-level of the design, top, and hierarchical instances, inst_C and pm_inst, are
always switched on: They belong to power domain PD1.
Hierarchical instances inst_A and inst_B are always switched on and off simultaneously:
They belong to power domain PD2.
Hierarchical instance inst_D can be switched on and off independently from hierarchical
instances inst_A and inst_B: It belongs to power domain PD3.
When a power domain is powered down, all signals and wires within the shutdown region
transition to the unknown state. All sequential elements (registers) and variables within the
powered-down region lose their state and are forced to the logic value X for the entire shutoff
period. This behavior is referred to as state loss or corruption.

5.2 Retention Cell (SRPG)

When a power domain is powered down, the states of certain sequential elements in the power
domain (latches, flip-flops) must be saved and retained for the entire shutoff period. When the
power domain is powered back up, the saved states must be written back into the elements. To
ensure that a powered-down block resumes normal operation after power up, these sequential
elements can be replaced by special state retention cells.

Depending on how the retained value is stored and retrieved/restored , there are at least two
flavors of retention registers, as follows:

1. Balloon-style retention: In a balloon-style retention register, the retained value is held in

an additional latch, often called the balloon latch. In this case, the balloon element is not
in the functional data-path of the register.
2. Master/slave-alive retention: In a master/slave-alive retention register, the retained
value is held in the master or slave latch. In this case, the retention element is in the
functional data-path of the register.

Ballon-style retention can be Dual-Pin Retention cell or Single-Pin Retention cell.

Master/slave-alive retention is same as Zero-Pin Retention cell.

Dual-Pin Retention:
Dual-Pin Retention is the one which has two separate control signals for save and restore
operation. Save/Restore operation can be level-sensitive or edge-sensitive.

Single-Pin Retention:
Single-Pin Retention is the one which has single control signal for both save and restore
operation. Save/Restore operation can be level-sensitive or edge-sensitive.
Save operation and Restore operation will be on opposite level/edge of control signal. i.e If save
is performed on level high than restore will be performed on level low of control signal.

Zero-Pin Retention:
Zero-Pin Retention is the one which does not have any control signal.
Save operation will be performed when the power domain in which cell is sitting goes from
NORMAL to CORRUPT state. Restore operation will be performed when the power domain in
which cell is sitting goes from CORRUPT to NORMAL state.

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

The basic flip-flop has been modified in SRPG, and the master latch runs on the same power
supply Vdd as combinational logic, while the slave latch runs on the different power supply Vcc.
The state of the system will be retained in the flip-flops during power down and all the
combinational logic will be turned off during sleep mode.

State retention registers require two types of power supplies: a switchable power supply and an
always-on power supply. This introduces some complications and penalties in power routing
area requirements. The physical designer, or implementation tool, must allocate extra area to
accommodate this additional power routing.

The advantages of SRPG include shutdown leakage savings, which can be independent of
process variations. It allows for faster system power-on because the state is preserved in the slave
latch.

Disadvantages include increased area and die size; timing penalties such as increased signal and
clocking delays; increased routing resources (power routing for Vcc and a power-gating signal
tree with on buffers); specialized library models for SRPG cells; additional power overhead in
the active mode; and impacts to functional verification, physical integration, and DFT etc.

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

 5.3 Isolation

A power domain is usually connected to other power domains. When a domain is powered
down, isolation logic must be added between domains to prevent the propagation of unknown
states from a power domain that is powered down to a power domain that remains on.

In other words, two power domains interact with each other and if one contains logic that is the
driver of a net and the other contains logic that is a receiver of the same net. When both power

unambiguous 1 or 0 value, except for a very short time when the value is in transition. The
structure of CMOS logic typically ensures that minimal current flow will occur when the input
value to a gate is a 1 or 0.

However, if the driving logic is powered down, the input to the receiving logic may float
between 1 or 0. This can cause significant current to flow through the receiving logic, which can
damage the circuit. An undriven input can also cause functional problems if it floats to an
unintended logic value.

To avoid this problem, isolation cells are inserted at the boundary of a power domain to ensure
that receiving logic always sees an unambiguous 1 or 0 value. Isolation may be inserted for an
input or for an output of the power domain.

An isolation cell operates in two modes: normal mode, in which it acts like a buffer, and
isolation mode, in which it clamps its output to a defined value. An isolation enable signal
determines the operational mode of an isolation cell at any given time.

Depending upon the need of user, there are mainly three types of isolation cells.

1. Isolation cell with clamp_value 1:

This type of Isolation cells will have function such that it will have o/p of logic 1 , when it is in
isolation mode. And when it is in non-isolation mode it will act as buffer i.e simply pass the data
to o/p. This is similar to OR gate.

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

 2. Isolation cell with clamp_value 0:
This type of Isolation cells will have function such that it will have o/p of logic 0 , when it is in
isolation mode. And when it is in non-isolation mode it will act as buffer i.e simply pass the data
to o/p.This is similar to AND gate.
3. Latch type Isolation cell:
This type of Isolation cells will have function such that it will latch the o/p of isolated port when
it is in isolation mode. And when it is in non-isolation mode it will act as buffer i.e simply pass
the data to o/p.This is similar to Latch.

Isolation cells are placed as close to the power shut-off domain as possible, but usually reside in
the always-on domain.

Common problems that may occur while inserting isolation cells include placing the isolation
cells in the wrong power domain or hooking up the isolation power supply to the switchable
power supply instead of the always-on power supply. These are catastrophic issues!

5.4 Level Shifters

Multi-supply voltage techniques require level shifters on signals that go from one voltage level to
another. Without level shifters, signals that cross-voltage levels will not be sampled correctly.
Two interacting power domains may also be operating with different voltage ranges. In this case,
a logic 1 value might be represented in the driving domain using a voltage that would not be an
unambiguous 1 in the receiving domain. i.e receiving domain might treat it as 0 due to high
operating voltage.

Level-Shifters are inserted at a domain boundary to translate from a lower to a higher voltage
range, and sometimes from a higher to a lower voltage range as well. The translation ensures the
logic value sent by the driving logic in one domain is correctly received by the receiving logic in
the other domain.

Level-Shifter cells are functionally like Buffer cell.

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Level shifters are added to ensure that blocks operating at different voltages will operate
correctly when integrated together in the SoC. Level shifters must ensure the proper drive
strength and accurate timing as signals transition from one voltage level to another. Level
shifters can be inserted during the synthesis or implementation stage.

Every signal that crosses an MSV power domain should have a level shifter attached to it.
Although level shifting from a higher-voltage power domain to a lower one is usually optional,
level shifting from a lower-voltage power domain to a higher one is mandatory.

Level shifters are placed close to the power domain boundaries. However, level shifters have two
power rails:
Primary power rail: usually set at the top and bottom edge of the level shifter
Secondary power rail: usually set at the center horizontal line of the level shifter

The power domain where the level shifter resides depends on which voltage the primary power
rail matches. For example, if the primary power rail of the level shifter is a 0.8V rail, that level
shifter should be placed in the 0.8V power domain. Therefore, some knowledge about the library
is needed to decide in which power domain to place the level shifter.

Using low-power level-shifting cells can have a significant impact on timing and physical
design.

Types of Level-Shifter Cells:

1. HL: High to Low type of LS cell is required when source domain is operating at high
voltage and sink domain is working at low voltage in any specific state of PST (Power-
State Table).

2. LH: Low to High type of LS cell is required when source domain is operating at low
voltage and sink domain is working at high voltage in any specific state of PST(Power-
State Table).

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

 3. HL_LH: This is the type of LS cell which will serve both purpose i.e it can convert signal
voltage from low to high and vice versa. This type of cell is mainly required when in 1
PST state source domain is operating at high voltage and sink domain is working at low
voltage while in another PST state source domain is operating at low voltage and sink
domain is working at high voltage.

Enable-Level Shifter cells often termed as ELS cells, are cells which has the functionality of both
Isolation and Level-shifter cells. In general, this will serve the purpose of both isolation and
level-shifting in Power-Aware designs.
This will have the advantage that it will occupy less area compared to separate isolation and
level-shifter cell.

5.5 Power Switches

Insertion of power switch cells is a necessity for on-chip power shut-off. Power switch cells can
be inserted in a column or a ring fashion.

physical characteristics. Generally, the larger the PSO power domain area, and the more logic
and macros in the PSO power domain area, the more power switches are needed.

The goal is to have the true optimal number of power switches to satisfy IR drop and current
density requirements. Too many power switches lead to wasted area, but too few power switches
create excessive IR drop and risks having too much current (rush current) going through each
power switch during wakeup.

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

Some power switches have built-in buffers/delays that accomplish two things: first, they control
the skew of the enable signal of the power switch; and second, they introduce a delay when the
enable signal traverses the power switch array.

It may be desirable to introduce a delay, because turning on the PSO power domain causes a
large current to be drawn by the domain, causing a current spike or rush current. Introducing a
delay between the times when each power switch turns on will spread out the turn-on time of the
PSO domain, thereby reducing the current spike. Another method for reducing the current spike
is to turn on the power within the domain in stages over time.

It is also desirable to design the power switches in groups of cells and turn them on and off one
group at a time. This way, the last group of power switches at the end of the shut-off sequence,
or the first group of power switches at the beginning of the power-on sequence, will handle the
large current instead of a single power switch.

In many designs, switches are -

switches have multiple enable pins; typically, the smaller switch is turned on first to get the
voltage up to 95 percent, then the bigger switch is turned on to reduce the IR drop.

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

In low-power verification, the focus is on ensuring that the design is electrically correct from a
low-power perspective. The flow will verify that the retention and isolation are complete and
correct as specified by the power intent.
Checks at this stage include tests for missing isolation or level shifter cells, checks that state
retention and isolation control signals are driven correctly by domains that remain powered up,
and tests for power control functionality. In later stages of the flow (post placement), these
checks also ensure that gate power pins are hooked to the appropriate power rails, that the
always- -down
domains back to logic.

Power-aware verification methodology can help verify power optimization without impacting
design intent, minimizing late-cycle errors and debugging cycles. After all, simulating without
power intent is like simulation with some RTL code black boxed.

The methodology brings together power-aware elaboration with formal analysis and simulation.
With power-aware elaboration, all the blocks as well as the power management features in the
design are in place, so we can verify our design with power intent. Power intent introduces
power/ground nets, voltage levels, power switches, isolation cells, and state retention registers.
Any verification technology simulation, emulation, prototyping, or formal can be applied on
a power-aware elaboration of the design.

How to capture the Power Intent (PI)?

The Power Format Initiative is an industry-wide effort to establish a single standard format for
specifying all power-specific design, constraint, and functionality requirements for a design and
capture all the power intent.
The two most popular power formats for capturing power intent are
1. Common Power Format (CPF)
2. Unified Power Format (UPF/1801)
CPF or UPF/1801 are used for MSV, PSO & DVFS. Clock gating and multi-VT do not use any
power intent. Also, clock gating and multi-VT by themselves do not provide enough power
reduction, hence PSO is the most favorable and used power reduction technique in the industry.

Detailed description of each power format type is out of scope of this document. To know more
browse through https://support.cadence.com

Steps in the Power-Aware Flow

1. Write and scrub the CPF or 1801/UPF power intent
2. Create a power-aware, power feature verification plan
3. Execute formal aspects of verification plan
4. Create dynamic tests for balance of verification plan
5. Execute dynamic tests on assigned engine.
6. Merge metrics coverage reporting
7. Normal cycle of debug/fix/regress (Repeat all tests if there are power-intent changes)

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The Xcelium simulation environment is used to verify that power intent as described in the
Common Power Format or Unified Power Format files is correctly implemented, including:
Logical netlist power domain reset, initialization, and control behavior
Physical netlists containing post place-and-route buffering and clock networks
IP interfaces and power domain interactions at the SoC level
Test structures such as BIST and scan chains that do not have an RTL equivalent
Anatomy of a Low Power Design

What needs Verification?

PI+ RTL Checks

Consistency of PI + RTL
Completeness of PI (CPF/UPF)
Isolation/level shifting Domains, modes, etc.
Power Control Module
Proper sequence and timing of domain control signals
Exercise all domain states

Simulation of power structures

Isolation
State retention
Level shifting
Power domain behavior
Ability to power on/off
State retention/restoration
Handle RAM/ROMs during shutoff/multiple voltages

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

 Interface to external and analog
System Level
HW/SW power management
Exercise all Legal power modes/states and
mode /state transitions
Verify system features in all relevant modes
System Power sequence
Effectiveness of power modes
System reset in all modes
Interaction of power domains
Proper isolation values
Critical signals between domains meet protocol
One domain shutoff does not affect other domains

Low Power Simulation Detects runtime issue. Such as,

Power control unit is designed or applied incorrectly

Incorrect power control sequences
Processes wait long periods (while blocking other task) or time out
Design environment attempted to access shutoff power domains
System buses lock, transaction stall, data is lost
Design logic is assigned to incorrect power domains
Power domain outputs are isolated to incorrect values
Design Fails to operate after power up
Design states are inadequately retained
Clock is improperly gated, isolated or retained
Reset is improperly or incompletely re-applied

Need for Static low power verification

Low power static verification checks help to verify correct implementation of low power design
techniques using formal techniques (versus simulation) early in the design process. These static
checks on RTL helps in finding the completeness of CPF or UPF upfront ensuring that CPF or
UPF contains all the isolation and level shifter rules for power and voltage domain crossings.
This would ensure that no low power cell is missed between two voltage or power domains.
Static verification adds value by identifying bugs which are otherwise very difficult and time
consuming to find in RTL simulations.

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

If you are using the power format CPF or UPF for the first time and wanted to run Low Power
Simulation using Xcelium Simulator, then here are the below links to our Rapid Adoption Kit
which will help you in kick start your journey towards becoming an Low Power Verification
Expert.

Introduction to CPF Low Power Simulation (RAK)

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od000000050YMEAY

A Brief Introduction to IEEE-1801 Low-Power Simulation (RAK)

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od000000050NOEAY

Conformal Low Power, Genus and Xcelium: Low Power Verification for Beginners
in 1801 (RAK)
https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od000000051qtEAA

User Guides of Different Power Formats:

Low-Power Simulation Guide (CPF)

https://support1.cadence.com/tech-
pubs/Docs/LowPowerCPF/LowPowerCPF19.03/LowPowerCPF.pdf

Low-Power Simulation Guide (IEEE 1801)

https://support1.cadence.com/tech-
pubs/Docs/LowPower1801/LowPower180119.03/LowPower1801.pdf

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

The above documents take you through a quick ride on basics of CMOS power dissipation,
power reduction techniques and a detailed description of Power Shutoff technique. It will help
you in understanding the basics of Low Power Verification before you start running low power
simulation for the first time. Having said that this document may not be enough, and it may not
cover many parts and aspects of Low Power Verification
https://support.cadence.com and search for more detail information about low Power Simulation,
about different power formats and related topics.

Now that you know Low Power Verification and have tamed it, Go and explore the world of
Low Power verification. not a mystery anymore. Is not it?

Support
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base, access to software updates for Cadence products, and the ability to interact with Cadence
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© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.