AIM:- Design of basic gates: AND,OR,NOT.

APPARATUS:- Synthesis tool used: Xilinx, Simulator used: VHDL.

THEORY:- AND:-The AND gate gives logical multiplication output. It has

two or more inputs and one output. Its output is low even if one input
is low. It is shown as: Y=A.B

OR:- OR gate performs logical addition. It has two or more inputs and
single output. Its output is high even if one input is high. It is shown as:
Y=A+B.

NOT:- NOT gate performs logical inversion. It is also called inverter. It

has one input and one output. It converts one logic level into opposite
logic level.

DOC:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;
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entity gate2 is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : out STD_LOGIC;

d : out STD_LOGIC;

e : out STD_LOGIC);

end gate2;

architecture Behavioral of gate2 is

begin

c<=a and b;

d<=a or b;

e<=not (a);

end Behavioral;

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SYNTAX:-

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SCHEMATIC RTL:-

WAVEFORM:-

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