Circuit 1: leakage current measurement

Make a new schematic “leakage”:

 Draw a single NMOS transistor with L=180nm and W=1.2um, just like in
assignment 1. Connect the source and bulk to ground. Connect a DC supply to
the drain and set its voltage to 1.8V (or a parameter Vdd). Connect a DC supply
to the gate and set its voltage to a parameter vgs

 Run a DC simulation and sweep the parameter vgs from 0 to 1.8V

 Measure the (subthreshold) current which is flowing into the drain of the
transistor. 

 Plot this current vs Vgs and show the y-axis in log scale.

 What is the current at Vgs=0? This is the leakage current of the transistor.

Vgs = 0 => Id = 14.1926pA

2) Change fq to 100MHz => period = 1e-8 s = 10ns (100 periods = 1us simulation)
(Period 1 ns => fq = 1e9 Hz = 1 GHz (1000Mhz) (simulation 100 ns = 100 periods))

Average current: 5.542E-6A; (average(IT("/M3/S")) in my case first PMOS is M3);

Vdd = 1.8V;

Dynamic power consumption: P = IV = 5.542E-6A * 1.8V = 9.976 uW;

W=J/s

J = W*s

Energy per cycle: E = PT= 9.976uW * 10 ns=9.946e-14J= 99.46 fJ