IEICE Electronics Express, Vol.18, No.
14, 1–5
LETTER
High-speed switching operation for a SiC CMOS and power module
Atsushi Yao1, a) , Mitsuo Okamoto1 , Fumiki Kato1 , Hiroshi Hozoji1 , Shinji Sato1 , Shinsuke Harada1 , and Hiroshi Sato1
Abstract This paper deals with the high-speed switching operation of
a main circuit when using a silicon carbide (SiC) complementary metal-
oxide semiconductor (CMOS) and power module for the high-speed drive.
When using the developed power module and SiC CMOS gate buffer, we
experimentally achieved the turn-on and turn-off switching speeds of about
−100 and 80 V/ns at a DC bus voltage of 600 V and a load current of 20
A. Based on the I -V characteristics of the developed SiC CMOS and the
gate charge of the SiC power MOSFET, the approximate switching time
was calculated.
Keywords: module, SiC CMOS, high-speed switching, wide-bandgap
power semiconductors, gate driver, SiC MOSFET
Classification: Power devices and circuits
1. Introduction
Wide-bandgap (WBG) power semiconductors such as sil-
icon carbide (SiC) and gallium nitride (GaN) have been
widely researched owing to their advantages of high with-
stand voltage, fast switching and high-frequency operation,
high-temperature tolerance, and low on-resistance [1, 2, 3,
4, 5, 6, 7, 8]. For instance, miniaturization and high output
power density of power converters can be achieved by the
high-frequency operation [1, 9, 10, 11]. For high-frequency
operation, it is important to reduce the switching time of
main circuits. To realize high-speed switching of the main
circuit, the gate capacitor of power devices should be quickly
charged and discharged [12]; in other words, a high-output-
current gate buffer is required and then the inductance be-
tween the gate buffer and power metal-oxide semiconductor
field-effect-transistor (MOSFET) should be low [13], and
the inductance of the main circuit should be reduced to sup-
press current and voltage surges [14, 15, 16]. In this study,
the main circuit inductance was reduced and a SiC comple-
mentary metal-oxide semiconductor (CMOS), which can be
operated at high-temperatures [17], and power SiC MOS-
FET were installed in the same module to shorten the gate
wire. Such a design cannot be achieved using a Si gate driver
owing to the effects of heat.
The recent SiC devices function as not only switching
elements of main circuits, but also various gate drive cir-
cuits [17, 18, 19]. In addition, several researchers focused
on SiC integrated circuits with CMOS designs [17, 20, 21,
22, 23, 24, 25]. Recently, M. Barlow et al. realized exper-
1 National Institute of Advanced Industrial Science and Technol-
ogy (AIST), 16-1 Onogawa, Tsukuba 305-8569, Japan
a) a.yao@aist.go.jp
DOI: 10.1587/elex.18.20210234
Received May 24, 2021
Accepted June 4, 2021
Publicized June 14, 2021
Copyedited July 25, 2021
Copyright © 2021 The Institute of Electronics, Information and Communication Engineers
imental turn-on and turn-off switching speeds of about 24
V/ns and −30 V/ns, respectively, at room temperature and a
DC bus voltage of 300 V using a SiC CMOS gate driver [17].
Our study explores the further faster switching of main cir-
cuits by using a power module for high-speed drive and SiC
CMOS gate buffer with large output current characteristics
of several amperes during the Miller plateau.
Modules for the high-speed switching of the SiC power
MOSFET in the main circuit has been studied recently [14,
15, 16]. In previous studies [15, 16], a Si gate driver was
placed outside the module and then the inductance of the
main circuit in the module was reduced to realize the high-
speed switching. Based on these studies [15, 16], in addition
to reducing the inductance of the gate wire, a way of reducing
the inductance of the main circuit in the module using the
developed SiC CMOS was explored.
This study focuses on a high-speed switching operation
of the SiC power MOSFET in the main circuit when using
a low-inductance module for the high-speed drive and the
SiC CMOS gate buffer. To quickly charge and discharge
the gate capacitor, the current required for SiC CMOS gate
buffer was estimated, and then the parallelized SiC CMOS
was developed to achieve a large output current of the SiC
CMOS. In addition, we developed a module that can in-
corporates both this SiC CMOS gate buffer and the power
MOSFET. In this module, the inductance of the main cir-
cuit in the module was reduced by connecting two substrates
together and by incorporating a snubber circuit within the
module [15, 16]. We experimentally examined the switch-
ing speed of the main circuit in a double-pulse-test when
using the developed module and SiC CMOS gate buffer. In
addition, the switching time was estimated by calculations
based on the gate (Qg ) charge of the SiC power MOSFET
and the I-V characteristics of the developed SiC CMOS.
2. Design, fabrication, and method
Figure 1(a) shows a schematic circuit of the system to mea-
sure the switching phenomenon. This circuit primarily con-
sists of the SiC power MOSFET of the main circuit and
the SiC CMOS-based final output transistor (gate buffer)
of the gate driver. To measure the current and the volt-
age in the double-pulse-test, a voltage probe (TPP0850,
Tektronix, Inc.), a Rogowski coil current probe (SS-284A,
Iwatsu Electric Co., Ltd.), and a digital phosphor oscillo-
scope (DPO5104, Tektronix, Inc.) were used. The induc-
tance L was 5 mH.
Figure 1(b) shows a photograph of the developed module.
This module consists of a SiC MOSFET (UMOS [26] of
1

Fig. 1 (a) Schematic of the setup for the switching test, (b) photograph
of the fabricated module for the high-speed drive; this module can reduce
the inductances of the main circuit and gate wire, (c) photograph of the
fabricated SiC CMOS gate buffer.
TPEC (Tsukuba Power Electronics Constellation), the block-
ing voltage is 1,200 V, the typical on-resistance is about 50
mΩ, the typical internal gate resistance Rgin is about 4 Ω,
and the die size is 3 × 3 mm2 ), a diode (TPEC, the block-
ing voltage is 1,200 V and the die size is 3 × 3 mm2 ), the
developed SiC CMOS, a decoupling capacitor Cd (100 nF,
C0805C104J5RACTU, KEMET Co.), and an internal snub-
ber circuit that has one resistor (1 Ω, WK73S2HTTE1R00F,
KOA Speer Electronics, Inc.) and one capacitor (10 nF,
CKG32KC0G3A103J335AJ, TDK Co.). In this module,
since the SiC CMOS gate buffer is installed inside the mod-
ule, the gate wire is shorter compared to the wire in the case
that the gate buffer is placed outside the module. In addition,
the inductance of the main circuit is reduced to realize the
high-speed switching of the SiC power MOSFET. This re-
duction is achieved by connecting two silicon-nitride active
metal-brazed (SiN-AMC) copper substrates together and by
incorporating a snubber circuit inside the module. In other
words, the inductance between P and N terminals shown in
Fig. 1 is reduced. See Refs. [15, 16] for details of the module
IEICE Electronics Express, Vol.18, No.14, 1–5
Fig. 2 Typical gate charge waveform for the UMOS at 600 V and 20 A.
containing two connected substrates and the snubber circuit
without a SiC CMOS gate buffer. In addition, when the
capacitor and the snubber resistor for high-temperature op-
eration are used [15, 16], this module can operate at 250◦ C.
Hereinafter, the module developed to reduce the inductance
of both the main circuit and gate wire is called “the two
low-inductance module”.
In our study, the switching time tsw of Vds was estimated
based on the gate (Qg ) charge of the UMOS and I-V char-
acteristics of the SiC CMOS gate buffer. Based on the Qg
results, the switching time tsw of Vds is estimated as fol-
lows [12, 27, 28]:
Qgd
tsw ≃ 0.8 × , (1)
Ig
where Qgd denotes the gate-drain charge [12] and Ig is the
gate current calculated based on the I-V characteristics of
the SiC CMOS gate buffer. Here 0.8 means 10%-90% of the
total switching time. In this study, Ig under the turn-on and
turn-off condition is given by
Vdd − Vg
Ig = (for turn-on), (2)
Vdspmos /Idspmos + Rgin
Vg
Ig = (for turn-off), (3)
Vdsnmos /Idsnmos + Rgin
where Idsnmos (Idspmos ) denotes the drain-source current and
Vdsnmos (Vdspmos ) are the drain-source voltage of the NMOS
(PMOS) in the SiC CMOS. Figure 2 shows the gate charge
waveforms of the UMOS at 600 V and 20 A. The Qg
results were derived from the measurement and extrapolation
results obtained using the Power Device Analyzer/Curve
Tracer (B1505A, Keysight Technologies, Inc.). In Fig. 2, the
region indicated by the blue arrow shows Qgd corresponding
to about 15.6 nC. Thus, for example, to realize a switching
time of about 6 ns, the output current of SiC CMOS gate
buffer during the Miller plateau of UMOS should be more
than about 2 A derived from Eq. (1).
Figure 1 (c) shows a photograph (top view) of the devel-
oped SiC CMOS gate buffer. In this study, only the final out-
put transistor (gate buffer) was fabricated using SiC CMOS
technology because its transistor is the most important part
of the gate driver. To achieve large current output charac-
teristics (e.g. more than about 2 A) of the SiC CMOS, the
fabricated SiC CMOS was parallelized. Here, the number
2
 IEICE Electronics Express, Vol.18, No.14, 1–5

of parallels is 1,200 and one unit is 100 µm. The approx- obtained an output current on the order of several amperes.
imate dimensions of SiC CMOS gate buffer are 1.2 × 2.8 Figure 4(a) shows the experimental turn-off and turn-on
mm (active area) without pads. The thickness of the gate waveforms of Vds and Ids under a switching condition of a DC
oxide film is 90 nm. In our SiC CMOS gate buffer, the ratio bus voltage of 600 V and a load current of 20 A with Vdd of
of the areas PMOS and NMOS is 1:1. For further details, 20 V in the double-pulse-test. Figures 4(b) and (c) indicate
see the fabrication process of the SiC CMOS component the experimental turn-off and turn-on waveforms of Vds at
in Ref [25], wherein the process employed was almost the
same as that in this study. The internal resistance of the SiC
CMOS gate buffer acted as the gate resistor, and no external
gate resistor was used [17]. Note that this internal resistance
is a nonliear resistor that depends on the applied voltage.

3. Results and discussion

Figures 3(a) and (b) show the I-V characteristics of the

NMOS and PMOS, respectively, in the SiC CMOS as mea-
sured by the curve tracer (CS-3200, Iwatsu Electric Co.,
Ltd.). To obtain the I-V characteristics, the drain-source cur-
rent Idsnmos (Idspmos ) and the drain-source voltage of Vdsnmos
(Vdspmos ) are measured at the gate-source Vgsnmos = 20, 25,
and 30 V (Vgspmos = −20, −25, and −30 V) of the NMOS
(PMOS) in the SiC CMOS. The output characteristics of the
NMOS and PMOS are almost identical. Note that the value
of V/I in these figures is the internal resistance of the SiC
CMOS gate buffer that corresponds to the gate resistance
for UMOS. The absolute values of drain-source current
increase with an increase in the absolute values of Vgsnmos
and Vgspmos . In the developed SiC CMOS gate buffer, we

Fig. 4 Experimental turn-off and turn-on waveforms of the main circuit

at 600 V and 20 A when using the developed module and SiC CMOS. (a)
Current and voltage waveforms at Vdd = 20 V, (b) Vds waveforms of the
turn-off operation at Vdd = 20, 25, and 30 V, (c) Vds waveforms of the turn-
on operation at Vdd = 20, 25, and 30 V, and (d) Vds waveforms of turn-on
operation at Vdd = 30 V with the SiC CMOS gate buffer placed outside
(switching time: 7.2 ns) and inside (switching time: 4.8 ns) the module,
Fig. 3 Typical I -V characteristics of SiC CMOS. (a) NMOS and (b)
for comparison purpose.
PMOS.

3

Fig. 5 Experimental and calculated switching time of Vds as a function
of Vdd when using the SiC CMOS gate buffer. The gray and yellow points
are calculated from Eqs. (1), (2), and (3).
Vdd = 20, 25, and 30 V. The green (■) and blue (▲) points
in Fig. 5 shows the experimental switching time during the
turn-on and turn-off operation of Vds as a function of Vdd . In
the switching test, the maximum Vin of the SiC CMOS gate
buffer was set to the same value as Vdd . The switching time
of Vds during the turn-off operation is defined as the rising
time of the voltage from 10% to 90% of the DC bus voltage.
The switching time of Vds during the turn-on operation is
defined as the falling time of the voltage to decrease from
90% to 10% of the DC bus voltage. Here, the experimental
switching time in the turn-on operation was about 4.8 ns
at Vdc = 600 V, Ids = 20 A, and Vdd = 30 V. In addition,
we experimentally realized a switching time of about 6.0 ns
during the turn-off operation at Vdd = 30 V. A peak overshoot
of about 690 V was observed at Vdc = 600 V and Ids = 20 A;
this value representing about 15% overshoot of the DC bus
voltage. The surge voltage was suppressed to less than about
90 V. Here, the turn-on switching speed dV/dt is about −100
V/ns, whereas the turn-off switching speed is about 80 V/ns.
Figure 4(d) shows the waveforms of the turn-on operation at
Vdd = 30 V with the SiC CMOS gate buffer placed outside
(switching time: 7.2 ns, switching speed: −67 V/ns) and
inside (switching time: 4.8 ns, switching speed: −100 V/ns)
the module for comparing the two situations. When the SiC
CMOS gate buffer is located outside the module, the gate
wiring is about 80 mm long; this length is almost the same as
that in previous studies [15, 16]. These results show that the
switching time can be shortened by reducing the parasitic
inductance of the gate wire (by placing the SiC CMOS gate
buffer inside the module) and by increasing the gate current.
A pioneering study [17], in which a SiC CMOS gate driver
was used, realized turn-on and turn-off switching speeds of
about −24 V/ns and 30 V/ns, respectively; in this study, we
achieved about 4.2 and 2.7 times the turn-on and turn-off
switching speeds, respectively, in the pioneering study. In
other previous studies [15, 16] that employed almost the
same module as the one used in this study and an external
Si gate driver, the switching speed was about −40 V/ns
during the turn-on operation and about 50 V/ns during the
turn-off operation for a waveform change defined from 10%
to 90%. With regard to the Si gate driver, the switching
speed is regulated because the gate buffer cannot be placed
within the module owing to the heating effects. The two low-
IEICE Electronics Express, Vol.18, No.14, 1–5
inductance module and the internal SiC CMOS gate buffer
allowed faster switching than when using the Si gate driver.
In Fig. 5, the gray (♦) and yellow (•) points indicate the
switching time of Vds as a function of Vdd calculated from
Eqs. (1), (2), and (3) during the turn-on and turn-off opera-
tions. The values were calculated using a circuit simulator
(PSIM, Powersim). For this calculation, the Qg charge of the
UMOS is as shown in Fig. 2, and I-V characteristics of the
SiC CMOS gate buffer are as shown in Fig. 3. The calculated
switching time in Fig. 5 is consistent with the experimental
switching time. The gate current during the Miller plateau
increases with an increase in Vdd . Thus, when Vdd increases,
the turn-on and turn-off switching time decrease. These cal-
culation results show that for the developed SiC CMOS gate
buffer with an output current of more than 2 A during the
Miller plateau, the switching time less than about 6 ns can be
achieved for the main circuit at Vdd = 30 V. The average er-
rors between the calculated and experimental times are only
about 14% within the parameter range of this study. It is
considered that the slight differences between experimental
and calculated results arise because factors such as the volt-
age dependence of UMOS input capacitance, the influence
of the parasitic component, and so on are neglected. In the
future, more accurate numerical calculations of high-speed
switching of the main circuit when using SiC CMOS gate
buffer and the module will be performed. In this study, the
fast switching of main circuits when using the developed SiC
CMOS gate buffer and the two low-inductance module for
a high-speed drive at room temperature was experimentally
demonstrated. In future studies, the high-speed switching
characteristics of this module at high temperatures will be
examined. This study paves the way for further research to-
ward higher-speed switching operations, prevention of false
turn-off/on, and the precise gate control. High-speed switch-
ing also helps reducing iron losses in the magnetic cores used
in motors and inductors [29, 30].
4. Conclusions
We focused on the high-speed switching operation of a SiC
power MOSFET in the main circuit when using a module for
the high-speed drive and SiC CMOS gate buffer. To quickly
charge and discharge the gate capacitor (i.e. to realize high-
speed switching) of the SiC power MOSFET, we developed
a SiC CMOS gate buffer with large current output charac-
teristics (the CMOS output current is more than about 2 A)
during the Miller plateau of the UMOS. Then we developed
a module that incorporates the SiC CMOS gate buffer and
SiC power MOSFET of the main circuit. This integrated
module was composed of two SiN-AMC substrates con-
nected together and of a snubber circuit. This module can
reduce the inductance of both main circuit and gate wire.
When using the developed module and SiC CMOS gate
buffer, we experimentally achieved the turn-on and turn-off
switching speeds of about −100 and 80 V/ns, respectively, at
600 V and 20 A. The approximate switching time was cal-
culated based on the Qg charge of the power MOSFET and
I-V characteristics of the developed SiC CMOS gate buffer.
These results will provide a reference for further work to-
4

ward high-temperature and high-speed power circuit that
incorporate combined modules for the high-speed drive and
the SiC CMOS gate buffer. In the future, accurate current
measurements will be performed using a wide-band current
probe. Further research will be conducted to generalize the
gate wire distance, gate current, and switching time.
Acknowledgments
This work was partly supported by a project (JPNP 14004)
commissioned by the New Energy and Industrial Technology
Development Organization (NEDO).
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