ECE 5745 Complex Digital ASIC Design

Topic 3: CMOS Circuits

Christopher Batten

School of Electrical and Computer Engineering

Cornell University

http://www.csl.cornell.edu/courses/ece5950
 Combinational Logic Sequential State

Part 1: ASIC Design Overview

P P Topic 1
Hardware
Description
Languages
M M
Topic 4 Topic 6 Topic 5
Full-Custom Closing Automated Topic 8
Design the Design Testing and Verification
Methodology Gap Methodologies

Topic 3
CMOS Circuits

Topic 7
Clocking, Power Distribution,
Topic 2 Packaging, and I/O
CMOS Devices

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 Combinational Logic Sequential State

CMOS Logic, State, Interconnect

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 • Combinational Logic • Sequential State

CMOS Logic, State, Interconnect

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 • Combinational Logic • Sequential State

CMOS Inverter Simple RC Model

Close switch when Vin = 0

Vin Vout
Vdd

Close switch when Vin = Vdd

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 A simple RC model for the
• Combinational Logic • Sequential State

inverter can
CMOSprovide significant
Inverter Simple insight
RC Model

Reff

Vin Vout Vin Vout

Cg Cd
Reff

Reff = Reff,N = Reff,P

Cg = Cg,N + Cg,P
Cd = Cd,N + Cd,P
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 11
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 The most basic CMOS gate
• Combinational Logic • Sequential State

is an inverter
CMOS Inverter Layout

VDD

WP/LP PMOS

Vin Vout
A Y
WN/LN

NMOS

GND

6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 10

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 The most basic CMOS gate
• Combinational Logic • Sequential State

is an inverter CMOS Inverter

Let’s make the following assumptions

1. All transistors are minimum length
WP/LP 2
2. All gates should have equal rise/fall
Vin Vout times. Since PMOS are twice as slow
as NMOS they must be twice as wide
WN/LN 1 to have the same effective resistance
3. Normalize all transistor widths to
minimum width NMOS

6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 9

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 • Combinational Logic • Sequential State

Series Transistors

Adapted from [Weste’11]

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 • Combinational Logic • Sequential State

Parallel Transistors

Adapted from [Weste’11]

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 Series and parallel MOSFET networks
• Combinational Logic • Sequential State

provide natural
Series/Parallel duals
Transistor of each
Networks areother
Natural Duals

A
A A B
B

Conducts if A=0 Conducts if A=0 OR B=0 Conducts if A=0 AND B=0

A
A A B
B

Conducts if A=1 Conducts if A=1 AND B=1 Conducts if A=1 OR B=1

6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 20

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 More complicated gates use more
• Combinational Logic • Sequential State

transistorsCMOS
in pullup/pulldown
Static Logic Style networks

VDD

Pullup network, connects output

to VDD, contains only PMOS
Input 0
Input 1 VOUT
Input N
Pulldown network, connects output
to GND, contains only NMOS

For every set of input logic values, either pullup or pulldown

network makes connection to VDD or GND
– If both connected, power rails would be shorted together
– If neither connected, output would float (tristate logic)

6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 19

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NAND and NOR gates illustrate the dual
• Combinational Logic • Sequential State

natureNAND/NOR
of the pullup/pulldown
Static CMOS Logic networks
Gates

NAND Gate NOR Gate

A A
(A.B) (A+B)
B B

(A.B) B
B (A+B)

ECE 5745 T03: CMOS 6.375

Circuits
Spring 2006 • L04 CMOS Transistors, Gates, and Wires13
• 21
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 • Combinational Logic • Sequential State

Approach for Designing More Complex Gates

I Goal is to create a logic function f (x1 , x2 , ...)
. We can only implement inverting logic with one CMOS stage
I Implement pulldown network
. Write PD = f (x1 , x2 , ...)
. Use parallel NMOS for OR of inputs
. Use series NMOS for AND of inputs
I Implement pullup network
. Write PU = f (x1 , x2 , ...) = g (x1 , x2 , ...)
. Use parallel PMOS for OR of inverted inputs
. Use series PMOS for AND of inverted inputs

ECE 5745 T03: CMOS Circuits 14 / 28

Designers can use a methodical
approach to build more complex gates
• Combinational Logic • Sequential State

Complex Logic Gate Example

A
f (A B) C
B PD (A B) C
(A+B).C
C PU (A B) C
(A B) C
( A B) C

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 • Combinational Logic • Sequential State

Single- vs. Multi-Stage Static CMOS Logic

Adapted from [Weste’11]

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 • Combinational Logic • Sequential State

Multiple Stages of Static CMOS Logic

Each design has different delay,

area, and energy trade-offs

Adapted from [Weste’11]

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 • Combinational Logic • Sequential State

CMOS Pass-Transistor Logic Style

Adapted from [Weste’11]

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 • Combinational Logic • Sequential State

CMOS Transmission Gate Multiplexer

Adapted from [Weste’11]

ECE 5745 T03: CMOS Circuits 19 / 28

 • Combinational Logic • Sequential State

CMOS Tri-State Buffers

Vdd

En

A Y

En
Gnd

Adapted from [Weste’11]

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 • Combinational Logic • Sequential State

Various Multiplexer Implementations

Each design has different delay,

area, and energy trade-offs
Simple first-order analysis can help
suggest some of these trade-offs

Adapted from [Weste’11]

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 • Combinational Logic • Sequential State

Larger Tri-State Multiplexers

Adapted from [Weste’11]

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 Combinational Logic • Sequential State •

CMOS Logic, State, Interconnect

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 Combinational Logic • Sequential State •

Level-High Latch

Adapted from [Weste’11]

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 Combinational Logic • Sequential State •

Positive-Edge Triggered Flip-Flop

Adapted from [Weste’11]

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 Combinational Logic • Sequential State •

Positive-Edge Triggered Flip-Flop

Adapted from [Weste’11]

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 Combinational Logic Sequential State

Take-Away Points
I We have reviewed basic CMOS circuit implementations
. Combinational Logic: static CMOS, pass-transistor, tri-state buffers
. Sequential State: latches, flip-flops
I In the next two sections, we will explore various methodologies which
enable mapping designs written in a hardware-description language
down into these circuits
I In the next part of the course, we will explore the details of how to
quantitatively evaluate the cycle time, area, and energy of these
circuits

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 Combinational Logic Sequential State

Acknowledgments
I [Weste’11] N. Weste and D. Harris, “CMOS VLSI Design: A Circuits
and Systems Perspective,” 4th ed, Addison Wesley, 2011.

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