Three terminal devices

• Two terminal devices have fixed IV characteristics

• Three terminal devices – IV of two terminal can be controlled using

the third terminal.
• Examples – Switch (linear), Transistors (non-linear)
 Switch – IV Characteristics
• IV characteristics between terminal 𝑇! and 𝑇" is controlled by 𝐶
𝐶

𝑇! 𝑇"

𝑖
𝐶 = ”1” (𝑂𝑁)
𝐶 = ”0” 𝐶 = ”1”
𝐶 = ”0” (𝑂𝐹𝐹)

𝑣
Switch OFF Switch ON
Switch – Types
• Depending on the control, the switch can be
• Analog: Controlled using physical toggle/button
• Digital: Controlled using voltage or current. Example – MOSFET
(voltage controlled), BJT (current controlled)

Analog switches Digital switches (Transistors)

Switch Application – Logic Gates
• We can use switches to build logic gates
A B Bulb
0 0 OFF
0 1 OFF
AND operation
1 0 OFF
1 1 ON

A B Bulb
0 0 OFF
0 1 ON
OR operation
1 0 ON
1 1 ON
 Switch Application – Logic Gates

A Bulb A B Bulb A B Bulb

0 ON 0 0 ON 0 0 ON
1 OFF 0 1 ON 0 1 OFF
1 0 ON 1 0 OFF
1 1 OFF 1 1 OFF

NOT operation NAND operation NOR operation

These circuits are “preferred” – because they can be cascaded to build combinational logic circuits
-> if we remove the bulb and use the voltage across instead to cascade and drive the next gate
Switch Application – Logic Gates
Alternative representations:
Switch Application – Logic Gates
Alternative representations:

Vss Vss Vss Vss

Switch Application – Logic Gates

𝐴 𝑉𝑶𝑼𝑻 𝐴 𝑩 𝑉𝑶𝑼𝑻 𝐴 𝑩 𝑉𝑶𝑼𝑻

0 5V 0 0 5V 0 0 5V
1 0V 0 1 5V 0 1 0V
1 0 5V 1 0 0V
1 1 0V 1 1 0V
Examples
Example
Implement using switches: 𝑓 = (𝐴 + 𝐵)𝐶
Digital Representation
• Binary → Two states (0/False, 1/True)
• Binary variables in circuit, need to use two states of device/parameters

Voltage Current State

5V à 1 2mA à 1 ON à 1
0V à 0 3mA à 0 OFF à 0

0V à 1 Low resistance à 1
3.3V à 0 High resistance à 0
Digital Representation
Suppose you want to send 010110

• Single value based representaion fails in the presence of noise

• Better approach – threshold-based system
• Simplest: Logical 0 = 𝑉 < 𝑉# Logical 1 = 𝑉 > 𝑉#
Static Discipline

• Specification for digital devices

• Requires devices to adhere to common representation to ensure that
valid input produces valid output
• This means, if
• Sender sends “0” Receiver interprets as “0”

• Sender sends ”1” Receiver interprets as “1”

 Static Discipline
Naïve approach: Single threshold based system
𝑉$ = 2.5 𝑉
5V

1 Valid 1 1 sender receiver

Logical 0: 𝑉% < 𝑉$ Logical 0: 𝑉& < 𝑉$

sender 2.5V receiver Logical 1: 𝑉% > 𝑉$ Logical 1: 𝑉& > 𝑉$

0 Valid 0 0
What if 𝑉& = 2.5𝑉? Undefined!

0V
 Static Discipline
Double threshold based system
𝑉' = High voltage threshold = 3𝑉
5V 𝑉( = Low voltage threshold = 2𝑉

1 Valid 1 1 sender receiver

3V Logical 0: 𝑉% < 𝑉( Logical 0: 𝑉& < 𝑉(
Forbidden
sender receiver Logical 1: 𝑉% > 𝑉' Logical 1: 𝑉& > 𝑉'
Region
2V

0 Valid 0 0 What if 𝑉% = 1.9𝑉 and channel noise is 0.5𝑉?

𝑉& = 1.9𝑉 + 0.5𝑉 = 2.4𝑉 = invalid
0V
è valid output producing invalid input,
i.e., no margin for noise
 Static Discipline
Four threshold based system à Tighter restriction on sender (output)
𝑉)' = Output high voltage threshold = 4.5𝑉

5V 𝑉)( = Output low voltage threshold = 0.5𝑉

1 Valid 1 𝑉*' = Input high voltage threshold = 3𝑉
4.5V 1
NM1 𝑉*( = Input low voltage threshold = 2𝑉
3V
Forbidden sender receiver
sender receiver
Region
2V Logical 0: 𝑉% < 𝑉)( Logical 0: 𝑉& < 𝑉*(
NM0 Logical 1: 𝑉% > 𝑉)' Logical 1: 𝑉& > 𝑉*'
0.5V 0
0 Valid 0 For static discipline, 𝑉)( < 𝑉*( < 𝑉*' < 𝑉)'
0V
Noise margins (NM):
• 𝑁𝑀+ = 𝑉)' − 𝑉*' = 4.5 − 3 = 1.5𝑉 (signiJicance? )
• 𝑁𝑀, = 𝑉*( − 𝑉)( = 2 − 0.5 = 1.5𝑉 (signiJicance? )
Static Discipline
Four threshold based system à Tighter restriction on sender (output)
Transistors as Digital Switch
• Transistors are 3 terminal non-linear devices, can be used as switch
• 2 types – Voltage Controlled, Current Controlled
• Metal Oxide Semiconductor Field Effect Transistor (MOSFET) are voltage controlled
• Control, 𝐶 = 𝑉!" . The IV characteristics (𝐼#" 𝑣𝑠 𝑉#" ) depends on 𝑉!"
• Actual dependency is complex.
• Will start with a simple (but approximate) one – S-Model (Switch Model)
MOSFET S-Model
• The MOSFET (approximately) behaves like a switch
• 𝐶 = 𝑉$% . Here, 𝐶 = “0” ⇒ 𝑉$% < 𝑉# , and 𝐶 = “1” ⇒ 𝑉$% ≥ 𝑉#
MOSFET S-Model
Logic Gates using MOSFET
Just replace the switches with MOSFETs!

Vss
Vss Vss

NOT Gate (Inverter) NAND Gate (Inverter) NOR Gate (Inverter)

MOSFET Logic Gates – More Examples

Vss Vss Vss

𝑂𝑈𝑇 = 𝐴𝐵 + 𝐶 + 𝐷 𝑂𝑢𝑡 = 𝐴 + 𝐵 𝐶𝐷 = 𝐴 + 𝐵 𝐶𝐷
Voltage Transfer Characteristics (VTC)
• Reminder: VTC is a graph where x axis = input voltage, y axis = output voltate
• Why? Design logic gates to follow a given static discipline

When 𝑣*- < 𝑉$ Logical 0 , 𝑣).$ = 𝑉/ = 5𝑉 (Logical 1)

When 𝑣*- ≥ 𝑉$ Logical 1 , 𝑣).$ = 0 (Logical 0)
Vss
VTC of NAND gate
• We only have one x axis, but two inputs
• Solution: Draw two VTC, one considering 𝑉AY=="0"
0, one considering 𝑉AY=="1"
1

Vss When 𝑉A0 =="0"

0 When 𝑉A0 =="1"
1

Vss Vss Vss Vss

VTC of NAND gate
• We only have one x axis, but two inputs
• Solution: Draw two VTC, one considering 𝑉 0, one considering 𝑉
AY=="0" AY=="1"
1

Vss A0 =="0"
When 𝑉 0 When 𝑉A
0 =
="1"
1

Homework: Find VTC for NOR gate

Construction of Real MOSFET

Top view of several n-channel

100 MOSFETs fabricated on a chip. The
𝜇𝑚 square MOSFETs in the center of the
photograph have a width and length
of 100 μm. (Photograph Courtesy of
Maxim Integrated Products.)
 Construction of Real MOSFET

Simplified cross section

and 3D view

Channel created
Will have some R
No channel, open ckt 𝑉12 = 0𝑉 𝑉12 > 𝑉$ -> SR model
 SR Model

1 1
𝑅)- = =
5 𝑊
𝑘4 (𝑉12 − 𝑉$ ) 𝑘𝑉)6
𝐿

Unit of 𝑘 = 𝑚𝐴/𝑉 7

• SR model is a better approximation than S model

• However, still an approximation. This model fails when 𝑉32 increases to around 𝑉12 − 𝑉$
SR Model - Inverter

Vss For example, if Vss

𝑉2 = 5𝑉,
Vss Vss 𝑅)- = 1 𝑘Ω, 𝑅( = 14 𝑘Ω
Vss

Vss

𝑅)-
𝑣).$,'&9: = Vss
𝑉2 𝑣).$,(%; =Vss
𝑉2 ≠0
𝑅)- + 𝑅(
 Design of logic gates
Expected
𝐼𝑁 𝑩 𝑶𝑼𝑻
𝐵
Low (𝑉!" < 𝑉# ) High (5𝑉) Low (𝑉$%# = 𝑉$%#,'() )
High (𝑉!" < 𝑉# ) Low (𝑉$%#,'() ) High (5V)

Vss

Actual
𝐼𝑁 𝑩 𝑶𝑼𝑻
Low (𝑉!" < 𝑉# ) High (5𝑉) Low (𝑉$%# = 𝑉$%#,'() )
High (𝑉!" < 𝑉# ) Low (𝑉$%#,'() = 0.5 𝑉) Low (𝑉$%# = 𝑉$%#,'()

Therefore, need to design logic gates properly

𝑉$ = 0.4 𝑉, Vss
𝑉2 = 5𝑉, 𝑅)- = 1 𝑘Ω, 𝑅( = 9 𝑘Ω such that
𝑅)- 1
𝑉).$,'&9: = Vss
𝑉2 = 5𝑉 𝑉).$,(%; =Vss
𝑉2 =5 = 0.5 𝑉 Vss
𝑅)- + 𝑅( 1+9
Design of logic gates - Example
Assume the following values for the inverter circuit parameters: 𝑉! = 5 𝑉, 𝑉" = 1 𝑉, and 𝑅𝐿 =
# &
10 𝑘Ω. Assume, further, that + = 5 for the MOSFET. Determine a sizing for the MOSFET so
$* %,- '
that the inverter gate output for a logical 0 is able to switch OFF the MOSFET of another inverter.

Solution:
𝑅)- 1 1
𝑉2 < 𝑉$ Now, 𝑅)- = = 5×
𝑅)- + 𝑅( 𝑊 𝑊/𝐿
𝑘45 𝐿 𝑉)6
𝑅)-
⇒5 <1
𝑅)- + 10
5 𝑊 5
⇒ 5𝑅)- < 𝑅)- + 10 Hence < 2.5 ⇒ >
𝑊/𝐿 𝐿 2.5
10
⇒ 𝑅)- < = 2.5 𝑊
4 ⇒ >2
𝐿
Review – MOSFET

Control = 𝑉!" = 𝑉! − 𝑉" , controls the IV between drain-source (𝐼#" vs 𝑉#" )

Threshold voltage = 𝑉$ , minimum voltage required to create the channel

Models
1. S Mode: Assumes an ideal channel with zero resistance
2. SR Model: Assumes finite channel resistance, 𝑅%& , depends on 𝑉!" − 𝑉$ = 𝑉%'
MOSFET Linear Models
S Model SR Model

1 1
𝑅!" = =
$ 𝑊
𝑘# 𝐿 (𝑉%& − 𝑉' ) 𝑘𝑉!(
Real MOSFET
2 2 2
• Why 𝑅%& = #
" (' 4' )
= 3'()
? Because channel width ∝ 𝑉%' , and 𝑅 ∝ 56789
3! $ %& '

• For small 𝑉#" , uniform channel, hence fixed 𝑅%& , therefore SR model valid.
• As 𝑉#" is increased, channel becomes tapered cause 𝑉!# ↓. Resistance ↑, slope ↓.
• This mode is called the triode mode. Condition: 𝑉#" < 𝑉%'
Real MOSFET

• When 𝑉#" = 𝑉%' , channel pinches off.

• Increasing 𝑉#" further have no effect on channel shape. Hence, current saturates
• This mode is called the saturation mode. Condition: 𝑉#" ≥ 𝑉%'
• Behaves like a current source (constant current) that depends on 𝑉%'
IV Characteristics of Real MOSFET

Mode Condition Equation

Cutoff 𝑉%& < 𝑉' 𝐼) = 0
Triode 𝑉%& ≥ 𝑉' 1 *
𝐼) = 𝑘[𝑉!( 𝑉)& − 𝑉)& ]
𝑉)& < 𝑉!( 2
Saturation 𝑉%& ≥ 𝑉' 𝑘 *
𝐼) = 𝑉!(
𝑉)& ≥ 𝑉!( 2

𝑉!( = 𝑉%& − 𝑉'

𝑊
𝑘 = 𝑘#$
𝐿
Solving Circuits with MOSFET
• Use Method of Assumed State!
• Three steps:
• Assume: One of the modes (Cutoff, Triode, Saturation)
• Solve: Use corresponding equation and KCL+KVL
• Verify: Check if the conditions of 𝑉!" and 𝑉#" are satisfied. If not,
repeat.
• Might need to solve quadratic equation (𝑎𝑥 $ + 𝑏𝑥 + 𝑐 = 0).
• If we get two roots, choose the one that’s favorable to your
assumption
Example 1
Solution:

Step 1: Assume the MOSFET in saturation

𝑘 *
Step 2: 𝐼) = 𝑉 Here, 𝑉%& = 𝑉% − 𝑉& = 𝑉% − 0 = 𝑉% = 𝑉+ = 2𝑉
2 !(
Therefore, 𝑉!( = 𝑉%& − 𝑉' = 2 − 1 = 1𝑉
0.5 *
∴ 𝐼) = 1 = 0.25 𝑚𝐴
2
Again, 𝑉)& = 𝑉) − 𝑉& = 𝑉) − 0 = 𝑉) = 𝑉-

The MOSFET is specified as KVL along 𝐿, : 𝐼) ×1𝑘Ω + 𝑉- = 5 − 0 ⇒ 𝑉. = 5 − 𝐼) ×1𝑘Ω

𝑉! = 1𝑉 and 𝑘 = 0.5 𝑚𝐴/𝑉 " . ⇒ 𝑉- = 5 − 0.25×1 = 4.75 𝑉 = 𝑉)&
Find 𝐼# and 𝑉$ for 𝑉% = 2𝑉.
Step 3: 𝑉%& = 2𝑉 > 𝑉' √ Therefore, assumption correct!
𝑉)& = 1𝑉 > 𝑉!( √ Correct ans: 𝐼) = 0.25 𝑚𝐴, 𝑉- = 4.75 𝑉
Example 2
Solution:

Step 1: Assume the MOSFET in saturation

𝑘 *
Step 2: 𝐼) = 𝑉 Here, 𝑉%& = 𝑉% − 𝑉& = 𝑉% − 0 = 𝑉% = 𝑉+ = 5𝑉
2 !(
Therefore, 𝑉!( = 𝑉%& − 𝑉' = 5 − 1 = 4𝑉
0.5 *
∴ 𝐼) = 4 = 4 𝑚𝐴
2
Again, 𝑉)& = 𝑉) − 𝑉& = 𝑉) − 0 = 𝑉) = 𝑉-

The MOSFET is specified as KVL along 𝐿, : 𝐼) ×1𝑘Ω + 𝑉- = 5 − 0 ⇒ 𝑉. = 5 − 𝐼) ×1𝑘Ω

𝑉! = 1𝑉 and 𝑘 = 0.5 𝑚𝐴/𝑉 " . ⇒ 𝑉- = 5 − 4×1 = 1 𝑉 = 𝑉)&
Find 𝐼# and 𝑉$ for 𝑉% = 5𝑉.
Step 3: 𝑉%& = 5𝑉 > 𝑉' √ Therefore, assumption wrong!
𝑉)& = 1𝑉 ≯ 𝑉!( ×
Example 2
Step 1: Assume the MOSFET in triode
Step 2: 𝐼) = 𝑘[𝑉!( 𝑉)& − 𝑉)& ]
The MOSFET is specified as
𝑉! = 1𝑉 and 𝑘 = 0.5 𝑚𝐴/𝑉 " .
Find 𝐼# and 𝑉$ for 𝑉% = 5𝑉.
Repeat:
1 *
2
Here, 𝑉%& = 𝑉% − 𝑉& = 𝑉% − 0 = 𝑉% = 𝑉+ = 5𝑉
Therefore, 𝑉!( = 𝑉%& − 𝑉' = 5 − 1 = 4𝑉
Again, 𝑉)& = 𝑉) − 𝑉& = 𝑉) − 0 = 𝑉) = 𝑉- . Assuming 𝑉)& = 𝑥
/0(!"
KVL along 𝐿, : 𝐼) ×1𝑘Ω + 𝑉- = 5 − 0 ⇒ 𝐼) = =5−𝑥
,
1 * 1
∴ 𝐼) = 0.5 4×𝑉)& − 𝑉)& ⇒ 5 − 𝑥 = 0.5 4𝑥 − 𝑥 *
2 2
⇒ 5 − 𝑥 = 2𝑥 − 0.25𝑥 * ⇒ 0.25𝑥 * − 3𝑥 + 5 = 0
Solving, 𝑥 = 2𝑉, 𝑥 = 10𝑉 Since 𝑉)& = 𝑥 is small in triode,
smaller value of 𝑥 is favorable
Therfore, 𝑉- = 𝑉)& = 𝑥 = 2𝑉, and 𝐼) = 5 − 𝑥 = 3 𝑚𝐴

Step 3: 𝑉%& = 5𝑉 > 𝑉' √ Therefore, assumption correct!

𝑉)& = 2𝑉 < 𝑉!( √ Correct ans: 𝐼) = 3 𝑚𝐴, 𝑉- = 2 𝑉
 Example 3 Step 2: 𝐼) =
𝑘 *
𝑉
2 -1
Let's assume 𝑉. = 𝑉& = 𝑥
Here, 𝑉%& = 𝑉% − 𝑉& = 𝑉% − 𝑉- = 2 − 𝑥
Therefore, 𝑉!( = 𝑉%& − 𝑉' = 2 − 𝑥 − 1 = 1 − 𝑥
Again, 𝑉)& = 𝑉) − 𝑉& = 𝑉) − 𝑉. = 5 − 𝑥
(#0.
Ohm’s law for the resistor: 𝐼) = ,23
=𝑥
4
∴ 𝑥 = 1 − 𝑥 * ⇒ 𝑥 = 2 1 − 2𝑥 + 𝑥 * ⇒ 𝑥 = 2 − 4𝑥 + 2𝑥 *
2
⇒ 2𝑥 * − 5𝑥 + 2 = 0
The MOSFET is specified as Solving, 𝑥 = 0.5, 𝑥 = 2𝑉 Since 𝑉)& = 5 − 𝑥 is large in saturation
𝑉! = 1𝑉 and 𝑘 = 4 𝑚𝐴/𝑉 " . smaller value of 𝑥 is favorable
Find 𝐼# and 𝑉$
∴ 𝑉! = 𝑉" = 𝑥 = 0.5𝑉, 𝐼# = 𝑥 = 0.5 𝑚𝐴,
Solution: 𝑉#" = 5 − 𝑥 = 4.5𝑉, 𝑉$" = 2 − 𝑥 = 1.5𝑉, and 𝑉%& = 1 − 𝑥 = 0.5𝑉
Step 1: Assume the MOSFET in saturation Step 3: 𝑉%& = 1.5𝑉 > 𝑉' √ Therefore, assumption correct!
𝑉)& = 4.5𝑉 > 𝑉!( √ Correct ans: 𝐼) = 0.5 𝑚𝐴, 𝑉- = 0.5 𝑉
Practice

Now if you assume saturation:

𝑘 * 2 *
𝐼) = 𝑉!( ⇒ 𝑥 = 4 − 3𝑥
2 2

Hint Explanation And if you assume triode:

,.0(! 1 *
Assume 𝐼) = 𝑥. For 5𝑘Ω: 𝐼) = ⇒ V4 = 10 − 5×𝐼) = 10 − 5𝑥. 𝐼) = 𝑘[𝑉!( 𝑉)& − 𝑉)& ]
/ 2
(" 0.
For 3𝑘Ω: 𝐼) = 5
⇒ V6 = 3×𝐼) = 3𝑥.
⇒ 𝑥 = 2[ 4 − 3𝑥 10 − 8𝑥 − 0.5× 10 − 8𝑥 ! ]
Therefore, V%& = 𝑉% − 𝑉& = 5 − 3𝑥, and 𝑉!( = 𝑉%& − 𝑉' = 5 − 3𝑥 − 1
Solve for 𝑥, take the ______ root
Also, V)& = 𝑉) − 𝑉& = 10 − 5𝑥 − 3𝑥 = 10 − 8𝑥