ENTITY Unit in VHDL

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VHDL stands for "very high speed integrated circuits hardware description language", and first
developed by the US department of defense in 1980s

Entity part is used to describe the input and output ports of an electronic circuit, i.e., used to
describe I/O ports.
A port can be an input port, or an output port, or both input and output port at the same time, or can be a
buffer port. In Figure 1-1, the graphical illustration of the port types is given.

Figure 1-1 2
The general structure of the entity part is shown in PS 1.1

entity entity_name is
port( port_ID1: I/O option signal_type;
port_ID2: I/O option signal_type;
⋯);
end [entity] [entity_name];

PS 1.1

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Example-1.1: The black box representation of an electronic circuit is shown in Figure 1-2.
Describe the electronic circuit ports by a VHDL program segment, i.e., by PS.

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Solution:
S1) First, write the reserved word entity as in PS 1.2

entity
PS 1.2
S2) In step 2, we give a name to entity as in PS 1.3.

entity my_circuit_name

PS 1.3
S3) In step 3, write the reserved word is to the end of the line of PS 1.3 as in PS 1.4.

entity my_circuit_name is

PS 1.4
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S4) In step 4, write the closing tag of entity part as in PS 1.5.

entity my_circuit_name is

end my_circuit_name

PS 1.5
S5) In step 5, put a semicolon to the end of the closing tag as in PS 1.6.

entity my_circuit_name is

end my_circuit_name;

PS 1.6

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S6) In step 6, write the reserved word port as in PS 1.7.
entity my_circuit_name is
port
end my_circuit_name;

PS 1.7
S7) In step 7, add parentheses to the port as in PS 1.8.

entity my_circuit_name is
port()
end my_circuit_name;

PS 1.8

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S9) If we look at the black box in Figure 1-2, we see that we have two input ports and three
output ports. Let’s give names to these ports as in PS 1.10.

entity my_circuit_name is
port( inp1
inp2
outp1
outp2
outp3 );
end my_circuit_name;

PS 1.10

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S10) In step 10, we indicate the type of the ports using the reserved words in and out as in
PS 1.11.
entity my_circuit_name is
port( inp1: in
inp2: in
outp1: out
outp2: out
outp3: out );
end my_circuit_name;

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S11) In Step 11, we indicate the data type available at the input and output ports an in PS
1.12 where we used std_logic for all port data types

entity my_circuit_name is
port( inp1: in std_logic
inp2: in std_logic
outp1: out std_logic
outp2: out std_logic
outp3: out std_logic );
end my_circuit_name;

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S12) In step 12, we put semicolon to the end of every std_logic except for the last one as
in PS 1.13

entity my_circuit_name is
port( inp1: in std_logic;
inp2: in std_logic;
outp1: out std_logic;
outp2: out std_logic;
outp3: out std_logic );
end my_circuit_name;

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The enclosing tag or enclosing line of the program segment in PS 1.13 can also be written as in
PS 1.14
entity my_circuit_name is
port( inp1: in std_logic;
inp2: in std_logic;
outp1: out std_logic;
outp2: out std_logic;
outp3: out std_logic );
end entity;
entity my_circuit_name is
port( inp1: in std_logic;
inp2: in std_logic;
outp1: out std_logic;
outp2: out std_logic;
outp3: out std_logic );
end;
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S12) In Step 12, add the header lines which are necessary for the data type std_logic to be
meaningful in our VHDL program as in PS 1.15.

library IEEE;
use IEEE.std_logic_1164.all;

entity my_circuit_name is
port( inp1: in std_logic;
inp2: in std_logic;
outp1: out std_logic;
outp2: out std_logic;
outp3: out std_logic );
end my_circuit_name;

PS 1.15

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S12) Finally, we can add some comments to our VHDL code. For this purpose, we can use

-- Your comment here

format in our program. Then, our entity part becomes as in PS 1.16.

library IEEE; -- IEEE library

use IEEE.std_logic_1164.all; -- Necessary to
use the std_logic

entity my_circuit_name is
port( inp1: in std_logic; --Input port
inp2: in std_logic; --Input port
outp1: out std_logic; --Output port
outp2: out std_logic; --Output port
outp3: out std_logic ); --Output port
end my_circuit_name; -- End of entity

PS 1.16 14