Lesson 5

PROCESSOR STRUCTURE AND

PROGRAM EXECUTION
Nguyễn Hồng Sơn

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CPU OPERATIONS
 CPU tasks
 Fetch instructions
 Interpret instructions
 Fetch data
 Process data
 Write data

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CPU with System Bus

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CPU internal structure

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Registers
 The CPU needs temporary memory areas to work,
called registers.
 Quantity and functionality vary by processor
design.
 One of the most important design decisions.
 The highest level in the memory hierarchy.

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 User-visible register
User-visible register is a register that can be
referenced via machine language, including:
 General Purpose: contain operands of instructions
 Data: contains only data, not used to calculate the
address.
 Address: used for addressing modes such as
segment pointer, index register, stack pointer
Condition Codes: contains condition codes (also
known as flags)
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 Control & status register
 There are a number of registers that are used
to control CPU operations
 Program Counter
 Instruction Decoding Register
 Memory Address Register
 Memory Buffer Register
 All designs have a register or set of registers
called PSW (Program Status Word)
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 PSW
 PSW contains condition codes along with other status
information. Common fields or flags include:
 Sign
 Zero
 Carry
 Equal
 Overflow
 Interrupt enable/disable
 Supervisor: Specify the mode as user or supervisor (kernel)

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Supervisor mode (Kernel mode)
 Privileged directives can only be executed in
supervisor mode.
 Special memory can only be accessed in
supervisor mode
 Used by the operating system
 Not available for user programs.

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Examples of registers

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 Program execution overview
 An executed program consists of a set of instructions
stored in main memory.
 The CPU is responsible for loading and executing each
instruction specified in the program.
 Thus, the process of running an instruction consists of two
steps:
 CPU reads instructions from memory
 The CPU executes instructions, which may include a number of
operations

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Instruction cycle
 Program execution consists of repeating the
process of instruction fetch and instruction
execution  instruction cycles
 Instruction cycle: The necessary time for running
completely an instruction.
 Subcycles:
 Fetch cycle
 Execute cycle

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Basic Instruction Cycle
start

Fetch Fetch cycle

next instruction

Execute instruction Execute cycle

End
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The process of running instructions
of a program
 At the beginning of each instruction cycle, the processor
fetches an instruction from memory
 PC (program counter): holds the address of the instruction
to be fetched next
 By default, increments the address in the PC by one after
each instruction fetch
 Instruction is fetched into IR (instruction register)

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The process of running instructions
of a program…
 The instruction contains bits that specify the action the
processor is to take.
 The processor interprets the instruction and performs the
required action.
 In general, these actions fall into four categories:
 CPU-Memory
 CPU-I/O
 Data processing
 Control

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 The process of running instructions
of a program…
 An instruction’s execution may involve a combination of
these actions.
 One execution cycle can have multiple memory references.
 One execution cycle can have multiple I/O references
 One execution cycle can have both I/O and memory
references

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 States of an Instruction
 (1)Instruction address calculation (iac): Determine the address of the next
instruction to be executed.
 (2)Instruction fetch (if): Read instruction from its memory location into the
processor.
 (3)Instruction operation decoding (iod): Analyze instruction to determine type of
operation to be performed and operand(s) to be used.
 (4)Operand address calculation (oac): If the operation involves reference to an
operand in memory or available via I/O, then determine the address of the
operand.
 (5)Operand fetch (of): Fetch the operand from memory or read it in from I/O.
 (6)Data operation (do): Perform the operation indicated in the instruction.
 (7)Operand store (os): Write the result into memory or out to I/O.

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 Instruction Cycle State Diagram

CPU access
2 5 7
MM or I/O

Multiple Multiple
operands results

Operations 3 4 6 4
inside CPU 1
Next Vector or
instruction string

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 Return for string or vector data
 An instruction can specify an operator to perform on a
vector (one-dimensional array) or sequence of characters.
This involves iterative retrieving or storing data.

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 Example: a Hypothetical Machine
 Memory word: 16 bit size
 Instruction: 4 bit opcode and 12 bit address (direct addressing mode)
 Data: 1 bit (sign) and 15 bit (magnitude)
 Registers:
 PC (Program Counter)
 IR (Instruction Register)
 AC(Accumulator)
 4 of 16 opcodes:
 0001: Transfer contents of memory location X to the AC
 0010: Transfer contents of AC to memory location X
 0101: Add M(X) to AC; put the result in AC.
 0110: Multiply M(X) by contents of AC; put the result in AC.

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 Example 1: programming
 Let adding the contents of the memory word at address 940 to the
contents of the memory word at address 941 and stores the result in
the latter location.
 The program is stored at address of 0x300
 Program
 Fetch contains of 0x940 to AC
 Add contains of 0x941 to contains of AC
 Transfer contains of AC to 0x941
 Thus, have 3 instruction with 3 fetch cycles and 3 execute cycles.

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 Cycle of Instruction 1

Main memory registers

300 1940 300 PC 300 1940 300 PC
301 5941 AC 301 5941 0003 AC

302 2941 1940 IR 302 2941 1940 IR

940 0003 940 0003

941 0002 941 0002

Fetch cycle of instruction 1 Execute cycle of instruction 1

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 Cycle of Instruction 2

300 1940 301 PC 300 1940 301 PC

301 5941 0003 AC 301 5941 0005 AC

302 2941 5941 IR 302 2941 5941 IR

940 940 3h + 2h=5h

0003 0003
941 0002 941 0002

Fetch cycle of instruction 2 Execute cycle of instruction 2

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 Cycle of Instruction 3

300 1940 302 PC 300 1940 302 PC

301 5941 0005 AC 301 5941 0005 AC

302 2941 2941 IR 302 2941 2941 IR

940 0003 940 0003

941 0002 941 0005

Fetch cycle of instruction 3 Execute cycle of instruction 3

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 Example 2

 Show the instruction cycles performing the calculation:

(3+2)*5 (5 contained at 0x942), store the results at 0x942

 Steps ......

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 300 1940 300 PC
300 1940 300 PC
301 5941 0003 AC
301 5941 AC
302 6942 1940 IR
302 6942 1940 IR
303 2942
303 2942

940 0003
940 0003 941 0002
941 0002 942 0005
942 0005
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 300 1940 302 PC
300 1940 302 PC
301 5941 0019 AC
301 5941 0005 AC
302 6942 6942 IR
302 6942 6942 IR
303 2942
303 2942
0005h * 0005h=0019h

940 0003
940 0003 941 0002
941 0002 942 0005
942 0005
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 300 1940 303 PC
300 1940 303 PC
301 5941 0019 AC
301 5941 0005 AC
302 6942 2942 IR
302 6942 2942 IR
303 2942
303 2942

940 0003
940 0003 941 0002
941 0002 942 0019
942 0005
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 Homeworks
1. Write a program to calculate (2+3)*(3+4) on a hypothetical machine
like example 2, with the number of 4 stored at 0x942, store the result at
0x942 and show all instruction cycles?
2. Write a program that performs the following calculation on an IAS
(John Von Neumann computer)
(4+2)*5, store the result at 0x202
Show all instruction cycles performing the above calculation?
With data (4,2, and 5) stored in main memory from location 0x200 and
program loaded into main memory starting at location 0x100.

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The End

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