4.3 Adders Page 4.

2
First, we will need the following:
x ⊕ y ⊕ z is 1 when just one or all three of x, y, z, is 1.
xy + xz + yz = xy ⊕ xz ⊕ yz, and is 1 when at least two of x, y, z, is 1.
Half adder:
Symbol Function Truth table Outputs Circuit
_____ x ___ c
|x c| s = arith x + y x y s d s = x ⊕ y ------*-------|AND|-------
| HA | with carry out c 0 0 0 0 c = xy -------|---*---|___|
|y s| 0 1 1 0 y | | ___ s
|_____| 1 0 1 0 | |---|XOR|-------
1 1 0 1 |-------|___|

Full adder:
Symbol Function Truth table Outputs
_____
|c d| s = arith x + y x y c s d s = x ⊕ y ⊕ c
| | with carry in c 0 0 0 0 0 d = xy ⊕ xc ⊕ yc
|x | and carry out d 0 0 1 1 0
| FA | 0 1 0 1 0 noting s = 1 when 1 or all 3 of x,y,c = 1
|y s| 0 1 1 0 1 d = 1 when at least 2 of x,y,c = 1
|_____| 1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Circuit
x ____ xy _____ d = xy ⊕ xc ⊕ yc
----------|x c|-----------------------------------| |----------------------
| HA | ____ | XOR |
----------|y s|--------|x c|---------------------|____ |
y |____| x ⊕
y | HA | c(x ⊕ y) = cx ⊕ cy
| |
------------------------|y s|------------------------------------------------
c |____| s = x ⊕ y ⊕ c

There is a "handle cranking" way of getting an expression for d. _ _ _

Looking at the rows of the truth table where d = 1 we see that d = xyc+xyc+xyc+xyc.
Adding Integers.
To perform the sum x2 x1 x0 with carry out c3, use the circuit
+ y2 y1 y0
= z2 z1 z0
c0 = 0 _____ c1 _____ c2 _____ c3 = carry out
--------|c d|-----------|c d|-----------|c d|-----------------
| | | | | |
x0-------|x | x1--|x | x2--|x |
| FA | | FA | | FA |
y0-------|y s|--| y1--|y s|--| y2--|y s|--|
|_____| |z0 |_____| |z1 |_____| |z2

Subtraction ______
_
For integers x, y, we use : x - y = x + y , where + and - are arithmetic.
Eg 15 - 5 = 1 1 1 1 . Perform 0 0 0 0 . Invert output to get 1 0 1 0 = 10 dec
- 0 1 0 1 + 0 1 0 1
= 0 1 0 1
Full Subtracter
Symbol Function Truth table Outputs Circuit
_____ _ _ _ _ c ______ d
|c d| arith s = x - y x y c s d s x s = x ⊕ y ⊕ c ---------------|c d|---------------
| | with carry in c 0 0 0 0 0 1 1 ___ _ | |
|x | and carry out d 0 0 1 1 1 0 1 _ _ x |NOT| x | FA |
| FS | 0 1 0 1 1 0 1 d = xy ⊕ xc ⊕ yc ---|___|-------|x | ___
|y s| 0 1 1 0 1 1 1 | | |NOT| s
|_____| 1 0 0 1 0 0 0 ---------------|y s|---|___|-------
1 0 1 0 0 1 0 y |_____|
1 1 0 0 0 1 0
1 1 1 1 1 0 0
_ _ _
noting s = 1 when 1 or all 3 of x,y,c = 1, and d = 1 when at least 2 of x,y,c = 1 .
____ _ _ _
Alternatively, s = x ⊕ y ⊕ c, and using a ⊕ b = a ⊕ b, we get s = x ⊕ y ⊕ c .
4.3 Sequential logic : The R-S Latch Page 4.3

The method we have used to build an adder is an example of COMBINATORIAL logic.

To build a memory store or to control the execution of events in sequence we need
SEQUENTIAL logic.
Sequential logic uses FEEDBACK. The OLD output from a feedback device is fed back into
the input to produce a NEW output.
The output is called the STATE of the device. The state depends on the current input and
the previous state, and by implication on the previous input.
Feedback devices go through a number of temporary TRANSITIONAL STATES before settling
down into a STEADY STATE. Some feedback devices have no steady state. We deal with those
that DO have a steady state.

The R-S Latch.

NOR circuit NAND circuit Symbol

___ ___ ____ _______
R------------| |------*-------Q S---|NOT|------| |------*-------Q | |
|NOR| | |NAND| | |R Q|
|-------|___| | |------|____| | | |
| | | | | _|
|------------------|---| |------------------|---| |S Q|
| | | | |_______|
|------------------| | |------------------| |
| ___ | | ____ |
|------| | | |------| | |
|NOR| | _ ___ |NAND| | _
S-----------|___|-----------*---P = Q R---|NOT|------|____|----------*----P = Q

Truth table: (R,S) = current input, (Q, P) = current output, (Qp, Pp) = previous output

R S Q P
__
NO CHANGE 0 0 Qp Qp PROVIDED previous input was not (1,1)

S = SET 0 1 1 0
R = RESET 1 0 0 1
NOT PERMITTED 1 1 0 0 NOR logic
1 1 NAND logic
If the input is changed from (1,1) to (0,0) there is theoretically no steady state.
In fact the device will flicker & then settle down into an INDETERMINATE steady state.
Thus an input of (1,1) means row 1 of the truth table ceases to hold, and moreover
produces outputs which are not complements of one another, and which depend on whether
NOR or NAND logic is used. An input of (1,1) must NOT be allowed to occur.
Use of the R-S latch as a memory store.
Suppose R = S = 0.
Changing S to 1 and back to 0 STORES 1 in the latch.
Changing R to 1 and back to 0 STORES 0 in the latch.
Thus the latch LATCHES onto its input and stores it.
The Clock.
A CPU has CLOCK that controls an OSCILLATOR whose output is a SQUARE WAVE.
1 cycle
_________
Signal | |
1| ____ ____ ____
| | | | | | |
| | | | | | |
| | | | | | |
0|____| |____| |____| |____ Time

The FREQUENCY of the clock in Hertz (Hz) is the number of cycles per second.
Note that the square wave is not exactly square since it is impossible to change signal
from 0 to 1 in zero time, but an oscillator generated "square" wave is very nearly square
Clocked R-S Latch Page 4.4
Circuit Symbol Function
___ R.Cl _____ _______
R------------|AND|---------|R Q|-----Q |R Q| R = S = 0 except on a clock pulse.
|-----|___| | | | |
| | | |> | No change to Q except on a pulse.
Cl-----* | | | _|
| ___ S.Cl | _| _ |S Q|
|-----|AND|---------|S Q|-----Q |_______|
S------------|___| |_____|

Cl denotes the square wave input from an oscillator controlled by a clock.

> denotes an input port for this "clock" input.
Edge triggered latches
Clocked latches are EDGE TRIGGERED. This means they are designed internally to respond
to a CHANGE in signal of the square wave they receive at their clock input port.
They are LEADING edge triggered if they respond to a change in signal from 0 to 1.
They are FALLING edge triggered if they respond to a change in signal from 1 to 0.
This means that the input signal to a clock port can be thought of as a PULSE.
On a pulse the input signal is momentarily raised from 0 to 1 and then falls back to 0.
For the clocked R-S latch R=S=0 except on a pulse, so Q is unchanged Q except on a pulse.
All latches in a CPU are clocked (pulsed) simultaneously.
For leading or falling edge triggered latches there is 1 clock pulse per clock cycle.
It is possible to design double edge triggered latches that respond to both the leading &
falling edges of the square wave signal so that there are 2 clock pulses per clock cycle.
AMD Athlon CPU's use double edge triggered latches and so can do more in 1 clock cycle.
4.4 Data latches and registers.
D-latch
Symbol Function Circuit _
_____ ___ D ______
|D Q| D = input D---*---|NOT|-----|R Q| Note that now we will never have R = S = 1.
| | Q = stored value | |___| | |
|> | | |> |
|_____| pulse stores input | D | |
|-------------|S |
|______|
Register
Symbol Circuit
____ _____ Z
|S Z| S ------*---------------------------------------------| |-----------------
| | | ______ | |
|D | D ------|----------- ----| D Q|---------------------| AND |
| | | ____ | | | |
|> | |-----| | | | |--|_____|
| | |AND | | | |
|RW | Cl -----------| |-----|> | |
|____| | | |______| |
|-----|____| ___ |
| |NOT| |
RW ------*----------------------------|___|----------
Function
S = SELECT S = 1 : RW = 1 (Write) : Z = 0, Pulse sets Q = D
D = DATA INPUT RW = 0 (Read) : Z = Q, Pulse leaves Q unchanged
RW = READ/WRITE
Q = STORED VALUE S = 0 : Z = 0, Pulse leaves Q unchanged
Z = OUTPUT
4.5 J-K latch, Toggle latch, Sequencer.
J-K
Symbol Truth table Circuit |-----------------------| Like an R-S with
_____ | ___ ____ | J as S, K as R
|J Q| J K Q |----|AND|-----|S Q|---*---Q
| | 0 0 Qp No change J-------------|___| | |
|> | 1 0 1 Set ___ |> | If J = K = 1
| _| 0 1 0 Reset K-------------|AND| | _| _ then a pulse TOGGLES
|K Q| __ |----|___|-----|R Q|---*---Q the stored value.
|_____| 1 1 Qp Toggle | |
|-----------------------|
J, K, Q are current input/output, Qp is previous output.
 T-Latch. Toggle with clear. Page 4.5
Symbol Function Circuit
___ ___ _______
T = input |-----|NOT|-----| |----|J Q|------Q
_____ Q = stored value | |___| |AND| | |
|T Q| | | | | |
| | CLR = 0 : J = K = T | |------------| | | |
|> | T = 1 : Pulse toggles Q T | | |___| |> |
|_____| T = 0 : Pulse leaves Q unchanged -------|--* | |
|CLR| | | ___ | |
CLR = 1 : J = 0 K = 1 | |------------| |----|K |
Pulse forces Q = 0 CLR | |OR | | |
-------*---------------|___| |_______|
3-bit sequencer SC
Symbol Circuit ^ b0 ^ b1 ^ b2
| | |
_____ E _____ | ___ E b0 _____ | ___ E b0 b1 _____ |
|E B| >-*--|T Q |---*---| |---*--|T Q|---*---| |---------|T Q|----|
| | | | | |AND| | | | |AND| | |
|> SC | | |> | |----|___| | |> | |---|___| |> |
|_____| | |_____| | | |_____| | |_____|
|CLR| | |CLR| | | |CLR| | |CLR|
| | | |
|-----------| |------------|

Function
B = (b2 b1 b0) = OUTPUT
E = ENABLE. If E = 1, a pulse increases b by 1 mod 8.
If E = 0, a pulse leaves b unchanged.
CLR = CLEAR If CLR = 0 a pulse forces b to zero.
Note that a pulse outputs a new b, but the feed forward feeds the old b into the
T-latches.
An n-bit sequencer implements the following rule for increasing bn-1...b2 b1 b0 mod 2n :
b0 is always complemented.
bi is complemented if bi-1 = bi-2 = ... = b2 = b1 = b0 = 1, i > 0.

4.6 Decoder and Multiplexer (Combinatorial circuits)

Decoder: 2 bit n bit
b0 ______ _______
------| |----A0 b | |-------A0
| 2 bit|----A1 Ai = 1 if (b1,b0) = i -------| n bit | --- Ai = 1 if b = i
b1 | dec |----A2 n bit | dec | ---
------|______|----A3 |_______|-------A2n - 1
__ __ __ __
A0 = b1 b0 A1 = b1 b0 A2 = b1 b0 A3 = b1 b0

Multiplexer: 2bit n bit

D0 D1 D2 D3 D0 D2n-1
| | | | | |
data data
b0 _|__|__|__|__ _|________|__
----------| | A = Di if (b1,b0) = i b | | A = Di if b = i
Select | 2 bit MUX |---------------------- -------| n bit mux |------------------
----------|_____________| n bit |_____________|
b1 select
__ __ __ __
A = D0 b1 b0 + D1 b1 b0 + D2 b1 b0 + D3 b1 b0