INTER IC SOUND(I2S)

PROTOCOL
INTRODUCTION
The protocol which is used to transmit digital audio data from one device to another
device is known as I2S or Inter-IC Sound protocol.
The digital audio signals in most systems are being processed by a number of devices, such as ADCs,
DACs, DSPs, Digital I/O interfaces, and many more.

In order for these devices to communicate audio data with each other a standard protocol
is required. One such is I2S protocol.
PINS
The I2S communication protocol is a 3 Wire protocol that simply handles audio data through a 3-line serial
bus which includes

1. SCK (Continuous Serial Clock), [mapped on SCK pin]

2. WS (Word Select) [mapped on NSS pin]
3. SD (Serial Data).[mapped on MOSI pin]
4. I2S2ext_sd & I2S3ext_sd :
a. Additional pin mapped on MISO pin. To control in full duplex pin.
5. MCK : Master clock
a. The clock generator(I2S) is the source of the master clock output.
I2S CLOCK GENERATOR ARCHITECTURE
Clock generation (contd.)
I2S bitrate = number of bits per channel × number of channels × sampling audio
frequency
bitrate determines the dataflow on the I2S data line and the I2S clock signal
frequency.
The I2S bitrate is calculated as follows:
I2S bitrate = 16 × 2 × FS if the packet length is 16-bit wide.
I2S bitrate = 32 x 2 x FS if the packet length is 32-bit wide.
FS - audio sampling frequency.
Clock generation (contd.)
The value of FS is configured with the formulas below:
When the master clock is generated (MCKOE in the SPI_I2SPR register is set):
FS = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16-bit wide
FS = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32-bit wide.
When the master clock is disabled (MCKOE bit cleared):
FS = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16-bit wide
FS = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32-bit wide
Four data and packet frames are available :

Data may be sent with a format of :

1. 16-bit data packed in 16-bit frame
2. 16-bit data packed in 32-bit frame
3. 24-bit data packed in 32-bit frame
4. 32-bit data packed in 32-bit frame
Four supported I2S protocols:

1. I2S Phillips standard

2. MSB-justified standard,
3. LSB-justified standard (right-justified),
4. PCM standard.
I2S Phillips standard :

16/32 bit data on 16/32 bit frame:

24 bit data on 32 bit frame:
MSB-justified standard :

16/32 bit data on 16/32 bit frame:

24 bit data on 32 bit frame:
LSB-justified standard :

16/32 bit data on 16/32 bit frame:

24 bit data on 32 bit frame:
PCM standard :

1. No channel-side information
2. Short and long frame formats (configure with PCMSYNC bit)
a. Long frame: WS asserted for 13 bits
b. Short frame : WS asserted for 1 bit
PCM standard - Wavaform
MODES OF TRANSMISSION :

1. Master - transmit mode,

2. Master - receive mode,
3. Slave- transmit mode,
4. Slave- receive mode.
BASIC REGISTER CONFIGURATION NEEDED :

Register Name : SPI_I2SCFGR

1. I2SSTD - I2S Standard:
1. I2SMOD: a. 00 = Philips,
a. 0 = SPI mode, b. 01 = MSB justified
b. 1 = I2S mode c. 10 = LSB justified,
d. 11 = PCM
2. I2SE:
a. 1 = enable I2S 2. DATLEN: data length:
a. 00 = 16-bit,
3. I2SCFG:
b. 01 = 24-bit,
a. 00 = slave xmit,
c. 10 = 32-bit (16-bit data register => 2
b. 01 = slave rcv,
reads for 24/32-bit data)
c. 10 = master xmit,
d. 11 = master rcv 3. CHLEN: word frame length:
a. 0 = 16-bit,
4. PCMSYNC:
b. 1 = 32-bit - LSBs = 0 for 16/24-bit data
a. used in PCM mode in 32-bit frame
5. CKPOL:
a. steady-state clock level (0/1)
I2s master mode:
In master mode for transmission and reception

- i2sx is used for Half duplex mode.

- I2sx and i2sx_ext are used for full duplex mode.

The master generated its own clock and ws signal.

Procedure:
1. Select the I2SDIV[7:0] bits (linear prescaler value) in the SPI_I2SPR register to define the serial clock baud
rate to reach the proper audio sample frequency.

2.The ODD bit (odd factor for the prescaler)in the SPI_I2SPR register also has to be defined.

3. Select the CKPOL bit to define the steady level for the communication clock.

4.Set the MCKOE bit in the SPI_I2SPR register if the master clock MCK needs to be provided to the external
DAC/ADC audio component.

5. Set I2SMOD bit in SPI_I2SCFGR to activate i2s functionality.

i2SSTD[1:0] $ PCMSYNC for standard.

DALEN[1:0] for data length.

CHLEN bit for channel length.

I2SCFG[1:0] bits for I2S master mode and its direction.

6. We must set I2SE bit in SPI_I2SCFGR register.

Transmission sequence
The sequence begins when a half-word is written into the Tx buffer.

First data is written into the TX buffer corresponds to channel left, when it is transferred to shift register,
then the data in channel right is written into TX buffer.

For every transaction TXE is set.

Here one full transaction means transmission of channel left data followed by channel right data.

The data half word is parallel loaded into the 16bit shift register during the first bit transmission and then
shifted out serially to the MOSI/SD pin, MSB first.

For continuous audio data transmission, it is mandatory to write the SPI_DR with the next data to
transmit before the end of the current transmission.

To switch off the I2S, by clearing I2SE, it is mandatory to wait for TXE = 1 and BSY = 0.
Reception sequence
The audio data are received by 16 bit packet.
This means that each time the Rx buffer is full, the RXNE flag is set and an
interrupt is generated if the RXNEIE bit is set in SPI_CR2 register.
Clearing the RXNE bit is performed by reading the SPI_DR register.
CHSIDE is updated after each reception. It is sensitive to the WS signal
generated by the I2S cell.
If we receive new data before the previous data is read an overrun error is
generated.(OVR flag is set, the ERRIE BIT is set in SPI_CR2 register an interrupt
is generated which indicates error ).
I2s slave mode:
In master mode for transmission and reception
- i2sx is used for Half duplex mode.
- I2sx and i2sx_ext are used for full duplex mode.
The clock and ws signal are input from the external master connected to I2S
interface.
Set I2SMOD bit in SPI_I2SCFGR to activate i2s functionality.
i2SSTD[1:0] $ PCMSYNC for standard.
DALEN[1:0] for data length.
CHLEN bit for channel length.
I2SCFG[1:0] bits for I2S master mode and its direction.
Transmission sequence

The sequence starts when the external master device send clock and ws signals.

The slave has to be enabled before the external master starts the communication. The I2S
data register has to be loaded before the master initiates the communication.(data in channel
left)

As the communication starts the data from the TX buffer is transmitted to shift register.

As the communication starts the data half-word is parallel-loaded into the 16-bit shift register
(from the internal bus) and then shifted out serially to the MOSI/SD pin MSB first.

The TXE flag is set after each transfer from the Tx buffer to the shift register and an interrupt is
generated if the TXEIE bit in the SPI_CR2 register is set.
Transmission sequence (contd.,)
For continuous transmission SPI_DR must be loaded with next data to be transmitted
before the end of the current transmission.
If the data is not loaded into the SPI_DR register before the first clock edge of the next
data communication an underrun error will be generated and UDR flag gets high.
If the ERRIE bit is set into the SPI_CR2 register, an interrupt is generated when the UDR
flag (underrun) in the SPI_SR register goes high.
In this it is mandatory to switch off the I2S and to restart a data transfer starting from
the left channel.
To switch off the I2S, by clearing the I2SE bit, it is mandatory to wait for TXE = 1 and
BSY = 0
Reception sequence
Configure the register into slave reception mode.
The data which is being received is stored in RX buffer. Then the RXNE flag is set and also an
interrupt is generated if the RXNEIE is set in the SPI_CR2 register.
The CHSIDE flag is updated each time data are received to be read from SPI_DR.
RXNE bit is cleared by reading the SPI_DR register.
If the new data is received before the previous data is read an overrun error is generated.
OVR bit is set and if ERRIE is set in the SPI_CR2 register an interrupt is generated to
indicate the error.
To switch off the I2S in reception mode, I2SE has to be cleared immediately after receiving the
last RXNE = 1.