Nama: Berlian Ishma Zhafira Sujana

NIM: 225150207111008
Kelas: A
Program Studi: Teknik Informatika
Mata Kuliah: Arsitektur dan Organisasi Komputer

Original 8086/8088 instruction set

Instructi
Meaning Notes Opcode
on

ASCII adjust AL after used with unpacked binary coded

AAA 0x37
addition decimal

8086/8088 datasheet documents

only base 10 version of the AAD
instruction (opcode 0xD5 0x0A), but
any other base will work. Later Intel's
ASCII adjust AX before documentation has the generic form
AAD 0xD5
division too. NEC V 20 and V 30 (and possibly
other NEC V-series CPUs) always
use base 10, and ignore the
argument, causing a number of
incompatibilities

Only base 10 version (Operand is

ASCII adjust AX after
AAM 0xA) is documented, see notes for 0xD4
multiplication
AAD

ASCII adjust AL after

AAS 0x3F
subtraction

destination := destination + 0x10… 0x15,

ADC Add with carry 0x80/2… 0x8
source + carry_flag
3/2

(1) r/m += r/imm; (2) r += 0x00… 0x05,

ADD Add 0x80/0… 0x8
m/imm;
3/0

(1) r/m &= r/imm; (2) r &= 0x20… 0x25,

AND Logical AND 0x80/4… 0x8
m/imm;
3/4
 Original 8086/8088 instruction set

Instructi
Meaning Notes Opcode
on

push eip; eip points to the 0x9A, 0xE 8,

CALL Call procedure instruction directly after 0xFF/2,
the call 0xFF/3

CBW Convert byte to word 0x98

CLC Clear carry flag CF = 0; 0xF8

CLD Clear direction flag DF = 0; 0xFC

CLI Clear interrupt flag IF = 0; 0xFA

CMC Complement carry flag 0xF5

0x38… 0x3D
,
CMP Compare operands
0x80/7… 0x8
3/7

CMPSB Compare bytes in memory 0xA 6

CMPSW Compare words 0xA 7

Convert word to
CW D 0x99
doubleword

Decimal adjust AL after (used with packed binary coded

DAA 0x27
addition decimal)
 Original 8086/8088 instruction set

Instructi
Meaning Notes Opcode
on

Decimal adjust AL after

DAS 0x2F
subtraction

0x48,
DEC Decrement by 1 0xFE/1,
0xFF/1

DX:AX = DX:AX / 0xF6/6,

DIV Unsigned divide r/m; resulting DX == remainder 0xF7/6

Used with floating-point

ESC
unit

HLT Enter halt state 0xF4

DX:AX = DX:AX / 0xF6/7,

IDIV Signed divide r/m; resulting DX == remainder 0xF7/7

0x69, 0x6B,
(1) DX:AX = AX * r/m; (2) AX = 0xF6/5,
IMUL Signed multiply
AL * r/ m 0xF7/5,
0x0FAF

(1) AL = port[ imm]; (2) AL = 0xE 4, 0xE 5,

IN Input from port port[DX]; (3) AX = port[DX]; 0xEC, 0xED

0x40,
INC Increment by 1 0xFE/0,
0xFF/0

INT Call to interrupt 0xCD

 Original 8086/8088 instruction set

Instructi
Meaning Notes Opcode
on

INTO Call to interrupt if overflow 0xCE

IRET Return from interrupt 0xCF

(JA, JAE, JB, JBE, JC, JE,

JG, JGE, JL, JLE, JNA, JNAE, 0x70… 0x7F,
JNB, JNBE, JNC, JNE, JNG, 0xE 3,
Jcc Jump if condition JNGE, JNL, JNLE, JNO, JNP, 0x0F83,
JNS, JNZ, JO, JP, JPE, JPO, 0x0F87
JS, JZ)

JCXZ Jump if CX is zero 0xE 3

0xE 9… 0xEB
JMP Jump , 0xFF/4,
0xFF/5

Load FLAGS into AH

LAHF 0x9F
register

LDS Load pointer using DS 0xC5

LEA Load Effective Address 0x8D

LES Load ES with pointer 0xC4

LOCK Assert BUS LOCK# signal (for multiprocessing) 0xF0

if (DF== 0) AL = *SI++ ; else A

LODSB Load string byte 0xAC
L = *SI--;
 Original 8086/8088 instruction set

Instructi
Meaning Notes Opcode
on

if (DF== 0) AX = *SI++ ; else A

LODSW Load string word 0xAD
X = *SI--;

(LOOPE, LOOPNE, LOOPNZ,

LOOP/LO LOOPZ) if (x && --
Loop control 0xE 0..0xE 2
OPx
CX) goto lbl;

copies data from one location to

MOV Move another, (1) r/m = r; (2) r =
r/m;

if ( DF==0)
*( byte*) DI++ =
*(byte*)SI++;
Move byte from string to
MOVSB else 0xA 4
string
*( byte*) DI-- = *( byte*) SI-
-;

if ( DF==0)
*( word*) DI++ =
*(word*)SI++;
Move word from string to
MOVSW else 0xA 5
string
*( word*) DI-- = *( word*) SI-
-;

(1) DX:AX = AX * r/m; (2) AX =

MUL Unsigned multiply
AL * r/ m;

Two's complement
NEG r/m *= -1;
negation
opcode equivalent to XCHG EAX,
NOP No operation 0x90
EAX
 Original 8086/8088 instruction set

Instructi
Meaning Notes Opcode
on

Negate the
NOT r/m ^= -1;
operand, logical NO T

(1) r/m |= r/imm; (2) r |= m/ im

OR Logical OR
m;

(1) port[imm] =
OUT Output to port AL; (2) port[ DX] =
AL; (3) port[ DX] = AX;

r/m = * SP++; POP CS (opcode

0x0F) works only on 8086/8088.
POP Pop data from stack
Later CPUs use 0x0F as a prefix for
newer instructions.
Pop FLAGS register from FLAGS = *SP++;
POPF 0x9D
stack

PUSH Push data onto stack *--SP = r/ m;

PUSHF Push FLAGS onto stack *--SP = FLAGS ; 0x9C

RCL Rotate left (with carry)

RCR Rotate right (with carry)
Repeat
(REP, REPE, REPNE, REPNZ,
REPxx MOVS/STOS/CMPS/LOD
REPZ)
S/SCAS
Not a real instruction. The assembler
will translate these to a RETN or a
RET Return from procedure
RETF depending on the memory
model of the target system.
RETF Return from far procedure
Return from near
RETN
procedure
ROL Rotate left
ROR Rotate right
SAHF Store AH into FLAGS 0x9E
Shift Arithmetically left (1) r/m <<= 1; (2) r/m <<= CL;
SAL
(signed shift left)

Shift Arithmetically right (1) (signed) r/m >>=

SAR
(signed shift right) 1; (2) (signed) r/m >>= CL;

alternative 1-byte encoding

SBB Subtraction with borrow of SBB AL, AL is available
via undocumented SALC instruction
 Original 8086/8088 instruction set

Instructi
Meaning Notes Opcode
on

SCASB Compare byte string 0xAE

SCASW Compare word string 0xAF
Shift left (unsigned shift
SHL
left)
Shift right (unsigned shift
SHR
right)
STC Set carry flag CF = 1; 0xF9

STD Set direction flag DF = 1; 0xFD

STI Set interrupt flag IF = 1; 0xFB

if (DF== 0) *ES : DI++ = AL; els

STOSB Store byte in string 0xAA
e *ES:DI-- = AL;

if (DF== 0) *ES : DI++ = AX; els

STOSW Store word in string 0xAB
e *ES:DI-- = AX;

(1) r/m -= r/imm; (2) r -=

SUB Subtraction
m/imm;

(1) r/m & r/imm; (2) r &

TEST Logical compare (AND)
m/imm;

Waits until BUSY# pin is inactive

WAIT Wait until not busy 0x9B
(used with floating-point unit)

r : = : r / m; A spinlock typically
XCHG Exchange data uses xchg as an atomic operation.
(coma bug).
XLAT Table look-up translation behaves like MOV AL, [ BX+AL] 0xD7
(1) r/m ^= r/imm; (2) r ^=
XOR Exclusive OR
m/imm;
Added in specific processors
Added w ith 80186 /80188

Instruction Meaning Notes

Check array
raises software interrupt 5 if
BOUND index against
test fails
bounds

Modifies stack for entry to

procedure for high level
language. Takes two
Enter stack
ENTER operands: the amount of
frame
storage to be allocated on the
stack and the nesting level of
the procedure.

equivalent to

IN ( E)AX, DX
Input from port to
INS MOV ES:[(E)DI], (E) AX
string
; adjust ( E)DI
according to operand
size and DF

Releases the local stack

Leave stack
LEAVE storage created by the
frame
previous ENTER instruction.
equivalent to

MOV (E) AX, DS:[( E)SI]

Output string to OUT DX, (E)AX
OUTS
port ; adjust ( E)SI
according to operand
size and DF

equivalent to

POP DI
Pop all general
purpose POP SI
POPA
registers from POP BP
stack POP AX ;no POP SP here,
only ADD SP,2
POP BX
 POP DX
POP CX
POP AX

equivalent to

PUSH AX
PUSH CX
PUSH DX
Push all general PUSH BX
purpose
PUSHA PUSH SP ; The value
registers onto
stack stored is the initial
SP value
PUSH BP
PUSH SI
PUSH DI

equivalent to
Push an
immediate
PUSH immediate PUSH 12 h
byte/word value
onto the stack PUSH 1200h

equivalent to

IMUL BX,12 h
IMUL DX,1200h
Signed IMUL CX, DX, 12h
multiplication of
IMUL immediate IMUL BX, SI, 1200h
immediate
byte/word value IMUL DI, word ptr
[BX+SI], 12h
IMUL SI, word ptr [ BP-
4], 1200h

equivalent to
Rotate/shift bits
SHL/SHR/SAL/SAR/ROL/ROR/RCL/RCR with an
ROL AX, 3
immediate immediate value
greater than 1 SHR BL, 3

Added w ith 80286

Instruction Meaning Notes

ARPL Adjust RPL field of selector

CLTS Clear task-switched flag in register CR0

LAR Load access rights byte

LGDT Load global descriptor table

LIDT Load interrupt descriptor table

LLDT Load local descriptor table

LMSW Load machine status word

Load all CPU registers, including internal ones Undocumented, 80286 and
LOADALL
such as GDT 80386 only

LSL Load segment limit

LTR Load task register

SGDT Store global descriptor table

SIDT Store interrupt descriptor table

SLDT Store local descriptor table

SMSW Store machine status word

STR Store task register

VERR Verify a segment for reading

VERW Verify a segment for writing

Added w ith 80386

Instruction Meaning Notes

BSF Bit scan forward

BSR Bit scan reverse

BT Bit test

Bit test and

BTC
complement

BTR Bit test and reset

BTS Bit test and set

Sign-extends EAX into EDX, forming the quad-word

Convert double-
EDX:EAX. Since (I)DIV uses EDX:EAX as its input, CDQ
CDQ word to quad-
must be called after setting EAX if EDX is not manually
word
initialized (as in 64/32 division) before (I)DIV.

Compares ES:[(E)DI] with DS:[(E)SI] and increments or

Compare string
CMPSD decrements both (E)DI and (E)SI, depending on DF; can be
double-word
prefixed with REP

Convert word to Unlike CW D, CW DE sign-extends AX to EAX instead of AX

CW DE
double-word to DX:AX

IBTS Insert Bit String discontinued with B 1 step of 80386

Input from port to

INSD string double-
word

Interrupt return;
IRETx D suffix means Use IRETD rather than IRET in 32 -bit situations
32-bit return, F
suffix means do
 not generate
epilogue code
(i.e. LEAVE
instruction)

Jump if ECX is
JECXZ
zero

LFS, LGS Load far pointer

Load stack
LSS
segment

Load string EAX = * ES: EDI±±; (±± depends on DF, ES cannot be

LODSD
double-word overridden); can be prefixed with REP

LOOPW , Loop, conditional

Same as LOOP, LOOP cc for earlier processors
LOOP ccW loop

LOOPD, if ( cc && --ECX) goto

Loop while equal
LOOPccD lbl; , cc = Z(ero), E (qual), N onZero, N (on)E (qual)

MOV
Move to/from CR=control registers, DR=debug registers, TR=test registers
to/from
special registers (up to 80486)
CR/DR/TR

Move string *(dword*)ES:EDI±± = (dword*) ESI±±; (±± depends on

MOVSD
double-word DF); can be prefixed with REP

Move with sign-

MOVSX (long)r = (signed char) r/m; and similar
extension

Move with zero- (long)r = (unsigned char) r/ m; and similar

MOVZX
extension

Output to port
OUTSD from string port[DX] = *( long*) ESI±±; (±± depends on DF)
double-word
 Pop all double-
word (32-bit)
POPAD Does not pop register ESP off of stack
registers from
stack

Pop data into

POPFD
EFLAGS register

Push all double-

word (32-bit)
PUSHAD
registers onto
stack

Push EFLAGS
PUSHFD register onto
stack

Compares ES:[(E)DI] with EAX and increments or

Scan string data
SCASD decrements (E)DI, depending on DF; can be prefixed with
double-word
REP

(SETA, SETAE, SETB, SETBE, SETC, SETE, SETG,

Set byte to one SETGE, SETL, SETLE, SETNA, SETNAE, SETNB,
SETcc on condition, SETNBE, SETNC, SETNE, SETNG, SETNGE, SETNL,
zero otherwise SETNLE, SETNO, SETNP, SETNS, SETNZ, SETO, SETP,
SETPE, SETPO, SETS, SETZ )

Shift left double-

SHLD
word

Shift right r1 = r1 >>CL ∣ r 2<<(32 -CL); Instead of CL, immediate

SHRD
double-word 1 can be used

Store string *ES: EDI±± = EAX; (±± depends on DF, ES cannot be

STOSD
double-word overridden); can be prefixed with REP

XBTS Extract Bit String discontinued with B 1 step of 80386

Added w ith 80486

Instructi
Meaning Notes
on

r = r<< 24 | r<<8 &0x 00FF0000 | r>>8 &0 x0000FF00 |

BSW AP Byte Swap
r>>24; Only works for 32 bit registers

CMPXCH atomic CoMPare See Compare-and-swap / on later 80386 as undocumented

G and eXCHanGe opcode available

Invalidate
INVD Flush internal caches
Internal Caches

Invalidate TLB E
INVLPG Invalidate TLB Entry for page that contains data specified
ntry

Write Back and Writes back all modified cache lines in the process or's internal
WBINVD
Invalidate Cache cache to main memory and invalidates the internal caches.

eXchange and Exchanges the first operand with the second operand, then
XADD
ADD loads the sum of the two values into the destination operand.

Added w ith Pentium

Instruction Meaning Notes

Returns data regarding processor identification and

CPU features, and returns data to the EAX, E BX, ECX, and
CPUID
IDentification EDX registers. Instruction functions specified by the EAX
register.[1] This was also added to later 80486 processors

CoMPare and Compare EDX:EAX with m64. If equal, set ZF and load
CMPXCHG8B eXCHanGe 8 ECX:EBX into m64 . Else, clear ZF and load m64 into
bytes EDX:EAX.

ReaD
RDMSR from Model- Load MSR specified by ECX into EDX:EAX
specific register
 Returns the number of processor ticks since the
ReaD Time
RDTSC processor being "ONLINE" (since the last power on of
Stamp Counter
system)

WRite to Model-
W RMSR Write the value in EDX:EAX to MSR specified by ECX
Specific Register

Resume from
This was introduced by the i386SL and later and is also in
System
RSM[2] the i486SL and later. Resumes from System
Management
Management Mode (SMM)
Mode

Added w ith Pentium MMX

Instruction Meaning Notes

Read the PMC [Performance Specified in the ECX register into

RDPMC
Monitoring Counter] registers EDX:EAX

Also MMX registers and MMX support instructions were added. They are usable for both integer
and floating point operations, see below .
Added w ith A MD K6

Instruction Meaning Notes

SYSCALL functionally equivalent to SYSENTER

SYSRET functionally equivalent to SYSEXIT

AMD changed the CPUID detection bit for this feature from the K 6 -II on.
Added w ith Pentium Pro

Instruction Meaning Notes

(CMOVA, CMOVAE, CMOVB, CMOVBE, CMOVC, CMOVE,

CMOVG, CMOVGE, CMOVL, CMOVLE, CMOVNA, CMOVNAE,
Conditional CMOVNB, CMOVNBE, CMOVNC, CMOVNE, CMOVNG,
CMOVcc
move CMOVNGE, CMOVNL, CMOVNLE, CMOVNO, CMOVNP,
CMOVNS, CMOVNZ, CMOVO, CMOVP, CMOVPE, CMOVPO,
CMOVS, CMOVZ)
 Generates an invalid opcode. This instruction is provided for
Undefined
UD2 software testing to explicitly generate an invalid opcode. The
Instruction
opcode for this instruction is reserved for this purpose.

Added w ith Pentium II

Instruction Meaning Notes

Sometimes called the Fast System Call instruction, this instruction

SYStem
was intended to increase the performance of operating system
SYSENTER call
calls. Note that on the Pentium Pro, the CPUID instruction
ENTER
incorrectly reports these instructions as available.

SYStem
SYSEXIT
call EXIT

Added w ith SSE

Instruction Opcode Meaning Notes

Selectively write bytes from mm1 to

MASKMOVQ Masked Move of
0F F7 /r memory location using the byte mask in
mm1, mm2 Quadword
mm2

Move packed single-precision floating-

Move Aligned Four
MOVNTPS m128, point values from xmm1 to m128,
0F 2B /r Packed Single-FP
xmm1 minimizing pollution in the cache
Non Temporal
hierarchy.

Move Quadword
MOVNTQ m64 ,
0F E 7 /r Using Non-Temporal
mm
Hint

NOP r/m16
Multi-byte no-
0F 1F /0
operation instruction.
NOP r/m32

Prefetch Data from

PREFETCHT0 0F 18 /1 Prefetch into all cache levels
Address
 Prefetch Data from Prefetch into all cache levels
PREFETCHT1 0F 18 /2
Address EXCEPT[3][4] L1

Prefetch Data from Prefetch into all cache levels EXCEPT

PREFETCHT2 0F 18 /3
Address L1 and L2

Prefetch Data from Prefetch to non- temporal cache

PREFETCHNTA 0F 18 /0
Address structure, minimizing cache pollution.

Processor hint to make sure all store

0F AE
SFENCE Store Fence operations that took place prior to the
F8
SFENCE call are globally visible

Added w ith SSE2

Instruction Opcode Meaning Notes

Invalidates the cache line that contains the

CLFLUSH 0F AE linear address specified with the source
Cache Line Flush
m8 /7 operand from all levels of the processor cache
hierarchy

0F AE
LFENCE Load Fence Serializes load operations.
E8

Performs a serializing operation on all load and

0F AE
MFENCE Memory Fence store instructions that were issued prior the
F0
MFENCE instruction.

Move
MOVNTI Move doubleword from r32 to m32 , minimizing
0F C3 /r Doubleword Non-
m32, r32 pollution in the cache hierarchy.
Temporal

Provides a hint to the processor that the

PAUSE F3 90 Spin Loop Hint
following code is a spin loop, for cacheability
Added w ith SSE3

Instruction Meaning Notes

Setup
Sets up a linear address range to be monitored by
MONITOR EAX, ECX, EDX Monitor
hardware and activates the monitor.
Address

Processor hint to stop instruction execution and

MWAIT EAX, ECX Monitor Wait enter an implementation-dependent optimized
state until occurrence of a class of events.

Added w ith SSE4.2

Instruction Opcode Meaning Notes

CRC32 r32, F2 0F 38
r/m8 F0 /r

F2 REX
CRC32 r32,
0F 38 F0
r/m8
/r

CRC32 r32, F2 0F 38
r/m16 F1 /r

Computes CRC value using the CRC-32C

CRC32 r32, F2 0F 38
(Castagnoli) polynomial 0x11 EDC6F41 (normal form
r/m32 F1 /r
Accumulate 0x1EDC6F41). This is the polynomial used in iSCSI.
CRC32 In contrast to the more popular one used in E thernet,
its parity is even, and it can thus detect any error with
F2 an odd number of changed bits.
CRC32 r64, REX.W
r/m8 0F 38 F0
/r

F2
CRC32 r64, REX.W
r/m64 0F 38 F1
/r

CRC32 r32, F2 0F 38
r/m8 F0 /r
Added w ith x86-64

Instruction Meaning Notes

CDQE Sign extend EAX into RAX

CQO Sign extend RAX into RDX:RAX

CMPSQ CoMPare String Quadword

CMPXCHG16B CoMPare and eXCHanGe 16 Bytes

IRETQ 64-bit Return from Interrupt

JRCXZ Jump if RCX is zero

LODSQ LOaD String Quadword

MOVSXD MOV with Sign Extend 32 -bit to 64-bit

POPFQ POP RFLAGS Register

PUSHFQ PUSH RFLAGS Register

RDTSCP ReaD Time S tamp Counter and Processor ID

SCASQ SCAn String Quadword

STOSQ STOre String Quadword

SW APGS Exchange GS base with KernelGSBase MSR

Added w ith A MD-V

Instruction Meaning Notes Opcode

Clear Global
CLGI Clears the GIF 0x0F 0x01 0xDD
Interrupt Flag

Invalidate TLB Invalidates the TLB mapping for the

INVLPGA entry in a specified virtual page specified in RAX and the 0x0F 0x01 0xDF
ASID ASID specified in ECX.

Move to or from Moves 32- or 64-bit contents to control 0x0F 0x22 or

MOV(CRn)
control registers register and vice versa. 0x0F 0x20

Move to or from Moves 32- or 64-bit contents to control 0x0F 0x21 or

MOV(DRn)
debug registers register and vice versa. 0x0F 0x23

Secure Init and

Verifiable startup of trusted software
SKINIT Jump with 0x0F 0x01 0xDE
based on secure hash comparison
Attestation

Set Global
STGI Sets the G IF. 0x0F 0x01 0xDC
Interrupt Flag

Loads a subset of processor state from

Load state From
VMLOAD the VMCB specified by the physical 0x0F 0x01 0xDA
VMCB
address in the RAX register.

Used exclusively to communicate with

VMMCALL Call VMM 0x0F 0x01 0xD9
VMM

Run virtual
VMRUN Performs a switch to the guest OS. 0x0F 0x01 0xD8
machine

Save state To
VMSAVE Saves additional guest state to VMCB. 0x0F 0x01 0xDB
VMCB
Added w ith Intel VT-x

Instruction Meaning Notes Opcode

Load Pointer to
Loads the current VMCS pointer from
VMPTRLD Virtual-Machine 0x0F 0xC7/6
memory.
Control Structure

Stores the current-VMCS pointer into

Store Pointer to
a specified memory address. The
VMPTRST Virtual-Machine 0x0F 0xC7/7
operand of this instruction is always 64
Control Structure
bits and is always in memory.

Clear Virtual-
VMCLEAR Machine Control Writes any cached data to the VMCS 0x66 0x0F 0xC7/6
Structure

Read Field from

VMREAD Virtual-Machine Reads out a field in the VMCS 0x0F 0x78
Control Structure

Write Field to
VMWRITE Virtual-Machine Modifies a field in the VMCS 0x0F 0x79
Control Structure

Call to VM Calls VM Monitor function from Guest

VMCALL 0x0F 0x01 0xC1
Monitor System

Launch Virtual Launch virtual machine managed by

VMLAUNCH 0x0F 0x01 0xC2
Machine current VMCS

Resume Virtual Resume virtual machine managed by

VMRESUME 0x0F 0x01 0xC3
Machine current VMCS

Leave VMX Stops hardware supported

VMXOFF 0x0F 0x01 0xC4
Operation virualisation environment

Enter VMX Enters hardware supported

VMXON 0xF3 0x0F 0xC7/6
Operation virualisation environment
Added w ith ABM
LZCNT, POPCNT (POPulation CouNT) - advanced bit manipulation

Added w ith B MI1

ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT

Added w ith B MI2

BZHI, MULX, PDEP, PEXT, RORX, SARX, SHRX, SHLX

Added w ith TB M
BEXTR, BLCFILL, BLCI, BLCIC, BLCMASK, BLCS, BLSFILL, BLSIC, T1 MSKC, TZMSK
Contoh implementasi bahasa pemrograman Assembly

Kode program di bawah merupakan implementasi aplikasi kalkulator sederhana (/, *, -, +)

menggunakan bahasa pemrograman Assembly. Baris 1-16 merupakan deklarasi berbagai variabel
yang digunakan dalam aplikasi. Baris 17 merupakan fungsi utama untuk menjalankan kode program
seperti fungsi main() pada bahasa lain. Baris 18-44 merupakan fungsi penghitungan: bagi, kali, kurang,
tambah. Baris 45-46 menandakan fungsi untuk menghentikan aplikasi. Baris 47-49 menandakan
bahwa kode program telah berakhir.

1 PAGE ,132
2 TITLE CALC
3 CGROUP GROUP CODESEG
4 CODESEG SEGMENT PARA PUBLIC 'CODE'
5 ASSUME CS:CGROUP,DS:CGROUP,ES:CGROUP
6 PUBLIC CALC

7 ORG 100H

8 CALC PROC FAR

9 JMP START

10 DB 'INTERRUPT NUMBER ='

11 INT_NUMBER DB 61h

12 SCREEN_HANDLE DW 0001h

13 MESSAGE DB 'PEMATH is not resident',13,10

14 MESSAGE_LEN EQU $-MESSAGE

15 TAG DB 'PEMATH'
16 TAG_LEN EQU $-TAG

17 START:
18 SUB AX,AX
19 MOV ES,AX
20 SUB BH,BH
21 MOV BL,INT_NUMBER
22 SHL BX,1
23 SHL BX,1
24 MOV DI,ES:[BX]
25 MOV ES,ES:[BX+2]
26 ADD DI,4
27 LEA SI,TAG
28 MOV CX,TAG_LEN
29 REPE CMPSB
30 JE CALL_CALC
31 MOV BX,SCREEN_HANDLE
32 MOV CX,MESSAGE_LEN
33 LEA DX,MESSAGE
34 MOV AH,40h
35 INT 21h
36 JMP SHORT CALC_EXIT

37 CALL_CALC:
38 MOV AL,INT_NUMBER
39 MOV BYTE PTR INT_CODE,AL
40 DB 0CDh ; INT
41 INT_CODE:
42 DB 00h
43 NOP
44 NOP

45 CALC_EXIT:
46 INT 20h
47 CALC ENDP

48 CODESEG ENDS
49 END CALC