194 IEEE Transactions on Consumer Electronics, Vol. 47, No.

1, FEBRUARY 2001

DESIGN OF DDFS-DRIVEN PLL FREQUENCY SYNTHESIZER WITH

REDUCED COMPLEXITY
Heung-Gyoon Ryu, Yun-Young Kim, Hyeong-Man Yu and Sang-Burm Ryu
Department of Electronic Engineering, Chungbuk National University
48 Kaesin-dong, Cheongju, Chungbuk, 361-763, Rep. of Korea

ABSTRACT level. And, in [3], it was proposed that replacing

DDFS-driven PLL synthesizer has a high
frequency resolution and wide frequency
bandwidth. Since the output of DDFS is a
synthesized analog signal, the waveform shaper
is needed to provide the digital input for a
DDFS-driven PLL synthesizer using the digital
type phase detector. Furthermore, a lot of
components in a DDFS unit can increase the
switching time and the power consumption. In
this paper, we propose a new design method of a
DDFS-driven PLL synthesizer, which does not
need the waveform shaper as well as the extra
circuits of DDFS. As a result, the proposed
method makes improvements such quality
factors as switching time and power con-
sumption, compared with the conventional
DDFS-driven PLL frequency synthesizer.
1. INTRODUCTION
DDFS (direct digital frequency synthesizer)
reconstructs the digital signal with a high-speed
DAC (digital-to-analog converter) to provide an
analog output signal and is used as a means of
generating the signal with performances of
exquisite step size, fast switching time, and
excellent spurious performance [ 11, For broad-
band applications, DDFS-driven PLL frequency
synthesizer is frequently employed.
Recently, there have been many researches on
techniques for thc frequency synthesis with such
high quality factors as fast switching speed, low
power consumption, low phase-noise, low spur-
ious level, and so on [2-71. In [2]: a method was
presented for reducing the spurious signal in a
fill1 DDFS structure by using a dithering signal.
However, there is no room to improve other
quality factors except for the reducing spurious
ROM (read-only memory or look-up table) with
nonlinear DAC could save the power con-
sumption. In spite of these efforts, there are
many problems to be improved when this DDFS
is used for DDFS-driven PLL synthesizer, since
DDFS-driven PLL synthesizer uses the fiill
DDFS structure. For the PLL,it is necessary to
digitize the analog output signal of DDFS by a
nonlinear device such as a hard limiter or
Sclimitt trigger, since the digital type phase
detector is used. This digitizing process can give
rise to rather increase the power consumption,
when the designed DDFS in 131 is used for
DDFS-driven PLL synthesizer. Therefore, when
we use the structure of DDFS-driven PLL, the
techniques presented in [2] and [3] can not
sufficiently improve the quality factors of
frequency synthesizer.
In this paper, we propose a new structure of
DDFS that has a significantly reduced structurc
as compared with the conventional DDFS.
Because only the complexity of DDFS is
drastically reduced in the proposed method for
thc performance improvement, it does not need
any technique for reducing the power con-
sumption. In other words, the proposed mcthod
can simukaneously reduce the circuit complexity
and power consumption, without process of [3],
Furthcrmore, the proposed synthesizer provides
faster switching speed than the conventional one.
Additionally, another scheme is investi- gated to
provide the digital reference with low jitter.
2. CONVENTIONAL DDFS-DWVEK
PLL FREQUENCY SYNTHESIZER
Conventional DDFS-driven PLL synthesizer is

Contributed Paper
Original manuscript received January 17, 2001 0098 3063/00 $10.00 2001 IEEE
 ct al.: Design of DDFS-Driven PLL Frequency Synthesizer with Reduced Complexity
RYLI
. Phase
N-2
ROM
N;'
,.
I7L7 -accumulator /(
1st MSB fl
T
Fig. 1 Conventional DDFS-driven PLL frequency synthesizer
shown in Fig.1. The input to tlie accumulator is
the frequency control word. Since this word
represents an N-bit digital value, the output
frcqucncy of DDFS, f b , is changed by variation
of input control word. The relationship between
the output frequency f o , and the input word, W .
is represented by
where fCLK is thc clock frequency. The phase
accumulator is a digital integrator and generates
the digital ramp output by pcrforming the
arithnietic function
S(n) = S(n - 1) + w
where S(n) and S(n - 1) represent the present
and the previous accumulator output. Eq. (2)
shows that the amount of accumulated phase is
irregularly changed as W is increased. This
becomes one of the main factors to generate the
discrete spurs in DDFS - it is considered as
phase jitter in a digital signal - in the output of
DDFS.
The ROM or look-up table converts the phase
into its equivalent aniplitude. In this con-
version, the quantization error is necessarily
generated. Furthermore. this ROM would
consume most of the power in this conversion
that usually uses a large look-up table. In D/A
conversion, there is additional power con-
sumption. Therefore, it is necessa3-y to provide a
countermeasure for this large power con-
sumption.
The hard limiter, which interfaces DDFS with
PLL, converts thc output of DAC to digital
195
> D/A f,\ Hard PLL -+
i converter ; hter +
OlltPUt
reference signal for PLL. Of course: when the
analog phase detector type PLL is used; this
procedure is not needed. However, since the
analog phase detector type PLL has a very large
size in circuit dimension [4], it is not appropriate
for applications of portable unit. Therefore, the
digital phase detector type PLL is preferred and
we are going to use this PLL in this paper. As an
input of the PLL: the digital waveform shaping
is necessary. There is an effect of non-ideal hard
limitation on the system performance such as thc
increase of the power consumption.
3. PROPOSED DDFS-DRTVEN PLL
FREQUENCY SYNTHESlZER
(2)
In the previous section, we investigated the
major portions of the performance degradation
in conventional DDFS-driven PLL synthesizer.
As shown in Fig. 1, the phase accumulator has
an N-bit input and (N-2)-bit output words. The
two MSBs of the accuiiidator output bits are
used to control the output waveform. In other
words, the first and second MSBs are used to
control the phase of 90" and 180", respectively.
It is easily found that the period of the first MSB
is equal to that of the DDFS output siiyial. That
is: the output frequency of DDFS is determined
by the first MSB of the accumulator output.
Therefore, f =1iT.
Hence, in a DDFS-driven PLL synthesizer,
the MSB of accumulator output is most appro-
priate for the input of PLL, because the
digitizing process is needless.
 IEEE Transactions on Consumer Electronics, Vol. 47, No. 1, FEBRUARY 2001

+
IstMSB frequency
DDS output 5
H
T=l/fo
Fig. 2 Proposed DDFS-driven PLL frequency synthesizer

Furthermore, such as ROM, D/A converter,

and hard limiter are not necessary, as shown in 4. SIMULATION RESULTS
Fig.2. Also, the effects of t h o x devices on the
system performance can be removed without
other manipulations. As compared with the con-
ventional DDFS-driven PLL synthesizer in Fig. 1,
since only a phase detector is used for DDFS in
Fig.2, the proposed synthesizer has the advan-
tages as follows: 1) The switching time can be
greatly shorten by removing the delay time at
each device. 2) The circuit complexity becomes
very simple and the power consumption can be
dramatically reduced.
Since the phase jitter of DDFS is generated by
the irregularly accumulated phase, we can not
make the jitter-free signal with the above
method. An alternative scheme to provide the
jitter-free signal is shown in Fig.3. This DDFS
unit uses two phase-accumulators. The second
stage takes the output carry of the first stage as
input. It does function as a noise-shaper. Even if
the first stage outputs the signal with the phase
error, the second phase accumulator generates
the jitter-free signal. Therefore, it is very
appropriate for applications of DDFS-driven
frequency synthesis.

77 ac cumulatar

Conventional Proposed
Required Transistors Transistors
accumulator devices (2428) (1804)
(pieces) Analog Analog
devices(35) devices(0)
j itter-f re e signal
Switching 33.144 12.654
time(ys) /2.2MHz step /2.2MHz step
Fig. 3 Jitter-free DDFS unit
I I I
Ryu et al.: Design of DDFS-Driven PLL Frequency Synthesizer with Reduced Complexity
....................1 .................
4fl” .~ - 1
I I
1 I
I
I I
........ ........ ~. .... .:..... ..
i 1
.,.................. ‘i ...................
I I
0 U .I. ........;.. ....... j ........ .j
OS 2”
Tine
Fig.4 Loop filter output
Next, the switching speed is generally defined
as inverse of the required maximum time to
switch and settle from one frequency to aiiothcr
frequency within its operating range. Here, we
consider the switching time as the required time
to switch fromW=l toW=15, when fcLK=10
MHz. The switching speed is specified at 2.2
MHz frequency step. As a result, for thc above
frequency step, the conventional DDFS takes
33.14411s (Table l), while the proposed one does
12.654ps. It means that the conventional one
takes the switching time approximately 2.62
times longer than the proposed method. If the
switching time of PLL is constant, the switching
speed of DDFS-driven PLL synthesizer depends
on only the DDFS unit. Fig. 4 shows the loop
filter output of PLL. It means that it is possible
for the proposed method to lock toward the
desired frequency likc the conventional frc-
quency synthesizer. Therefore, the proposed
method can lock within the desired frequency
range in addition to faster switching speed and
sinaller power consumption.
Finally, we investigated how much the noise
shaper of Fig. 3 can reduce the phase jitter. Fig.5
shows the outputs of the accumulator output
when W = l . In case of the conventional
accumulator of Fig. 5(a), there is obvious phase
jitter. This phase jitter causes the terrific phase
noise in the PLL. On the contrary, the phase
accumulator using noise shaper provides the
jitter-free reference to the PLL (see Fig. 5(b)).
Thereforc, if the PLL maintains the desired
phase noise level, this DDFS-driven PLL
frequency synthesizer can maintain the least
phase noise performance.
I97
I
I I
I I
I I
i I I
I I
I I
I I
I I
I I
I I
I I
I I
I I
I I I
! I
........ I -40011s -200ns Os 20011s
4”
eye-sweep(426ns,90nsl
(a) Jittered signal from the conventional
phase accumulator
I
I
I
-ov5u+-------------- r-------------- i
-20~s ns 2 0us
e y e - s w e e p ( 2 7 . 3 ~ ~1~us)
(b) Jitter-free signal from the noise shaper
Fig. 5 Reduced jitter by noise shaper
5. CONCLUSIONS
In this paper, we have investigated the
problems of the conventional DDFS-driven PLL
synthesizer. Because of these drawbacks, the
conventional DDFS causes larger power con-
sumption, circuit complexity, and switching time.
To overcome the above drawbacks, we have
proposed the DDFS-driven PLL synthesizer with
reduced complexity and verified the improved
performance for the switching speed and power
consumption. In addition to these results, we
have introduced the noise shaper, which is a
method to reduce the phase jitter. On the
contrary to the general phase accumulator, the
noise shaper has provided the jitter-free
reference to the PLL.
From the above results, if the more frequency
control word bits are used for fine resolution, it
is expected that the power consumption, swi-
198 IEEE Transactions on Consuiner Electronics, Vol. 47, No. 1, FEBRUARY 2001
tching speed, and circuit complexity arc more
improved.
REFERENCES
111 B-G. Goldberg, Digital Techniques in
Frequency Synthesis, McGraw-Hill. 1996.
[2] M. Flanagan and G.A. Zimmerman,
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thesis,” IEEE Transactions on Communi-
cations, vo1.43, no.7, pp. 2254-2262, July
1995.
[3] S. Mortezapour and E.K.F. Lee, ”Design
of Low-Power ROM-Lcss Direct Digital
Frequency Synthesizer Using Nonlinear
Digital-to-Analog Converter, “IEEE .Jour-
nal on Solid-state Circuits, vol. 34, no. 10,
pp. 1350- 1359, October 1999.
[4] K. Tajima, Y. Imai, Y. Kanagawa, and K.
Itoh, ”A 5 to l0GHz Low Spurious Triple
Tuned Type PLL Synthesizer Driven by
Frequency Converted DDS Unit,” ZEEE
MTT-S International, vol. 3, pp. 1217-
1220, 1997.
151 T. Saba, D.K. Park, and S. Mori, ”Fast
Acquisition PLL Frequency Synthesizer
with Improved N-Stage Cycle Swa-
llower,” IEEE ISSSTA ‘94, v01.2, pp.352-
356, 1994.
[6] Y. Sumi: S. Obote, N.fitai: H. Ishii, and
R. Furuhashi,”PLL Synthesizer with
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[7] D. Wulich, ‘‘ Fast Frequency Synthesis by
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BIOGRAPHIES
Heung-Gyoon Ryu was
born in Seoul, Korea in
1959. He received the B.S.
and M.S. and Ph.D.
degrees in electronic engin-
eering from Seoul National
University in 1982, 1984
and 1989. Since 1988, he
has been with Chungbuk
National University, Korea, where he is
currently professor of electrical and electronic
department. His main research inteiests are in
the field of digital communication systems,
circuit design, spread spectrum system and
communication signal processing.
Yun-Young Kim was
born in Koesan, Korea in
1975. He received the B.S.
degree in the department
of electrical and electro-
nics engineering from
Chungbuk National Uni-
versity in February 2000.
He is currently working
towards M.S. degree on digital communication
system. HIS research interests also include
frequency synthesizer & modem design and
spread-spectmm systems.
. . .. . . . . . . . . . . .. . . ... . . .
Hyeong-Man Yu was
born in Cheongp, Korea in
1974. He received the B.S.
degree in the department of
electrical and electronics
engineering from Chung-
buk National University in
February 2000. He is
currently working towards M.S. degree on
digital communication system. His research
interests also include frequency synthesizer
design and LPI & AJ systems.
Sang-Burm Ryu was born
in Geumsan, Korea in 1971
He received B.S. degree
from Daejon National
University of Technology in
February 1996. He is
currently working towards
M.S. degree in the depart-
ment of electronic engineering, Chungbuk
National University. He is currently working on
digital modem design. His research interests also
include direct digital frequency synthesis and
digital F
G communication and CDMA.