Master Slave Flip Flop:

Source: M. Morris Mano, Digital Design, Prentice-Hall, Inc

A master slave JK flip is a cascade of two SR Flip Flop with feedback from the output of the
second to the input of the first as illustrated in the figure. Positive clock pulse are applied to
the first flip flop and clock pulse are inverted before these are applied to the second flip flop.
When clock =1, the first flip is enabled and the output Y and Y´ respond to the inputs J and K.
At this time the second flip flop is disabled because its clock is low ( Clk=0). When clock goes
low the first flip flop is disabled and second is enabled. Therefore output Q and Q’ follows the
output Y and Y’. Since the second simply follow the first one, it is referred to as the slave and
the first one as the master. Hence this configuration is referred to as the Master Slave Flip Flop.
The Master-Slave combination can be constructed for any type of flip flop by adding a clocked
RS flip flop with an inverted clock to form the slave. An example of master slave JK flip flop
constructed with a NAND gate is shown in the figure above. It consists of two flip flop. Gate
1 through 4 form the Master flip flop and gate 5 through 8 form the slave flip flop. The
information present at the J and K inputs is transmitted to the master flip flop on the positive
edge of the clock pulse and is held there until the negative edge of the clock pulse occurs, after
which it is allowed to pass through the slave flip flop. The clock input is normally 0 which
keeps the output of gate 1 and 2 at the 1 level. This prevents the J K inputs from affecting the
master flip flop. The slave flip flop is clocked RS type with the master flip flop supplying the
inputs and the clock input being inverted by gate 9. When the clock is 0 the output of gate 9 is
1, so that the output Q = Y and Q’ = Y’. When the positive edge of clock pulse occurs the master
flip flop is effected and may switch states as per the input J and K. The slave is isolated as long
as the clock is at the level 1, because the output of gate 9 provides a 1 to both inputs of the
NAND basic flip flop of gates 7 and 8. When the gate inputs returns to 0 the Master flip flop
is isolated from J and K inputs and the slave flip flop goes to the same state as the master flip
flop.

J K Yt+1 Y’t+1 Qt+1 Q’t+1

0 0 Yt Y’t Qt Q’t
0 1 0 1 0 1
1 0 1 0 1 0
1 1 Y’t Yt Q’t Qt

Edge Triggered Flip Flop :

Positive edge triggered D Flip Flop:

Source: M. Morris Mano, Digital Design, Prentice-Hall, Inc