Faculty of Environment and Technology

Academic Year: 17/18

Examination Period: Summer

Module Leader: John C. Sullivan

Module Code: UFMFR8-15-1
Module Title: Digital Principles for Robotics

Duration: 2 Hours

Standard materials required for this examination:

Examination Answer Booklet Yes

Multiple Choice Answer Sheet No

Type of paper e.g. G3, G14 N/A
Graph Paper
Number of sheets per student 0

Additional materials required for this examination:

Details of additional material supplied by UWE Bristol: Formula Sheet

To be collected with Answer Booklet (please delete as appropriate) No

Details of approved material supplied by Student: None

To be collected with Answer Booklet (please delete as appropriate) No

University approved Calculator Yes

Candidates permitted to keep Examination Question Paper Yes

Candidates are NOT permitted to turn the page

over until the exam starts

UFMFR8-15-1 Page 1 of 8
__________________________________
Instructions to Candidates:

Candidates must answer the TWO questions of Section A AND any TWO questions
from Section B
____________________________________

SECTION A

QUESTION 1 [25 marks]

Figure Q1(a): Segments LED Display

A 7-segment display consists of seven segments - LEDs - as illustrated in Figure Q1(a). In

order to produce the desired Decimal/Hex number, the correct combination of segments
should be selected. For example, if a decimal ‘2’ is to be displayed, segments ‘a’, ‘b’, ‘g’ ‘e’
and ’d’ are selected. The complete sequence of Hex numbers is shown in Figure Q1(b).

Figure Q1(b): Complete Sequence of Hex Numbers

Segment ‘b’ is ON (equal to 1) for some digits and is OFF (equal to 0) for others. Our goal
is to find the digital circuit that will control the behaviour of segment ‘b’.

a. Considering that the digital system has FOUR inputs, derive the truth table that
corresponds to segment ‘b’. Then, write down the associated Boolean expression
(Sum of Products).
[8 marks]

b. Simplify the Boolean expression derived in a) using a K-map, then draw the
corresponding circuit using 2-input AND and OR gates.
[10 marks]

c. Write a VHDL programme that implements this digital system as simplified in b) using
only 2-input gates. The use of signals is mandatory.
[7 marks]

UFMFR8-15-1 Page 2 of 8
QUESTION 2 [25 marks]

a. What are the main two architectures available in microcontrollers? State briefly the
main differences between them.
[5 marks]

b. Why do you think that a watchdog timer is important in an embedded application?

Explain briefly how it works.
[5 marks]

c. The PIC16F877’s analogue to digital converter (ADC) is used to regularly convert N

samples from an external temperature sensor. Upon completing a conversion (N
samples), an interrupt is triggered and the average of these N samples is then
calculated.

Explain how the interrupt system works in the case of the PIC16F877 using the ADC
example. At what point is the stack involved? What is its role? What do ‘context save’
and ‘context restore’ mean? What is the role of the interrupt service routine (ISR)?
What does it implement in this particular case?

[8 marks]

d. Consider the two pieces of code of Figure Q2. The dotted lines represent
instructions. ‘Table’ is a subroutine.

i. Explain the difference between a “call” instruction and a “goto” instruction.

[3 marks]

ii. What should be the last instruction in the subroutine of Figure Q2(a) - just
before the ‘end’ statement?
[2 marks]

iii. What should be the last instruction in the subroutine of Figure Q2(b) to get the
same behaviour of that of the code of Figure Q2(a)?
[2 marks]

…………. ………….
…………. ………….
call Table goto Table
…………. ………….
…………. ………….
Table ………….. Table ………….
………….. ………….
………….. ………….
………….? ………….?
end end

(a) (b)
Figure Q2

UFMFR8-15-1 Page 3 of 8
SECTION B

QUESTION 3 [25 marks]

a. Perform the conversions to complete Table Q3(a). You should show your working
calculations.
[6 marks]

Decimal Binary Hex

10110
37
1A6
Table Q3(a)

b. What is the largest decimal number value that can be represented by an 8-bit binary
number? Show your working calculations.
[2 marks]

c. Consider the following truth table.

a b c s
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

i. Write the Boolean equation that describes the circuit represented by the truth
table.
[5 marks]

ii. Check that the logic circuit of Figure Q3(a) implements actually the same logic
function (fill Table Q3(b)).
[5 marks]

UFMFR8-15-1 Page 4 of 8
 a b c
a.b a b c a.b a.c b.c s
0 0 0
0 0 1
a.c 0 1 0
s 0 1 1
1 0 0
b.c 1 0 1
1 1 0
1 1 1
Figure Q3(a) Table Q3(b)

d. The waveforms illustrated in Figure Q3(b) are applied to the logic circuit of Figure
Q3(c). Determine the output waveform X.
[7 marks]

a a a.b

b b
b+c X
c
c
Figure Q3(c)
Figure Q3(b)

QUESTION 4 [25 Marks]

An asynchronous MOD-8 counting up circuit using negative edge triggered JK flip flops is
shown in figure Q4, where a falling edge clock signal is applied to the first JK flip flop only.

'1' '1' '1'

SET
Q0 SET
Q1 SET
Q2
J Q J Q J Q

K CLR Q K CLR Q K CLR Q

Figure Q4: Counting up MOD-8 Asynchronous Circuit

a. What makes the counter asynchronous?

[2 marks]

UFMFR8-15-1 Page 5 of 8
b. If the period of the clock signal is Tc = 0.5 milliseconds, what is the period of the clock
signal at the input of the second flip flop? What is then the period of the output signal
Q2 of the third flip flop? How many flip flops are required so that the clock signal at
the input of the last flip flop is 16 times of that at the input of the first one?
[6 marks]

c. The counter of figure Q4 is used to implement a MOD-5 counter. Draw the state
diagram of this MOD-5 counter and its corresponding logic circuit.
[6 marks]

d. Using the same procedure as for the counter of figure Q4, draw the logic circuit
corresponding to a counting down circuit (from 7 down to 0).
[6 marks]

e. Explain how 2- input multiplexers can be used to implement a counting up/down

MOD-8 counter (combining counting up and counting down counters).
[5 marks]

QUESTION 5 [25 Marks]

A MOD-5 synchronous counter is required.

a. When do we consider a system (for example a counter) to be synchronous?

[2 marks]

b. Draw a transition diagram showing all possible states and set up the table that lists
all present states and their corresponding next states for the MOD-5 synchronous
counter.
[4 marks]

c. Expand the table to include all the J and K inputs to the three flip flops. Use Table
Q5 for this purpose.
[6 marks]

d. Derive the K-map for every input (J1, J2, J3, K1, K2 and K3) and write down the
corresponding Boolean equations.
[9 marks]

e. Draw the corresponding logic circuit

[4 marks]

UFMFR8-15-1 Page 6 of 8
 Transition at PRESENT NEXT State J K
the Output State Q(N) Q(N+1)

00 0 0 0 x
01 0 1 1 x
10 1 0 x 1
11 1 1 x 0

Table Q5. Transition Table of a JK Flip Flop

QUESTION 6 [25 Marks]

The flowchart of the “main” code to implement a counting up/counting down system is
illustrated in Figure Q6. After initialising a set of registers, the “main” keeps waiting for a
pushbutton to be pressed. Once it is done and depending on the pushbutton being
pressed, the main will call either an increment subroutine or a decrement subroutine.
Pushbutton 1 corresponds to bit 0 of PORTB and pushbutton 2 corresponds to bit 1 of the
same port.
(hint: to test the pushbuttons use either BTFSC or BTFSS).

a. Write the assembly code to implement the main part of the system as illustrated by
the flowchart of Figure Q6. Note that INC and DEC are calls to two subroutines for
incrementing and decrementing.
[12 marks]

b. Consider the code in Table Q6. Add comments as necessary to the code. Draw the
corresponding flowchart and explain what the code is actually implementing.

[13 marks]

Start

YES YES YES

Button1 = 0 Call Delay Button1 = 0 INC Button1 = 1

NO NO NO

YES YES YES

Button2 = 0 Call Delay Button2 = 0 DEC Button2 = 1

NO
NO

Figure Q6

UFMFR8-15-1 Page 7 of 8
;**********************************************************************
include "P16F877.INC" ;

OUTREG EQU H'0020'

outval EQU H'0100'
INREG EQU H'0021'
Inval EQU H'0100'
;**********************************************************************
banksel TRISD
clrf PORTD
banksel PORTD
;**********************************************************************
start movlw 0
movwf PORTD
loop incf PORTD, F
call Delay
nop
goto loop
;*********************** Delay Subroutine *****************************
Delay movlw outval
movwf OUTREG
time2 movlw inval
movwf INREG
time1 decfsz INREG, f
goto time1
decfsz OUTREG, f
goto time2
return
end
Table Q6

END OF EXAM PAPER

UFMFR8-15-1 Page 8 of 8