10

Fundamentals of Integrated Circuit Fabrication

Outline

10-1 Introduction
10-2 Fundamentals of Integrated Circuits
10-3 Types of Integrated Circuits
10-4 Advantages and Disadvantages of Integrated Circuits
10-5 Scale of Integration
10-6 Crystal Growth and Wafer Preparation
10-7 Epitaxial Growth
10-8 Oxidation for Isolation
10-9 Photolithography for Pattern Transfer
10-10 Etching for Design
10-11 Diffusion for Doping
10-12 Ion Implantation for Doping
10-13 Metallization for Interconnection
10-14 Testing for Reliability
10-15 Packaging Protection
10-16 IC Symbols
10-17 Fabrication Steps for Different Circuits
10-18 Real-Life Applications

Objectives

This chapter deals with the fundamentals of integrated circuit fabrication. In the field of
nanotechnology, this basic idea of fabrication is very important from the point of view of
semiconductor device engineering. Semiconductor device fabrication is the process used to create
chips for devices that are a part of our everyday use. It is a multiple-step sequence of
photographic and chemical processing during which electronic circuits are gradually created on a
wafer substrate made of pure semi-conducting material. In this chapter, readers will learn how
integrated circuits are designed and fabricated. The topics include electronic fundamentals,
crystal growth and wafer types, transistor types, basic design concepts, mask making, wafer
 processing, materials used for fabricating the wafer, equipments used for processing the wafer,
clean room standards, testing and reliability control, assembly and packaging, and different IC
types.

10-1 INTRODUCTION

In the world of semiconductor devices and integrated circuits, silicon is the commonly used
semiconductor material, and it is mostly used as a substrate material. For example, solar cells made
of silicon wafers are cheaper and can be used for practical applications by common people. Of late,
it has been observed that GaAs fabrication has advanced compared to silicon due to its greater
thermal stability, direct band gap and higher electron mobility. However, GaAs fabrication is a
difficult process and the cost incurred is also very high.
Today compound semiconductors are the main point of attraction. IV–IV, III–V and II–VI are the
common compound semiconductors used in research and industry. Among these the compound
semiconductor III–V is widely used as it has multiple applications in LED, LASER, etc. Excimer
lasers are ideal sources for large-area patterning, lithographic processes, TFT display annealing and
LED laser lift-off. Micromachining is a broad application sector in which both excimer and DPSS
lasers are used. Silicon, sapphire, polymers, CVD diamond, III–V semiconductors—gallium arsenide
(GaAs), indium phosphide (InP), gallium phosphide (GaP) and III-nitrides gallium nitride (GaN) and
aluminum nitride (AlN)—are materials routinely machined by both these lasers in applications such
as structuring, drilling, dicing and cutting. Optoelectronic devices using III–V compound
semiconductor materials are increasingly becoming central to optical communications. One of the III–
V materials systems on which they are based—indium phosphide (InP)—is of particular importance
because it enables devices with the crucial cost and performance characteristics that system vendors
require and will be required in the future. InP provides monolithic integration of multiple functions
(e.g., lasers, modulators, and optical attenuators) on a chip, and offers high-performance low-cost
solutions. InP is a very compact, low-cost technology for 2.5 Gbit/sec and medium-reach systems
operating at 10 Gbit/sec for metro transmission.
Band-gap energies of II–VI semiconductors span a wide range of electromagnetic spectrum, with
the band-gap energy of HgTe (0 eV) at the lower end of the spectrum to BeSe (6 eV) at the other
extreme of the spectrum. The large band-gap energy II–VI compounds are sensitive to wavelengths in
the visible and ultraviolet region of the electromagnetic spectrum. Its main applications lie in
electroluminescent phosphorous, solar cells, IR sensors based on HgCdTe, and blue laser diode using
ZnSe. In recent years the grand success in the field of GaN-based III–V material has reduced the
interest in the development of the ZnSe-based blue laser diode. Moreover doping is a big problem in
the II–VI material. It has been observed that the II–VI-based diodes are not stable for long-duration
applications, and their usage in solar cells results in lower efficiency. Nowadays II–VI
semiconductors are popular in the investigation of spintrinics and dilute magnetic semiconductors
(DMS). The most common DMS are CdTe, CdSe, ZnSe and CdS used with transition metal ions such
as Mn, Fe and Co forming the alloys like CdXTe, ZnXSe where, X = Mn, Fe and Co. These structures
are suitable for studying carrier transport. But the main problem of II–VI is that it uses III–V as the
only suitable substrate for the growth of the nanostructures.

10-2 FUNDAMENTALS OF INTEGRATED CIRCUITS

The fabrication of integrated circuits is an art. From the age of LSI (large-scale integration) to VLSI
(very-large-scale integration), the device dimension has reduced by a large amount, but at the same
time its switching speed has increased. ULSI (ultra-large-scale integration) is used for low-
dimensional nanostructure devices. Nowadays, the use of MBE (molecular beam epitaxy), MOCVD
(metal-organic chemical vapour deposition) and CBD (chemical bath deposition), make it possible to
fabricate the nanostructure semiconductor devices in the form of Quantum Well, Quantum Wire and
Quantum Dot. Nano devices are typically 1–100 nm (in each direction) in dimension. The smaller the
devices, greater is the challenge of fabrication due to the new electronic properties of these devices.

Figure 10-1 Comparative diagram of development of the BJT/MOS vs. year

Figure 10-2 Components/chip vs. year

 Figure 10-3 Minimum size vs. year

As shown in Fig. 10-1, there has been a shift from the bipolar technology to the MOS technology. A
projection up to the year 2010 shows that an approximate 95 percent of the market will be composed
of MOS devices, and the remaining 5 percent will be bipolar. The bold arrowhead line shows the
average trend line in the figure.
With devices getting smaller and smaller, the number of their components/chips has been
increasingly getting bigger and bigger with time. A plot in Fig. 10-2 projected up to year 2010 shows
the number of components/chip vs. time (year). The bold arrowhead line shows the average trend line
in the figure.
Figure 10-3 shows the drop in feature size projected up to the year 2010. The bold arrowhead line
shows the average trend line in the figure.

10-3 TYPES OF INTEGRATED CIRCUITS

10-3-1 Monolithic IC
In the monolithic IC the entire circuit is built into a single piece of semiconductor chip, which
consists of active and passive components. The most commonly used integrated circuits,
microprocessors, memories, etc., are all monolithic.

10-3-2 Hybrid IC
In hybrid IC the electronic circuit is generally integrated in the ceramic substrate using various
components and then enclosed in the single package. Therefore, the hybrid IC consists of several
monolithic ICs connected by metallic interconnects mounted on a common substrate. Hybrid
integrated circuits simultaneously form an electrical, mechanical and thermal bond.
Hybrid IC technology bonds various substrates either at the die level or at the wafer level. This
technology streamlines the connections between different semiconductor chips by replacing wire
bonding. This process achieves an accelerated, streamlined and less costly process. Hybrid IC
allows increase in communication bandwidth and facilitates higher system yield.

10-4 ADVANTAGES AND DISADVANTAGES OF INTEGRATED CIRCUITS

The advantages of integrated circuits are as follows:

1. Small in size due to the reduced device dimension

2. Low weight due to very small size
3. Low power requirement due to lower dimension and lower threshold power requirement
4. Low cost due to large-scale production
5. High reliability due to the absence of a solder joint
6. Facilitates integration of large number of devices
7. Improves the device performance even at high-frequency region

The research and development in the field of IC technology is going on in different parts of the world
but still there are several limitations. The disadvantages of integrated circuits are as follows:

1. IC resistors have a limited range

2. Generally inductors (L) cannot be formed using IC
3. Transformers cannot be formed using IC

10-5 SCALE OF INTEGRATION

Historically, the first semiconductor IC chips held one diode/transistor. Advancement of technology
enabled us to add more and more transistors. The first to arrive was small-scale integration (SSI),
then improvements in technique led to devices with hundreds of logic gates—large-scale integration
(LSI). Present day microprocessors have millions of logic gates and transistors. Intel co-founder,
Gordon E. Moore, in 1965 published a paper on the future projection of IC technology. Moore’s Law
is responsible for “smaller, cheaper and more efficient IC”. Gordon Moore’s empirical relationship
is cited in a number of forms, but its essential thesis is that the number of transistors that can be
manufactured on a single die will double every 18 months. The Moore’s low representation of
number of components per chip versus year is shown is Fig. 10-2.

10-5-1 Types of IC Chips

Analog
Analog chips are small transistor count precision circuits. Amplifiers, filters, sensors, etc. fall into
this category.

ASIC or application specific integrated circuits

The development in the fabrication of IC’s has enabled us to create powerful circuits in nano devices.
ASIC brings a lot more of functionality into the same area. These are IC’s that are created for specific
purposes—each device is created to do a particular job. The common application area for this is
Digital Signal Processing—signal filters, image compression, etc.
 SoC or systems on a chip
These are highly complex mixed signal circuits (digital and analog all on the same chip). A network
processor chip or a wireless radio chip is an example of a SoC. The planar technology for IC
fabrication consists of the following processes:

1. Crystal growth of the wafer

2. Epitaxial growth
3. Oxidation
4. Photolithography
5. Etching
6. Diffusion
7. Ion implantation
8. Metallization
9. Testing and packaging

10-6 CRYSTAL GROWTH AND WAFER PREPARATION

Crystal growth and wafer preparation is the most fundamental step in device fabrication. Various
crystal growth techniques are used to form the bulk crystal. One of the methods is the Czochralski
process to form silicon wafers. A small seed crystal of silicon is attached to the top of a rod and
lowered into a crucible of molten silicon to which acceptor impurities have been added. As the rod is
very slowly pulled out of the ‘melt’ under carefully controlled conditions, we find that a single p-type
or n-type crystal ingot of the order of several inches has grown, as shown in Fig. 10-4. This technique
is referred to as the Czochralski or CZ process. The ingot is subsequently sliced into round wafers to
form the substrate on which all integrated components are fabricated. One side of each wafer is
lapped and polished to eliminate surface imperfections before proceeding with the next process.

Figure 10-4 Growth of bulk silicon crystal by Czochralski method

 The crystal ingot in Fig.10-5(a) and the cylindrical Si crystal in Fig. 10-5(b) show that the crystal
is properly shaped in a cylindrical form using a diamond cutter, and ultimately the cylindrical shaped
crystal is cut into smaller pieces to form the wafer, as shown in Fig. 10-5(c).

Figure 10-5 Preparation of wafers from ingot (a) Ingot of Si (b) Cylindrical Si crystal (c) Wafer preparation

10-7 EPITAXIAL GROWTH

Epitaxy, derived from Greek epi ‘upon’ and taxis ‘arrangement’, refers to the growth of crystals on a
crystalline substrate that determines their orientation. Epitaxy involves the extension of the substrate
lattice by the overgrowth of a layer of identical material. This is known as homoepitaxy or
autoepitaxy. For example, Si on Si or Ga As on Ga As. On the other hand, if the epitaxial layer and
the substrate are chemically and often crystallo graphically different, then this is called heteroepitaxy.
For example, Si (diamond lattice) on sapphire (hexagonal) or Ga As on Si. The epitaxial process is
used to form a layer of single-crystal silicon on an existing crystal wafer of the same or different
material. Epitaxial growth is performed in a special furnace called the reactor. Silicon wafers are
inserted in the reactor and heated to a temperature of 900–1000°C. The temperature varies from
substrate to substrate. Production technology uses the hydrogen reduction of gases like silane (SiH4)
or silicon tetrachloride (SiCl4) as the source for the silicon to be grown.
Silane has two advantages. It requires a lower temperature and has a faster growth rate than silicon
tetrachloride.
The chemical reaction for the hydrogen reduction of SiCl4 is:

And that for SiH4 is:

For example, an n-type epitaxial layer, typically from few nanometre to few micrometre thick, is
grown into a p-type substrate having resistivity of approximately few Ω-cm, corresponding to NA =
1.4 × 1015 atoms/cm3.
Since epitaxial growth requires the production of epitaxial films of impurity concentrations, it is
essential to introduce impurities, such as phosphine (PH3) for n-type doping or diborane (B2H6) for
p-type doping into the SiCl4-hydrogen gas stream. The reactor consists of a long cylindrical quartz
tube encircled by a radio-frequency induction coil and allows precise impurity control for the
production of an epitaxial layer. The silicon wafers are loaded on a rectangular graphite rod called
boat. The boat is inserted into the reactor and the graphite is heated to a temperature above 1500°C.
The temperature is raised keeping in mind that the melting point of Si is 1420°C. A control console
permits the introduction and removal of various gases required for the growth of suitable epitaxial
layers. As a result, it is possible to form an almost abrupt step p–n junction as shown in Fig. 10-6.

Figure 10-6 Epitaxial growth on Si wafer

10-8 OXIDATION FOR ISOLATION

Silicon technology has the natural ability to grow an oxide layer on the silicon surface, as shown in
Fig. 10-7. SiO2 as a passivating layer has the following characteristics:

Figure 10-7 Growth of oxide layer

1. The impurities that are used to dope the silicon do not penetrate the silicon dioxide. Thus, when used with the masking
techniques, selective doping of specific regions of the chip is accomplished.
2. It is capable of being etched by hydrogen fluoride (HF) to which the underlying silicon is impervious.

Thermal oxidation of silicon is achieved in the presence of water vapour; this process is called wet
oxidation. The chemical reaction for this process is:

Si + 2H2O → SiO2 + 2H2

Dry oxidation of oxygen:

Si + O2 → SiO2
The thickness of the oxide layers is generally in the order of 0.02 μm to 2 μm; the specific value
selected depends on the barrier required to prevent dopant penetration. Process temperature, impurity
concentration, and processing time are several of the factors that influence the thickness of the SiO2
layer. The outer silicon dioxide layer is obtained by chemical vapour deposition (CVD).

10-9 PHOTOLITHOGRAPHY FOR PATTERN TRANSFER

Photolithography is the optical process of transferring geometric shapes on a mask to the surface of a
silicon wafer. The steps for the photolithographic process are: photo resist coating, soft-baking, mask
alignment, UV exposure and development, and hard-baking. The process for the formation of a thin
uniform layer of viscous liquid photo resist on the wafer surface is shown in Fig. 10-8(a). In the
starting of the photolithographic process, the wafer is coated with a uniform film of a photosensitive
emulsion. The photo resist is slightly hardened by soft-baking and then selectively removed by
projection of UV light through mask. The monolithic fabrication technique requires the selective
removal of the insulator layer of SiO2 to form openings through which impurities can be diffused.

Figure 10-8(a) Wafer on a spinner and photo resist

There are two types of photo resists used—positive and negative photo resist [see Fig. 10-8(b)].
For positive resists, the resist is exposed with UV light. Exposure to the UV light changes the
chemical structure of the resist and it becomes more soluble in the developer. The developer solution
washes the exposed resist part, forming windows on the substrate. The mask contains an exact copy
of the pattern which is to be transferred on the wafer surface.
The behaviour of the negative resists is just the opposite of the positive photo resist. When the
negative resist is exposed to the UV light it becomes polymerized, which is not possible to dissolve.
Negative photo resist masks contain the inverse of the pattern to be transferred on the surface of
substrate. The developer solution removes only the unexposed portions and the negative resist
remains on the surface wherever it is exposed.
The photo resist coatings become photosensitive, or image-able, only after soft-baking. Soft-baking
is performed during which almost all of the solvents are removed from the photo resist coating.
Under-soft-baking will prevent light from reaching the sensitizer. This under-soft-baked positive
resist is then readily attacked by the developer in both exposed and unexposed areas, causing less
etching resistance. Over-soft-baking will degrade the photosensitivity of resists by either reducing the
developer solubility or actually destroying a portion of the sensitizer.

Figure 10-8(b) Photolithography processes using negative and positive photo resist

10-9-1 Mask Alignment and UV Exposure

The most important and complicated step in the photolithography process is mask alignment. In
general, photo-mask is a plastic or glass plate with a pattern of emulsion. The mask is aligned on the
top surface of the wafer, so that the pattern can be transferred on it. Once the mask has been
accurately aligned with the pattern on the wafer’s surface, the photo resist is exposed through the
pattern on the mask with a high intensity ultraviolet light. There are three primary exposure methods.

Contact printing
In this technique the resist-coated silicon wafer is brought into physical contact with the photo-mask,
as shown in Fig. 10-8(c). The wafer is held on a vacuum system. The system is exposed with UV light
from the top of the mask as the wafer is in contact position with the mask. As the photo resist and the
mask are in direct contact, a high resolution is possible in contact printing. But the disadvantage with
contact printing is that the dust trapped between the resist and the mask can damage the mask and
cause defects in the pattern. As the photo-mask is in direct contact with photo resist it cannot be
reused.
 Figure 10-8(c) Contact printing

Proximity printing
This technique is almost similar to contact printing technique except that a small (10–15 μm) gap is
maintained between the mask and the wafer [see Fig. 10-8(d)]. It is very important to note that the gap
minimizes, but may not eliminate the damage to the mask.

Figure 10-8(d) Proximity printing

Projection printing
Projection printing is the most advanced technique, it avoids mask damage. An image of the patterns
on the mask is projected onto the resist-coat which is a certain height away as shown in Fig. 10-9. To
achieve high resolution only a small portion of the mask is imaged. This small region image field is
scanned over the surface of the wafer. Projection printers that step the mask image over the wafer
surface are called step-and-repeat systems having several nano-metre resolution.
Figure 10-10 (a) shows response curves for negative and positive resist after the exposure and
development.
 The negative resist is completely soluble in the developer solution at low-exposure energies. As
the exposure is increased above a threshold energy more of the resist film remains after development.
For positive resists, the resist solubility in its developer is finite even at zero-exposure energy. The
solubility gradually increases until, at some threshold, it becomes completely soluble. These curves
are affected by all the resist processing variables: initial resist thickness, pre-bake conditions,
developer chemistry, developing time, and others.

Figure 10-9 Projection printing

Figure 10-10(a) Resist exposure characteristics of the negative and positive photo resist
 Figure 10-10 Photolithography process (b) Masking and exposure to UV radiation (c) Development (d) Etching for desired pattern

Hard-baking is the final and the important step in the photolithographic process. This step is
essential in order to harden the photo resist and improve adhesion of the photo resist to the wafer
surface. A large black-and-white layout of the desired pattern openings is prepared, and then reduced
photographically. This negative of the required dimensions is placed as a mask over the photo resist,
as shown in Fig. 10-10(b). By exposing the emulsion to ultraviolet light through the mask, the photo
resist becomes polymerized under the transparent regions of the mask. The mask is now removed, and
the wafer is developed using a chemical (such as trichloroethylene), which dissolves the unexposed,
i.e., unpolymerized portions of the photo resist film, and leaves a surface pattern [see Fig. 10-10(c)].
The emulsion, which was not removed in development, is now fixed, so that it becomes resistant to
the corrosive etches used next [see Fig. 10-10(d)].
Those portions of SiO2 which are protected by the photo resist are unaffected by the acid as shown
in Fig. 10-10(c). After diffusion of impurities, the resist mask is removed (stripped) with a chemical
solvent (such as hot H2SO4) coupled with a mechanical abrasion process. A negative photo resist is
used in the process described above. Positive photo resist is also employed in which the exposed
portion of the polymer is washed away and thus, the unexposed material is retained. The remaining
processing steps are identical, and independent of the type of photo resist used.
Mask design for photolithographic process is an art. The designing of a photographic mask
involves complicated and expensive processes. After the circuit layout has been determined, a large-
scale drawing is made showing the locations of the openings to be etched in the SiO2 for a particular
process step. Invariably, chip layout is obtained by computer-aided design. The drawing is made to a
magnified scale of about 1000:1, and results in dimensions more easily managed by a drafter.
The composite drawing of the circuit is partitioned into several levels called masking levels, used
in fabricating the chip. For example the gate patterns for the MOS/CMOS devices are on one level,
the source and drain contact windows on another level. Today’s computer-driven optical-pattern
generators convert the patterns into digital information and transfer the geometric layout of the chip
onto a photosensitive glass plate.
The smallest features that can be formed by the photolithographic process are limited by a
wavelength of UV light. Electron beams have much smaller wavelengths than optical radiation, and
are capable of defining much smaller areas. A narrow electron beam scans a mask covered with an
electron-sensitive resist and the pattern is written on the mask with the scanning controlled by a
computer.

10-10 ETCHING FOR DESIGN

Etching selectively removes layers of SiO2, metals, and poly-silicon, according to the desired
patterns delineated by the resist. The two major methods of etching are wet chemical etching or dry
etching. The windows are created by the photolithographic process and subsequent etching process in
the desired pattern implemented by the masking process is shown in Fig. 10-11.

Figure 10-11 Etching of selected section

10-10-1 Wet Chemical Etching

Wet etching is accomplished by partial submersion of the wafer in an acid bath having some definite
concentration. Etching solutions are housed in a temperature-controlled baths. The baths are usually
equipped with ventilation or a slotted exhaust at the back of the etch station. Vertical laminar-flow
hoods are generally used to supply uniformly-filtered air to the top surface of the etch baths. The
difficulty of the wet etching is that the chemicals enter just below the photo resists and etch more
regions below the feature size and sometimes damage the devices with unnecessary extra etching.
Common etching solutions are given in Table 10-1.

Table 10-1 Common etching solutions

Materials to Etch Etchants

Silicon
Polycrystalline Silicon (Si)
Silicon Dioxide (SiO2)
Silicon Nitride (Si3N4)
Hydrofluoric, nitric, acetic acids and iodine
Potassium hydroxide
Ethylene diamine
Buffered oxide etch (BOE) – Hydrofluoric acid and ammonium fluoride
BOE, ethylene glycol, monomethyl ether
Hydrofluoric acid and nitric (P-etch) acid
Phosphoric and hydrofluoric acid

CVD Oxide or Pad Etch Ammonium fluoride, acetic and hydrofluoric acids
Metals
Aluminium (Al) Phosphoric, nitric, acetic and hydrochloric acids
Ceric ammonium nitrate and nitric acid
Chromium/Nickel (Cr/Ni)
Hydrochloric and nitric acids (aqua regia)
Hydrochloric and nitric acids (aqua regia)
Potassium iodide (KI)
Gold (Au) Potassium cyanide (KCN) and hydrogen peroxide (H2O2)
Ferric chloride (FeCl3) and hydrochloric acid

Ferric nitrate (FeNO3) and ethylene glycol

Silver (Ag)
Nitric acid

10-10-2 Dry Chemical Etching

Dry processing effectively etches desired layers through the use of gases, using either, a chemically
reactive gas, or through physical bombardment of argon atoms. Dry etching is commonly used due to
its ability to better control the etching process and decrease contamination levels.

10-10-3 Chemical Plasma Etching

Plasma etching systems have been developed that can effectively etch silicon, silicon dioxide, silicon
nitride, aluminium, gold, glass, etc. The barrel or cylindrical, and the parallel plate or planar are the
two kinds of plasma etching reactor systems are generally used. The typical reactor consists of a
vacuum reactor chamber made usually of aluminium, glass, or quartz. A radiofrequency (RF) energy
source is used to activate fluorine-based or chlorine-based gases, which act as etchants. Wafers are
loaded into the chamber, a pump evacuates the chamber, and the reagent gas is introduced in the
chamber. The RF energy ionizes the gas and forms the etching plasma, which reacts with the wafers.

Figure 10-12 Plasma etching system

Physical bombardment
Plasma or sputter etching process is the physical technique involving ion impact and energy transfer.
In a glow-discharge environment the wafer to be etched is attached to a negative electrode. The
dislocation of the surface atom occurs due to the positive argon ions bombarded on the wafer surface.
An RF energy source provides the power in the system as shown in Fig.10-12.

10-10-4 Ion Beam Etching

Ion beam etching is similar physical etching processes which use a beam of low-energy ions to
remove material. By an electrical discharge the ion beam is extracted from an ionized gas such as
argon or argon/oxygen or plasma. An electrical discharge creates an ion plasma with the energy of a
few hundred electron volts.

10-10-5 Reactive Ion Etching

Reactive ion etching (RIE) is a combination of chemical and physical etching. During RIE, a wafer is
placed in a chamber with an atmosphere of chemically reactive gas either CF4 or CCl4 at a low
pressure. The ions strike the wafer surface vertically.

10-11 DIFFUSION FOR DOPING

Diffusion is a process of introduction of impurities into the substrate layer in the planar process. The
introduction of controlled impurity concentrations is performed in a diffusion furnace at a temperature
of about 1000°C over several hours for silicon substrate. The diffusion oven accommodates few
wafers in a quartz carrier inside a quartz tube. The temperature must be controlled carefully so that it
becomes uniform over the entire hot zone of the furnace. Impurity sources may be gases, liquids, or
solids. Gaseous impurities used are generally the hydrides of boron, arsenic, and phosphorus. An
inert gas (nitrogen) transports the impurity atoms to the surface of the wafers where they diffuse into
the wafer substrate.

Figure 10-13 Cross section of an IC transistor (a) Idealized (b) Actual

The cross-sectional diagrams with diffusion are shown in Fig. 10-13(a). When a window is
opened in the SiO2 impurities are introduced, they will laterally diffuse the same distance vertically.
Hence, the impurity will spread out under the passivating oxide surface layer. The junction profiles
should be drawn more realistically in this case, as shown in Fig.10-13(b).

10-12 ION IMPLANTATION FOR DOPING

Ion implantation is the most widely used technique to introduce dopant impurities into
semiconductors. The ionized particles are accelerated through an electrical field and targeted at the
semiconductor wafer. In a vacuum, a beam of appropriate ions, like phosphorus for n-type or boron
for p-type, are accelerated by energies between several hundreds of keV as shown in Fig. 10-14. The
depth of penetration of these ions in the substrate is determined by the accelerating energy, the beam
current, and the concentration of dopant ions.

Figure 10-14 Ion Implantation process in a vacuum chamber

This process is used wherever thin layers of doped silicon are required—the channel in a
MOSFET, the emitter region of a BJT, and the gate region of a JFET. Ion implantation process is
specially designed for such narrow regions; it permits the controlled doping concentrations than
diffusion. The SiO2 passivation layer forms an effective barrier against implanted ions, so that only
the photo-lithographically defined regions are doped.
A second and the most important advantage of ion implantation is that it is performed at low
temperatures. As a result, previously implanted regions have a lesser tendency for lateral spreading.
The third advantage of the ion-implantation process is that both the beam current and the accelerating
potential are electrically controlled outside of the apparatus in which the implantation occurs.
 Figure 10-15(a) Metallization for different contact points

Figure 10-15(b) Metallization for contact points for an n–p–n transistor

10-13 METALLIZATION FOR INTERCONNECTION

The metallization process is used to form the contacts and interconnections of the components on the
devices/chips. These are formed by the deposition of a thin layer of good conducting pure metal like
aluminium or gold over the selected surface of the chip using a metallic mask. The metallization is
performed in a high vacuum (~10−6 milibar) enclosure in order to avoid oxidation. Metal deposition
is achieved by high-vacuum evaporation inside a bell jar. The metal (aluminium or gold) is heated
until it vaporizes, and the gaseous molecules formed uniformly radiate in all directions and cover the
wafer surface. A metal mask with a definite pattern is used to define the connection pattern between
the components, and the unwanted metal is etched and removed. The metal connection with wire bond
is shown in Fig. 10-15(a).
Metal connection in semiconductor layer of a transistor emitter, base and collector region is shown
in Fig. 10-15(b).

10-14 TESTING FOR RELIABILITY

After all the fabrication processes are done successfully, the semiconductor device is tested
thoroughly through the different characterization processes. IC’s are fabricated by the batch process,
so some of the IC may not perform according to standard. An electronic tester presses tiny probes
against the chip to check its functional property; for example, checking of truth table for digital logic
gates. ICs are often designed with “self testability features” for example, built-in self-test (BIST) for
speed testing. These processes reduce test costs and time. The standard checking can be done by the
reliability testing process by an IC tester.

10-15 PACKAGING PROTECTION

The last step of this process is packaging. Packaging is done according to the dimension of the
product type, and the requirements of the manufacturer. The wafer is certified then the wafer is broken
into small individual dies. Small wires are bonded to connect pads to the external connection pins.
The most common packaging is dual input packaging or DIP, mostly used in digital IC. Pin grid array
(PGA) and leadless chip carrier (LCC) packages are used in modern VLSI design. After testing and
packaging, the product is sent to the market for sale.

10-16 IC SYMBOLS

The standard symbols of different types of IC like passive components, active components and logic
gates are shown in Fig. 10-16.
 Figure 10-16 Standard IC symbols

10-17 FABRICATION STEPS FOR DIFFERENT CIRCUITS

10-17-1 Fabrication of Resistors in Integrated Circuits

Resistors in IC can be made by the base diffusion method. The resistor is made up of a p-layer within
one n-type island or the reverse, as shown in Fig. 10-17.

Figure 10-17 Resistor in IC

Here p+ diffusions are useful for low value resistors to form the ohmic contact. The value of
resistance can be changed by changing the length and width, i.e., the dimension of the device, and the
resistivity of the diffused material. Resistance values can vary from a few ohms to kilo ohms by the
diffusion technique; tolerance of the resistor value is very poor, about 30% approximately. Thin film
resistors which have reduced space are used in order to get high value resistors.

where, ρ is the resistivity, l = length and A = area.

Resistance value depends on l, A and ρ. The drawback for these resistors is substantial parasitic
junction capacitance, which causes a lot of problems for high frequency operations. In MOS devices
the poly-silicon layer on the oxide is used as an improved useful resistor, since the thin layer
provides a better surface area matching, and hence more accurate resistor ratio.

Difference between ohomic contact and Schottky contact

Both ohomic contact and Schottky contact are types of metal-semiconductor contact. Schottky diode
or contact is a metal-semiconductor diode or contact having characteristics similar to a p–n junction.
When the metal is deposited directly on the semiconductor surface, the Schottky contact is produced.
The fabrication structure is shown in Fig. 10-18.

Figure 10-18 Schottky contact

The direct metal-semiconductor contact produces a contact potential barrier known as Schottky
barrier. This barrier produces the rectifying behaviour. Thus, the Schottky barrier diode is designed.
In case of ohomic contact the metal is not directly deposited on the semiconductor surface. Instead of
that a high doped layer (either n+ or p+) is placed between the semiconductor and the metal to make
the gradual change in barrier potential. So, there is no rectifying behaviour.
The junction of the metal semiconductor, the same metal-doped layer, produces a linear behaviour,
i.e., ohomic behaviour. The junction that follows ohm’s law, i.e., linear nature in I–V characteristics
forms an ohmic contact (see Fig. 10-19).
 Figure 10-19 Ohomic contact

The n+ region is formed with highly doped Al; the same metal is used for metallic contact.

The applications of Schottky contact

Electron availability is very high in the metal as the Schottky diode is made with the directly
deposited metal on semiconductor surface. Therefore, the Schottky diode is a majority carrier device.
As the time of injection of the electrons from conduction band to metal decreases, the switching
becomes faster. This diode has low reverse and forward impedances. So, it is used in high-speed
switching devices.

10-17-2 Steps of Fabrication of Capacitors

In ICs, capacitors are fabricated using the depletion region capacitance of a reverse-bias p–n
junction, or by MOS structure. In case of junction capacitance, the magnitude depends on the
dimension and type of the junction, and the applied bias. A depletion capacitance can be formed using
MOS structure. A parallel plate capacitor is obtained by MOS technique.
A pair of n+ layers is deposited to form source (S) and drain (D), as shown in Fig. 10-20. A thin
silicon dioxide (SiO2) layer acts as the dielectric layer. The heavily doped n-region and the Al layers
act as the two plates of the capacitor. The magnitude of the capacitance is generally very small, in the
order of picofarad.

Figure 10-20 Capacitor on IC

10-17-3 Steps of Fabrication of the Transistor Circuit

A step-by-step process will now be followed for the fabrication of a transistor circuit, as shown in
Figs. 10-21(a) and 10-21(b).
Step I: On the p-type substrate a layer of n-type semiconductor is formed. However, in the oxidation
process a thin layer of SiO2 is formed for isolation.
Step II: Photolithographic process using UV ray source is shown in Fig. 10-21(c). The optical mask
of a desired pattern is placed in between UV source and the Kodak photo resist (KPR). The mask
consists of a dark pattern. The UV ray, which is allowed to fall on the selected region, becomes solid
polymerized; other unexposed regions remain liquid, which are then removed.
Step III: The p+ diffusion at the window region is done by ion implantation technique or by chemical
deposition, as shown in Fig. 10-21(d).
Step IV: Again, to form a p-region within an n-region, another set of masks are used, and the second
step of photolithography is performed, as shown in Fig. 10-21(e).

Figure 10-21(a) Transistor circuit

Figure 10-21(b) Epitaxial layer growth and oxidation

Figure 10-21(c) Photolithography process

 Figure 10-21(d) Etching process

Figure 10-21(e) Second level of photolithography and doping

Figure 10-21(f) Third level of doping

Figure 10-21(g) Multilevel pholithography

Figure 10-21(h) Metal interconnections for different contact points

Step V: The third-level mask is used to get the pattern, as shown in Fig. 10-21(f). Multiple types of
masks and subsequent photolithography is done to achieve the desired complicated circuit.
Step VI: Before metallization, the metal mask of the desired pattern is used. In the mask, the blank
space is kept where we want to go for metallization [see Fig. 10-21(g)].
Step VII: Metal interconnections for different contact points are used, as shown in Fig. 10-21(h). The
metallization is performed at a very low pressure, at about 10‒6 forr. Special pumps are used to
achieve low pressure and O2 free environment in order to avoid oxidation. Total metallization is
preformed in a closed chamber and the room should be clean. High pure gold or Al is used for
metallization. Purity is 99.9999% and the cost of the metal is very high.

Solved Examples

Example 10-1 Fabricate the circuit, as shown in the following diagram.

Solution:
In the circuit shown in the diagram, two diodes are connected back to back with a common p-type.
Oxidation is done on the p–n layer, where p is the substrate.

Step I: Oxidation is done on the p–n layer, where p is the substrate.

Step II: Photolithography is performed using UV source.

Step III: After photolithography the desired window region is achieved, and the remaining SiO2 is
removed by chemical etching.
Step IV: In the window region, p+ ions are doped for the following desired pattern. By doping, a p+
region isolated of the n-region can be achieved.

Step V: Using the metal masking, subsequent metallization is performed at a very low pressure in
order to avoid oxidation.

Thus, the desired pattern is achieved in these steps.

Example 10-2 Fabricate the circuit, as shown in the following diagram.

Solution:
Two front-to-front connected diodes are given in the circuit, as shown in the diagram.
Step I: The n-type layer is grown on the p-type substrate.
Step II: By wet or dry oxidation, the SiO2 layer is grown on top of the n-type layer.

Step III: Photolithography is performed using mask.

Step IV: The SiO2 layer is removed by chemical or wet etching.

Step V: After removing the oxide layer, the p-type impurity within the window region is doped.

Step VI: Metallization is performed to get the contact points 1, 2 and 3. Terminals 1 to 2 form one
diode, and 2 to 3 form another diode placed front-to-front.
Example 10-3 Draw the cross-sectional diagram of the circuit, as shown in the following diagram.

Solution:
The given diagram shows a transistor circuit. The following diagram shows the cross sectional view
of the transistor.
 10-17-4 The Schottky Diode
In Fig. 10-22, terminal 1 forms the ohmic contact, because Al is deposited on the n+ region and not on
the n− region, but terminal 2 forms the Schottky contact. The Schottky contact together with the two
terminals forms the Schottky diode

10-17-5 Schematic Diagram of a CMOS Circuit

CMOS or complimentary MOS consists of nMOS and pMOS. Figure 10-23(a) shows the CMOS
circuit.
Figure 10-23(b) shows that one nMOS and one pMOS are placed on a common substrate. It looks
like two tubs are placed on a same base. The source, gate and drain are indicated by S, G and D
respectively.
The CMOS circuit contains both nMOS and pMOS; it is either nMOS or pMOS for a complete
cycle of input signal and it is operated for either a +ve or a − ve cycle. Therefore, the CMOS is ON
for both the half-cycles. With the help of twin-tub method, a complete CMOS can be realized.

Figure 10-22 Cross-sectional view of a Schottky diode

Figure 10-23(a) CMOS circuit

 Figure 10-23(b) Cross sectional view of twin tub CMOS

10-18 REAL-LIFE APPLICATIONS

In our daily life integrated circuits are applied everywhere. In addition to their wide use in computers
and mobile phones, ICs are mostly used in optoelectronic devices—LED, LASER, modulator,
demodulator, set-top box, etc. Even a calling bell uses an IC with music encoded in it. Solar cells are
very popular as an alternative source of energy. They are also very popular in the photovoltaic
industry today. These also use IC chips.
Since the early 1990s, many new electronic materials have been incorporated into silicon CMOS
transistors for enhancing their device performance and efficiency. This trend will continue, and it is
expected that more non-silicon-based materials will be incorporated into CMOS transistors and
integrated onto the silicon substrate in future technology nodes. With the advent of new fabrication
techniques, 90 nm, 65 nm and 45 nm device fabrication is possible. This lower dimension technology
starts a new era of small and powerful devices and also makes technology integration possible. For
example, we were not happy with mobile phones equipped only with voice service, but nowadays
cell phones come with numerous features—camera, music, radio, bluetooth, etc. This technology
integration is possible due to the advancement in fabrication and chip-processing technology. We are
looking forward for many more advanced features as time progresses.

POINTS TO REMEMBER

1. In monolithic circuits, the entire circuit is built into a single piece of semiconductor chip consisting of passive and active
components; physical properties of the semiconductor determine performance of the circuit.
2. Hybrid integrated circuits are devices that apply standard semiconductor processing technology to individual ICs, and fuse them
together to simultaneously form an electrical, mechanical, and thermal bond.
3. Hybrid integrated circuit offers a new a paradigm in integrated circuit and system designs and architectures by permitting:
a. Increase in communication bandwidth
b. Modular chip design process
c. Higher system yields with more reliability
4. Integrated circuits have the following advantages:
a. Small in size due to the reduced device dimension
b. Low weight due to very small size
c. Low power requirement due to lower dimension and lower threshold power requirement
d. Low cost due to large-scale production
5. The Czochralski process is used to grow ingot and subsequently to design the wafer.
 6. The epitaxial process is used to form a layer of single-crystal silicon on an existing crystal wafer of the same or different
material.
7. Thermal oxidation of silicon is achieved in the presence of water vapour; this process is called wet oxidation.
8. The process for pattern definition by applying thin uniform layer of viscous liquid photo resist on the wafer surface is the
photolithography process.
9. The composite drawing of the circuit is partitioned into several levels called masking levels, used in fabricating the chip.
10. Etching is the process of removing the unwanted portion of the layer or region from the surface during the fabrication process.
Etching can be of two types:
a. Dry etching
b. Chemical etching
11. Diffusion of impurities into substrate layer is the basic step in the planar process.
12. The ionized particles are accelerated through an electrical field and targeted at the semiconductor wafer.
13. The metallization process is used to form the interconnections of the components on the chip.
14. IC testing is performed before packaging.

OBJECTIVE QUESTIONS

1. Monolithic IC consists of:

a. Active components
b. Passive components
c. Both active and passive components
d. None of the above
2. In monolithic IC:
a. Performance depends on the substrate
b. Performance does not depend on the substrate
c. Performance depends on interconnects
d. Performance depends on packaging
3. Oxidation is used for:
a. Isolation
b. Interconnection
c. Doping
d. None of the above
4. Doping means:
a. Addition of impurity material in semiconductor band structure
b. Removing of impurity material in semiconductor band structure
c. Cleaning the surface
d. None of the above
5. Metallization is used for:
a. Interconnection
b. Protection
c. Packaging
d. None of the above
6. Packaging is used for:
a. Protection
b. Safety
c. Both (a) and (b)
d. None of the above
7. Testing is used for:
a. Checking reliability
b. Quality control
c. Both (a) and (b)
d. None of the above
8. Optical masking is used for:
 a. Pattern transfer
b. Protection
c. Cleaning
d. None of the above
9. Etching is used for:
a. Selective removal of the unwanted surface
b. Cleaning
c. Interconnection
d. None of the above
10. System on chip means:
a. It consists of both analog and digital IC
b. It consists of only analog IC
c. It consists of only digital IC
d. None of the above
11. Advantages of IC are:
a. Small size
b. Low cost
c. High packing density
d. None of the above
12. Inductor design in an IC:
a. Is not possible
b. Is possible
c. Is possible with discrete components
d. None of the above

REVIEW QUESTIONS

1. What is an IC? Explain its application in modern life.

2. Classify the different types of IC. Explain their uses.
3. What is the difference between Ohomic contact and Schottky barrier contact?
4. Explain the process of crystal growth.
5. Explain Moore’s law.
6. Classify different types of oxidation process. Explain each process in detail.
7. What is photolithography?
8. Classify different types of photolithographic processes and explain their working principle in detail.
9. What are the differences between positive and negative mask?
10. What are the differences between dry etching and wet etching?
11. Explain the process of ion implantation.
12. Explain the process of metallization.
13. Explain the impact of the use of IC in modern life.

PRACTICE PROBLEMS

1. Draw the schematic diagram of a MOS transistor.

2. Draw the schematic diagram of a bipolar junction transistor.
3. Draw the schematic diagram of fabrication of a diode with a resistance in series.
4. Draw the schematic diagrams of CMOS circuit.

SUGGESTED READINGS
1. Singh, J. 1994. Semiconductor Devices: An Introduction. New York, NY: McGraw-Hill.
2. Streetman, B.G. and S. Banerjee. 2000. Solid State Electronic Devices. New Delhi: Pearson Education.
3. Millman, Jacob and Christos C. Halkias. 1986. Integrated Electronics: Analog and Digital Circuits and Systems. New
Delhi: McGraw Hill Book Company.
4. Pierret, R. F and G.W. Neudeck. 1989. Modular Series on Solid State Devices. Boston, M.A.: Addison Wesley.
5. Gandhi, S. K. 2002. VLSI Fabrication Principles. New Delhi: Wiley & Sons.
6. Singh, B. P. and Rekha Singh. 2006. Electronic Devices and Integrated Circuits. New Delhi: Pearson Education.