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DLD
DLD
Duty Cycle - The ratio of the pulse width (time when the signal is high) to
the period (complete cycle) of a digital waveform, expressed as a
percentage.
Soln:
(a) The period T is measured from the edge of one pulse to the
corresponding edge of the next pulse.
1 1
(b) f = = = 100 Hz
𝑇 10 𝑚𝑠
𝑡𝑤 1 𝑚𝑠
(c) Duty Cycle = x 100% = x 100% = 10%
𝑇 10 𝑚𝑠
RP:
A periodic digital waveform has a pulse width of 25 μs and a period of
150 μs. Determine the frequency and the duty cycle.
𝑡𝑤 25 μ𝑠
(c) Duty Cycle = x 100% = x 100% = 16.67 %
𝑇 150 μ𝑠
Soln:
1 1
(a)T = = = 1 μs
𝑓 1 𝑀𝐻𝑧
It takes 1 μs to transfer each bit in the waveform. The total transfer
time for 8 bits is 8 x 1 μs = 8 μs
(b) The parallel transfer would take 1 μs for all eight bits.
RP:
If binary data are transferred on a USB at the rate of 480 million bits per
second (480 Mbps), how long will it take to serially transfer 16 bits?
480 x 1000000 b = 1 s
16 b = ?
-8
= 16 / 480 x 1000000 = 3.33 x 10
(*signed number ⇒ + → 0
⇒- →1
binary number ရဲ ့ရှေ့ဆုံးကကောင်ကိုပြောင်း)
Soln:
+39 ⇒ 32 + 4 + 2 + 1
5 2 1 0
2 +2 +2 +2
00100111
- 39 ⇒ 10100111 Binary Number(Sign magnitude)
⇒ 11011000 1’s complement (*sign bit ကိုထည့်မစဥ်းစား)
⇒ 11011000
+ 1
——————
11011001 2’s complement
Soln:
+19 ⇒ 16 + 2 + 1
4 1 0
2 +2 +2
00010011
- 19 ⇒ 10010011 Binary Number(Sign magnitude)
⇒ 11101100 1’s complement
⇒ 11101100
+ 1
——————
11101101 2’s complement
0 0 0 1 0 1 1 1
16 4 2 1 = +23\
7 6 5 4 3 2 1 0
b. 11101000 ⇒ - 2 2 2 2 2 2 2 2
1 1 1 0 1 0 0 0
-128 64 32 8 = -24
(* -24 ⇒ 1’s complement
- ထွက်တဲကေ
့ ာင်ကို 1 ပေါင်းပေးရတယ် signed number မလို့ )
-24 + 1 = -23
1 0
a. E516 = (E x 16 ) + (5 x 16 ) = (14 x 16) + (5 x 1) = 22910
3 2 1 0
b. B2F816 = (B x 16 ) + (2 x 16 ) + (F x 16 ) + (8 x 16 )
3 2
= (11 x 16 ) + (2 x 16 ) + (15 x 16) + (8 x 1)
= 4581610
40
= 2.5 → 0.5 x 16 =8 =8
16
2
= 0.125 → 0.125 x 16 = 2 = 2
16
28A (Hexadecimal)
2591
= 161.9375 → 0.9375 x 16 = 15 = F
16
161
= 10.0625 → 0.0625 x 16 = 1 = 1
16
10
= 0.625 → 0.625 x 16 = 10 = A
16
A1F (Hexadecimal)
a. 8416 - 2A16
2A16 = 00101010
b. C316 - 0B16
0B16 = 00001011
(*1’s complement of 0B16 = 11110100)
The output X is HIGH when all inputs are LOW as shown in the timing
diagram.
[*
Soln:
Soln:
Soln:
(a)
(b)
(c)
Soln:
Soln:(*The simplified output is 4 input )
= A+B+C+D
Soln: