Analysis of Copper Treatments and the Effects on Signal Propagation

Steven G. Pytel1,2, Paul G. Huray2, Stephen H. Hall1, Richard I. Mellitz1,Gary Brist1,

Harry M. Meyer III3, Larry Walker3, and Marc Garland3
1
Intel Corporation, Columbia, South Carolina, 29210, USA
spytel@ansoft.com
2
University of South Carolina, Columbia, South Carolina, 29208, USA
3
Oak Ridge National Laboratory, Oak Ridge, Tennessee, 37830, USA

ABSTRACT
As computer data rates increase into the 30 – 50 Gb/s
range fundamental material challenges emerge that make it
difficult to design a robust electrical interconnect between the
transmitter and receiver. This paper discusses the effects of
differing copper treatments and the effects these treatments
have on signal propagation for a computer electrical
interconnect. Two types of treatments have been studied: high
profile copper (HPC) and low profile copper (LPC).
Discussions on the physical surface geometry and elemental Figure 1: Basic copper foil is produced by the electrodeposition of
analyses of these copper types along with their signaling Cu ions from a CuSO4 acid bath onto a relatively smooth Cathode
effects are discussed below. by rotating the drum. Copper on the Matte (solution) side exhibits
larger grain boundaries than copper on the Shiny (Drum) side.
I. INTRODUCTION
Above 3 Gb/s electrical interconnect losses become
heavily dependent on fundamental physical characteristics
such as dipole relaxation in dielectrics [1, 2, 3, and 4] and
surface roughness effects on the conductor. This work focuses
on increased losses due to copper roughness variations caused
by copper surface treatments such as electrodeposition, acid
baths, grain boundary etching, and metal passivation to
inhibit corrosion.
Surface treatments are commonly applied to copper foils
prior to printed circuit board manufacturing to help promote
reliable dielectric - copper interfaces. This interface can be
subjected to severe mechanical and thermal stresses that Figure 2: Post treatment of basic copper foil after the fabrication
causes adhesion breakdown and in severe cases lifting of process shown in Figure 1.
copper traces from the dielectric or electrical opens in the
circuit path. Morgan hypothesized the cause for this additional loss
Different profile surfaces are typically produced by the was based on the analytical assumption of a rough surface
electrodeposition of small copper “anchor nodules” on the compared to a perfectly smooth metal surface with
matte side (side adjacent to the CuSO4 bath) or to the shiny conductivity equal to that of the bulk metal [5]. He studied
side (side adjacent to the Cathode drum). The general process two-dimensional cases that assumed the roughness consisted
for an electrodeposited foil is shown in Figure 1. The copper of infinitely long grooves parallel to or normal to the current
foil characteristics can be modified by changing the flow. Three geometrical shapes studied by Morgan were
revolution rate of the drum and by controlling the applied square, rectangular, and equilateral triangle grooves. Huray et
potential between the anode and cathode. al. have developed a theoretical three-dimensional analysis
Surface treatments are then added to one of these two based upon the experimental studies and analysis of this
sides by a post treatment process as shown in Figure 2. paper [6] that further supports some of Morgan’s hypotheses
and extends the range of application to 100 GHz.
II. PREVIOUS ELECTRICAL LOSS STUDIES III. ELECTRON MICROSCOPY
Samuel P. Morgan published the first study on conductor Two Scanning Electron Microscopes (SEMs) were
surface roughness losses by using a numerical solution to employed for this work. Images were captured using three
Maxwell’s equations using a 2-D surface distortion model and types of electron microscope detectors: a Backscattered
determined that at 10 GHz current flow transverse to periodic Electron (BSE) detector, a Secondary Electron (SE) detector,
structures could increase loss by up to 100% and if the and an Auger Electron Spectroscopy detector.
current flow was parallel the losses could increase by up to The first set of experiments captured the cross-section of
33% [5]. several six layer test boards created for analysis using BSE

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and SE detectors (FR4 and Isola 620). The next experiment
scanned several different copper foils using BSE and SE
detectors. These images were taken at different depths
dependent on the energy level of the accelerating voltage (5
kV – 25 kV). A Hitachi S-3400N SEM was used for these
measurements.
The final experiments used a Phi 680 Auger Nanoprobe
SEM to determine the surface profile and elemental
composition of the various copper samples. AES very
accurately determines the surface layer composition by
measuring the emitted Auger electrons spectrograph.
ideally smooth plane was approximately 12 µm. Figure 5
shows backscattered SEM images (a – d) and a SE SEM
image (e) of high profile copper foil; Figure 5 (e) shows on
average that the smallest electrodeposited geometrical shape
is a “snowball” with a diameter of approximately 40 nm (400
Angstroms). This figure provided the inspiration for the 3D
power absorption approach and model created by Huray Et al
[6].

50 µm
Generation of an Auger electron requires at minimum three
electrons to be ejected from an atom’s shell therefore
Hydrogen and Helium atoms cannot be detected using this
technique. RF sputtering with Argon ions removes surface
layer atoms producing a depth profile of the sample.

IV. COPPER ANALYSIS

A. Scanning Electron Microscopy
Figure 4: Backscattered image of the upper microstrip shown in
Six layer test boards with microstrip and stripline Figure 3 detailing the high profile copper surface.
structures were fabricated using different dielectrics (FR4 and
ISOLA 620) along with different copper profiles (high profile
and low profile) were examined.

200 µm

Figure 5: High profile copper foil at (a)1,000x, (b)5,000x,

(c)10,000x, (d)25,000x, and (c)100,000x times magnification at a
32° offset angle.

Gold
Nickel
Figure 3: Six layer test board using with high profile copper
Phosphorous
50 µm

protected by a soldermask on FR4 was analyzed using BSEs.

Figures 3 – 5 show backscattered SEM images of high

profile copper as a copper foil (Figure 5) and in a PCB stack
up (Figures 3 and 4). These images are representative of
copper that has been grown by electrodeposition. From the
cross-section images the largest divergence of copper from an Figure 6: Backscattered SEM image of low profile copper on FR4
with electroless nickel and gold used for corrosion resistance.

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20 µm
Figure 7: Backscattered SEM image of low profile copper microstrip
on FR4 using a soldermask for corrosion resistance.
Figure 8: Low profile copper foil at (a)1,000x, (b)5,000x,
(c)10,000x, and (d)25,000x times magnification at a 32° offset
angle.
Figure 9: Low profile copper foil at (a)1,000x, (b)5,000x,
(c)10,000x, and (d)25,000x times magnification at a 32° angle.
Figure 6 shows low profile copper foil with a soldermask
and Figure 7 without a soldermask using gold, electroless
nickel coating for corrosion prevention while Figure 8 shows
a 32˚ offset angle SEM of the untreated side of the low profile
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foil under various magnifications. Note the corrosion
inhibitor layer of Gold and the electroless nickel does not
evenly coat the microstrip. Further analysis shows that the
electroless nickel is composed of three molecules: nickel, a
nickel phosphorous compound, and pure phosphorous. This is
a result of poor growth in the corrosion inhibitor layer and
may contribute to higher losses in microstrip structures that
undergo this process.
In contrast to the high profile copper shown in the
previous figures (12 µm maximum divergence) the low
profile copper has a maximum divergence of approximately 4
µm from an idealized smooth plane.
V. MEASURED ELECTRICAL LOSS OF ROUGH
SURFACES
Analyzing the loss associated with the different foil types
shows an increase in insertion loss between the high profile
copper and low profile copper microstrips (1” stripline boards
were not created for this experiment). The measurement data
shown in Figures 10 and 11 were taken using Model 50A-
GSG-250 GGB PicoprobesTM on an Agilent E8364B PNA.
These measurements show an increase in the insertion loss for
a very short length (1 inch). At 40 GHz there is approximately
3 dB more loss in high profile copper compared to low profile
copper. Similar measurements taken on Isola 620 for
microstrip and stripline structures of single-ended and
differential transmission lines all yield greater loss. All traces
on the PWB were routed at a 10 degree angle to minimize any
potential differences due to fiber weave.
S21 (dB) One Inch Microstrip Comparison
0
Low Profile
))
-4
-8
Copper
High Profile
( (
-12
Copper
-16
0 5 10 15 20 25 30 35 40 45 50
freq, GHz
Figure 10: Comparison of insertion loss for one inch microstrips
fabricated on FR4 that are 4 mils wide and 2 mils high.
Similar frequency domain measurements for five and
seven inch stripline structures fabricated on Isola 620 were
performed and are shown in Figure 11. These copper traces
have a nominal width of 4 mils and nominal height of 2 mils.
They are actually trapezoidal in shape similar to the traces
depicted in Figure 4 Frequency domain measurements
provide significant insight into the electrical characteristics of
the system interconnect, however these measurements alone
are not sufficient, additional information from the time
domain is necessary to determine if timing margins will be
satisfied.
The impact of the increased losses due to surface
roughness can easily be seen by looking at a single 30 Gb/s
pulse in the time domain.
Simulations using measured s-parameters from 7 inch, 4
mil wide microstrip traces on FR4 show significant voltage
reduction (40 mV) at 30 Gb/s (15 GHz) when HPC is used
compared to LPC (observation from the simulation also
shows 30 ps of delay). As data rates continue to scale higher
silicon design becomes more complex and this margin plays a
significant role for operating systems.

HPC 5” & 7”
LPC 5” & 7”

Figure 14: Seven inch stripline fabricated from HPC on Isola 620
simulated at 10 Gb/s.
Figure 11: Comparison of IL for 5 inch and 7 inch striplines
fabricated on Isola 620 that are 4 mils wide and 2 mils high.

Figure 15: Seven inch stripline fabricated from LPC on Isola 620
simulated at 10 Gb/s.

The comparison at 10 Gb/s yields slight differences in eye

magnitude and eye height between the two copper types (~
Figure 12: Time domain comparison of HPC and LPC 7” long 4 mil
wide microstrip on FR4 at 30 Gb/s. 2.5 ps and ~ 22.7 mV).

VI. NUMERICAL SIMULATION COMPARISONS

To determine the effects that surface roughness losses
including inter-symbol interference (ISI) have in the time
domain, circuit simulations using the QuickEye analysis
option within Ansoft’s Designer™ with Nexxim™ was
utilized. These simulations used a 5 ps rising and falling edge
rate into the measured s-parameter files with a pseudo-
random maximal length bit sequence (215 – 1) which results
in 32,767 data bits being simulated. To gain insight into the
ISI effects of surface roughness two bit rates were assumed
30 Gb/s (unit interval, UI = 33. 3 ps) and 10Gb/s (UI = 100 Figure 16: Seven inch stripline fabricated from HPC on Isola 620
simulated at 30 Gb/s.
ps). The schematic is shown below.

Figure 13: Schematic for 10 and 30 Gb/s simulations.

The 10 Gb/s (5 Ghz) data rate was chosen because it is

representative of today’s high end data rates and is utilized in
the IEEE 802.3ap Ethernet standard. The masks are held
constant for the 10 Gb/s (Figures 14 and 15) simulations and
the 30 Gb/s (Figures 16 and 17) simulations to show the Figure 17: Seven inch stripline fabricated from LPC on Isola 620
differences from copper surface roughness. simulated at 30 Gb/s.

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 However the differences at 30 Gb/s become quite
significant resulting in an eye width difference of
approximately 7.8 ps and eye height of approximately 47.5
mV. A visual representation of the differences is easily made
by comparing the respective masks for each simulation.
Another increasingly common way to interpret signaling
data is analyzing it in the statistical domain. This results in a
Bit Error Ratio (BER, often called Bit Error Rate). This is the
number of interpreted errors per the number of data bits. The
x-axis is defined in UI (Eye Width = Bit Rate • UI) and the y-
axis is defined in BER. A third dimension is Eye Height and
is selected when defining the “Bathtub Curve”. Plots
comparing the BER of the different copper foils were created
using the VerifEye analysis within Ansoft’s Designer™ with
Nexxim™. Many bus standards commonly accept a BER of
1x10-12 as the minimum passing criteria for high speed
differential signaling. The differences between HPC and LPC
are significant for a BER of 1x10-12 when the bathtub curve
was plotted for an eye magnitude of 240 mV. This results in
an eye width of 23 ps for HPC and 54 ps for LPC at a data
Figure 20: Sputter profile of high profile copper.
rate of 10 Gb/s.
Within approximately 250 nm of the high profile copper
foil are numerous impurities that affect the electrical
HPC conductivity of the conductor. A large concentration of zinc is
LPC present for nearly 250 nm which is most likely due to the
passivation of the metal. Passivation of the conductor is
intentionally performed to provide a corrosion barrier at the
surface of the metal. This passivation barrier is an alloy of
copper and zinc commonly referred to as “Brass”. Depending
∆UI ≅.23 ∆UI ≅.54 on the concentration of zinc in the alloy, the brass electrical
conductivity will change. However, increased zinc
concentration lowers the electrical conductivity and according
to the International Annealed Copper Standard (IACS) brass
Figure 18: Bathtub curve comparison for LPC and HPC at an eye is only 28% as conductive as copper [7]. This is significant
magnitude of 240 mV. because the skin depth of a 10 GHz signal in copper is .67 µm
and 1.23 µm for brass that is 28 % as conductive as copper.
VII. AUGER ELECTRON SPECTROSCOPY This means that at a minimum 20% of the current is flowing
Compositional analysis performed on the high profile in a conductor with a much higher resistivity. At 30 GHz up
copper shows nitrogen, oxygen, silicon, and zinc impurities to 33% of the current is flowing within the brass surface (skin
all within 250 nm of the surface. depth of brass at 30 GHz ~ 710 nm). Finally at 100 GHz up to
65% of the current is flowing in the brass surface (skin depth
SEM Before Sputtering SEM After Sputtering of brass at 100 GHz ~ 390 nm). This passivation of copper
significantly contributes to the losses as frequencies continue
to scale. There are also significant concentrations of oxygen,
o1
o2 o1
o2
nitrogen, and silicon that potentially form oxide layers as
thick as 50 nm on the surface of the conductor.
Copper post treatment for creating HPC and LPC yield
o3 o3
significantly different amounts of Brass. LPC showed a brass
10/13/06 20.0keV 5.0kX 5.0 µm 10/13/06 20.0keV 5.0kX 5.0 µm
layer of approximately 75 nm which is significantly less than
Atomic Concentration Table
Area C N O Si Cu Zn
Atomic
Area
Concentration Table
C Cu the HPC.
1 44.45 6.96 19.89 20.80 1.94 5.96 1 26.37 73.63
2
3
43.67 7.61
42.81 7.66
20.84
22.41
19.44
19.95
1.68
1.34
6.76
5.82
2
3
13.89
20.65
86.11
79.35
This work has not attempted to separate out differing loss
Figure 19: Atomic concentrations of elements located on the surface effects caused by surface roughness and brass deposition; it
of the high profile copper before and after sputtering. simply characterized all loss as a function of copper surface
roughness. A study is currently underway to distinguish the
loss mechanisms separately and is left for a future
publication.

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 brass layer has varying thicknesses depending on the copper
Low Profile Copper processing. Another key finding was potential silicon oxide
and silicon nitride layers formed on the surface of the copper
which also act to impede current flow. This work assumed all
additional losses were due to the increased copper roughness
and work is currently underway to determine the individual
loss contributions for roughness, brass, and silicon dioxide…
will be reported on in a future publication.

IX. ACKNOWLEDGMENTS
Research measurements at ORNL sponsored by the
Assistant Secretary for Energy Efficiency and Renewable
Energy, Office of FreedomCAR and Vehicle Technologies, as
part of the High Temperature Materials Laboratory User
Program, Oak Ridge National Laboratory, managed by UT-
Battelle, LLC, for the U.S. Department of Energy under
contract number DE-AC05-00OR22725.
The University of South Carolina would like to
acknowledge the generous contributions of software it has
received from Ansoft Corporation.
Figure 21: Sputter profile of low profile copper. X. REFERENCES
[1] P.G. Huray, S.G. Pytel, R.I. Mellitz, and S.H. Hall,
VIII. CONCLUSION “Dispersion Effects from Induced Dipoles”, 10th Annual
An analysis of two copper foil types and cross-sections of IEEE SPI Proceedings, Berlin, Germany, May 9-12, 2006,
boards fabricated from FR4 and Isola 620 has been pp 213-216.
performed. These results show post surface treatments [2] P.G. Huray, F. Popoola, S.G. Pytel, R.I. Mellitz, D. Hua,
produce significantly different boundaries that promote better and S.H. Hall, “Response Function from Induced Dipoles
adhesion between the conductor and dielectric, but degrade above 10 GHz”, IEEE SoutheastCon 2007, Richmond,
the electrical performance by increasing insertion loss and Virginia, March 22 – 25, 2007, Accepted for Publication.
causing smaller eye openings. [3] S.G. Pytel, G. Barnes, D. Hua, A. Moonshiram, G. Brist,
A summary of the loss between different copper foil types R.I. Mellitz, S.H. Hall, and P.G. Huray, “Dielectric
is shown below. It compares the results in the frequency, time, Modeling and Characterization up to 40 GHz”, 11th
and statistical domains. This information provides a guide Annual IEEE SPI Proceedings, May 13 – 16, 2007,
that allows the design engineer the ability to properly Submitted for Publication.
construct a high speed serial system interconnect. [4] A.R. Djordjevic, R.M. Biljic, V.D. Likar-Smiljanic, T.K.
Sarkar, “Wideband Frequency-Domain Characterization of
FR-4 and Time-Domain Causality,” IEEE Transactions on
Statistical
Frequency Domain EMC, V. 43, n4, November 2001, pp 662 – 667.
Common to All Time Domain
Domain EH=240mV
BER=1x10
-12 [5] S.P. Morgan, “Effect of Surface Roughness on Eddy
Current Losses at Microwave Frequencies”, Journal of
Applied Physics, V. 20, pp 352 – 362, 1949.
Data
Cu Length F IL EH EW EW
Foil
K
(in) (GHz) (dB)
Rate
(mV) (ps) (ps) [6] P.G. Huray, S.G. Pytel, S.H. Hall, F. Oluwafemi, R.I.
(Gb/s)
Mellitz, D. Hua, and P. Ye, “Fundamentals of a 3-D
HPC
Isola
7 10 -8.6 10 294 90 23
“Snowball” Model for Surface Roughness Power Losses”,
620
Isola - 11th Annual IEEE SPI Proceedings, May 13 – 16, 2007.
HPC 7 20 30 28 11 8
620 15.0 [7] “Electrical Conductivity of Materials,” [Online document
Isola
HPC
620
7 30 -21 N/A N/A N/A N/A
cited 2007 February 25], Available HTTP:
LPC
Isola
620
7 10 -7.4 10 317 93 54 http://www.kp44.org/ftp/ElectricalConductivityOfMaterial
LPC
Isola
7 20
-
30 76 19 18
s.php
620 13.0
Isola -
LPC 7 30 N/A N/A N/A N/A
620 18.0

Table 1: Summary of loss results for HPC and LPC.

AES has shown that copper surfaces are passivated with a

zinc solution that forms up to a 250 nm brass boundary which
results in reduced electrical conductivity. This becomes a
significant loss mechanism above 10 GHz (20% of current is
flowing through a reduced conductivity layer). However, this

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