GAZI UNIVERSITY

Microprocessors Laboratory EEE306

(Lab 6 Report)

Abdullah Bilgin
181110017

Instructors
Prof. Dr. HASAN ŞAKİR BİLGE
Arş. Gör. ORHAN BARIŞ GANGAL
 İNİTİALİZE SECTİON:

; GPIO base addresses of port D and E

gpioDbase EQU 0x4005B000 ; inp

gpioEbase EQU 0x4005C000 ; out

; GPIO offsets, least significant 8 bits (mostly)

gpioData EQU 0x000 ; 'data' add relevant gpio data mask offset for masking, to
read or write all values add 0x3FC to base which is sum of all bit constants

gpioDir EQU 0x400 ; 'direction' 0 for inp, 1 for out, inp by default

gpioAfsel EQU 0x420 ; 'alterrnate function select' 0 for standard gpio and gpio
register used in this time, 1 for path over selected alternate hardware function, hardware function
selection is done by gpiopctl register control, 0 default

gpioPctrl EQU 0x52C ; 'port control' see documentation

gpioLock EQU 0x520 ; to unlock 0x4c4f434b shoulb be written, any other write
locks back, enables write access to gpiocr

gpioCr EQU 0x524 ; 'commit' gpioafsel, pur, pdr, den can only be changed with
setting bit in cr, only modified when unlock gpiolock

gpioAmsel EQU 0x528 ; 'analog mode select' only valid for pins of adc, set for
analog,

gpioDen EQU 0x51c ; 'digital enable'

; GPIO data mask offset constant, [9:2] in address are ussed for [7:0] bits masking

; to only write to pin 5 of any port 'five' offset should be added to gpiodata

; to only write to pins 2 and 5 of any port data should be written dataregister address + 'two'+'five'
offset address remainings left unchange in output 0 in input mode

gpioDataZero EQU 0x004

gpioDataOne EQU 0x008

gpioDataTwo EQU 0x010

gpioDataThree EQU 0x020

gpioDataFour EQU 0x040

gpioDataFive EQU 0x080

gpioDataSix EQU 0x100

gpioDataSeven EQU 0x200

; NVIC (ENn) nested vectored interrupt controller- interrupt set enable registers activate to handle
exceptions of relavent sources

nvicBase EQU 0xE000E000 ; base addr followings are offsets

nvicEN0 EQU 0x100 ; for interrupts 0-31, set 1 relavent to activate

interrupt, by default 0 all

nvicEN1 EQU 0x104 ; for interrupts 32-63

nvicEN2 EQU 0x108 ; for interrupts 64-95

nvicEN3 EQU 0x10C ; for interrupts 96-113

; GPIO Interrupt registers, least significant 8 bits (mostly)

gpioIs EQU 0x404 ; 'interrupt sense' 1 for level sensitivity, 0 for edge sensitivity,
default 0 all

gpioIbe EQU 0x408 ; 'interrupt both edges' if 1 regardless of gpioie register

interrupt occur for both edge, if 0 gpioie register define which edge, default 0 all

gpioIev EQU 0x40C ; 'interrupt evet' 1 for rising edge, 0 for falling edge, 0 default

gpioIm EQU 0x410 ; 'interrupt mask' 1 to send interrupt to interrupt controller, 0

default

gpioRis EQU 0x414 ; 'raw interrupt status' read only, set automatically if
interrupt occur if gpioim is set interrupt sent is to interrupt controller, if level detectin signal must be
held until serviced, if edge write 1 to gpioicr to erase relavent gpioris, gpiomis is the masked value of
gpioris

gpioMis EQU 0x418 ; 'masked interrupt status' readonly, if 1 sent to

interrupt controller, if 0 no interrupt or masked

gpioIcr EQU 0x41C ; 'interrupt clear' for edge sensitivity write 1 clears gpiomis
and gpioris, no effect on level detect, no effect writing 0

; GPIO Pad control registers

gpioDr2r EQU 0x500 ; '2ma drive select' if select dr4r, dr8r cleared automatically,
all set default

gpioDr4r EQU 0x504

gpioDr8r EQU 0x508 ; used for high current applications

gpioOdr EQU 0x50C ; 'open drain select' set for open drain, if set
corresponding gpioden bit should also be set, gpiodr2r, 4r,8r, gpioslr should be used for desired fall
time, if pin is imput no effect
gpioPur EQU 0x510 ; 'pullup select' set to add 20k ohm pullup, if set gpiopdr
automatically cleared, write access protected by gpiocr register

gpioPdr EQU 0x514 ; 'pulldownselect'

gpioSlr EQU 0x518 ; 'slew rate sontrol select' available only when 8ma strength
used

; GPIO clck gating register

; default 0 and disabled by clck blocking

; bit #0 for port A and #1 for port B should be set to enable ports

; after setting 3 clck cycle is needed to reach port registers properly

rcgcgpio EQU 0x400FE608

DataAddr EQU 0x20000400

fastDelayData EQU 0XABCD

slowDelayData EQU 0X4C0000

gpioDataMsk EQU 0x3FC

AREA INIT , CODE, READONLY

EXPORT initializegpio

initializegpio

; enable clck for port D, E

LDR R1, =rcgcgpio

LDR R0, [R1]

ORR R0, R0, #0x18

STR R0, [R1]

NOP

NOP

NOP

; direction port E (out)

LDR R1, =gpioEbase

ADD R1, R1, #gpioDir

LDR R0, [R1]

ORR R0, R0, #0x3F

STR R0, [R1]

; afsel E Base

LDR R1, =gpioEbase

ADD R1, R1, #gpioAfsel

LDR R0, [R1]

BIC R0, #0xFF

STR R0, [R1]

LDR R1, =gpioDbase

ADD R1, R1, #gpioAfsel

LDR R0, [R1]

BIC R0, #0xFF

STR R0, [R1]

; den 1 for D and E port

LDR R1, =gpioDbase

ADD R1, R1, #gpioDen

LDR R0,[R1]

ORR R0, R0, #0xFF

STR R0, [R1]

LDR R1, =gpioEbase

ADD R1, R1, #gpioDen

LDR R0,[R1]

ORR R0, R0, #0xFF

STR R0, [R1]

; interrupt mask for portD 2nd pin

LDR R1,=gpioDbase

ADD R1,#gpioIm

LDR R0,[R1]
 ORR R0,#2

STR R0,[R1]

; interrupt rising edge for portD 2nd pin

LDR R1,=gpioDbase

ADD R1,#gpioIbe

LDR R0,[R1]

ORR R0,#2

STR R0,[R1]

; NVIC for portD

LDR R1,=nvicBase

ADD r1,#nvicEN0

LDR R0,[R1]

ORR R0,R0,#0x8

STR R0,[R1]

BX LR

ALIGN

END

; GPIO base addresses of port D and E

gpioDbase EQU 0x4005B000 ; inp

gpioEbase EQU 0x4005C000 ; out

gpioAbase EQU 0x40058000

; GPIO offsets, least significant 8 bits (mostly)

gpioData EQU 0x000 ; 'data' add relevant gpio data mask offset for masking, to
read or write all values add 0x3FC to base which is sum of all bit constants

gpioDir EQU 0x400 ; 'direction' 0 for inp, 1 for out, inp by default

gpioAfsel EQU 0x420 ; 'alterrnate function select' 0 for standard gpio and gpio
register used in this time, 1 for path over selected alternate hardware function, hardware function
selection is done by gpiopctl register control, 0 default

gpioPctrl EQU 0x52C ; 'port control' see documentation

gpioLock EQU 0x520 ; to unlock 0x4c4f434b shoulb be written, any other write
locks back, enables write access to gpiocr

gpioCr EQU 0x524 ; 'commit' gpioafsel, pur, pdr, den can only be changed with
setting bit in cr, only modified when unlock gpiolock

gpioAmsel EQU 0x528 ; 'analog mode select' only valid for pins of adc, set for
analog,

gpioDen EQU 0x51c ; 'digital enable'

; GPIO data mask offset constant, [9:2] in address are ussed for [7:0] bits masking

; to only write to pin 5 of any port 'five' offset should be added to gpiodata

; to only write to pins 2 and 5 of any port data should be written dataregister address + 'two'+'five'
offset address remainings left unchange in output 0 in input mode

gpioDataZero EQU 0x004

gpioDataOne EQU 0x008

gpioDataTwo EQU 0x010

gpioDataThree EQU 0x020

gpioDataFour EQU 0x040

gpioDataFive EQU 0x080

gpioDataSix EQU 0x100

gpioDataSeven EQU 0x200

; NVIC (ENn) nested vectored interrupt controller- interrupt set enable registers activate to handle
exceptions of relavent sources

nvicBase EQU 0xE000E000 ; base addr followings are offsets

nvicEN0 EQU 0x100 ; for interrupts 0-31, set 1 relavent to activate

interrupt, by default 0 all

nvicEN1 EQU 0x104 ; for interrupts 32-63

nvicEN2 EQU 0x108 ; for interrupts 64-95

nvicEN3 EQU 0x10C ; for interrupts 96-113

; GPIO Interrupt registers, least significant 8 bits (mostly)

gpioIs EQU 0x404 ; 'interrupt sense' 1 for level sensitivity, 0 for edge sensitivity,
default 0 all
gpioIbe EQU 0x408 ; 'interrupt both edges' if 1 regardless of gpioie register
interrupt occur for both edge, if 0 gpioie register define which edge, default 0 all

gpioIev EQU 0x40C ; 'interrupt evet' 1 for rising edge, 0 for falling edge, 0 default

gpioIm EQU 0x410 ; 'interrupt mask' 1 to send interrupt to interrupt controller, 0

default

gpioRis EQU 0x414 ; 'raw interrupt status' read only, set automatically if
interrupt occur if gpioim is set interrupt sent is to interrupt controller, if level detectin signal must be
held until serviced, if edge write 1 to gpioicr to erase relavent gpioris, gpiomis is the masked value of
gpioris

gpioMis EQU 0x418 ; 'masked interrupt status' readonly, if 1 sent to

interrupt controller, if 0 no interrupt or masked

gpioIcr EQU 0x41C ; 'interrupt clear' for edge sensitivity write 1 clears gpiomis
and gpioris, no effect on level detect, no effect writing 0

; GPIO Pad control registers

gpioDr2r EQU 0x500 ; '2ma drive select' if select dr4r, dr8r cleared automatically,
all set default

gpioDr4r EQU 0x504

gpioDr8r EQU 0x508 ; used for high current applications

gpioOdr EQU 0x50C ; 'open drain select' set for open drain, if set
corresponding gpioden bit should also be set, gpiodr2r, 4r,8r, gpioslr should be used for desired fall
time, if pin is imput no effect

gpioPur EQU 0x510 ; 'pullup select' set to add 20k ohm pullup, if set gpiopdr
automatically cleared, write access protected by gpiocr register

gpioPdr EQU 0x514 ; 'pulldownselect'

gpioSlr EQU 0x518 ; 'slew rate sontrol select' available only when 8ma strength
used

; GPIO clck gating register

; default 0 and disabled by clck blocking

; bit #0 for port A and #1 for port B should be set to enable ports

; after setting 3 clck cycle is needed to reach port registers properly

rcgcgpio EQU 0x400FE608

fast_delaydata1 EQU 0xABCD

 AREA INTRPT, CODE

ALIGN

EXTERN checkblink

EXPORT ISRD

ISRD PROC

PUSH {LR}

BL checkblink

POP {LR}

; clear flag for further interrupts

LDR R1, =gpioDbase

ADD R1,#gpioIcr

LDR R0,[R1]

ORR R0,#2

STR R0,[R1]

BX LR

ENDP

ALIGN

AREA MAIN, CODE

ALIGN

EXTERN initializegpio

ENTRY

EXPORT __main
__main

BL initializegpio

bbb B bbb

ALIGN

END

MAİN

; GPIO base addresses of port D and E

gpioDbase EQU 0x4005B000 ; inp

gpioEbase EQU 0x4005C000 ; out

gpioAbase EQU 0x40058000

; GPIO offsets, least significant 8 bits (mostly)

gpioData EQU 0x000 ; 'data' add relevant gpio data mask offset for masking, to
read or write all values add 0x3FC to base which is sum of all bit constants

gpioDir EQU 0x400 ; 'direction' 0 for inp, 1 for out, inp by default

gpioAfsel EQU 0x420 ; 'alterrnate function select' 0 for standard gpio and gpio
register used in this time, 1 for path over selected alternate hardware function, hardware function
selection is done by gpiopctl register control, 0 default

gpioPctrl EQU 0x52C ; 'port control' see documentation

gpioLock EQU 0x520 ; to unlock 0x4c4f434b shoulb be written, any other write
locks back, enables write access to gpiocr

gpioCr EQU 0x524 ; 'commit' gpioafsel, pur, pdr, den can only be changed with
setting bit in cr, only modified when unlock gpiolock

gpioAmsel EQU 0x528 ; 'analog mode select' only valid for pins of adc, set for
analog,

gpioDen EQU 0x51c ; 'digital enable'

; GPIO data mask offset constant, [9:2] in address are ussed for [7:0] bits masking

; to only write to pin 5 of any port 'five' offset should be added to gpiodata

; to only write to pins 2 and 5 of any port data should be written dataregister address + 'two'+'five'
offset address remainings left unchange in output 0 in input mode

gpioDataZero EQU 0x004

gpioDataOne EQU 0x008

gpioDataTwo EQU 0x010

gpioDataThree EQU 0x020

gpioDataFour EQU 0x040

gpioDataFive EQU 0x080

gpioDataSix EQU 0x100

gpioDataSeven EQU 0x200

; NVIC (ENn) nested vectored interrupt controller- interrupt set enable registers activate to handle
exceptions of relavent sources

nvicBase EQU 0xE000E000 ; base addr followings are offsets

nvicEN0 EQU 0x100 ; for interrupts 0-31, set 1 relavent to activate

interrupt, by default 0 all

nvicEN1 EQU 0x104 ; for interrupts 32-63

nvicEN2 EQU 0x108 ; for interrupts 64-95

nvicEN3 EQU 0x10C ; for interrupts 96-113

; GPIO Interrupt registers, least significant 8 bits (mostly)

gpioIs EQU 0x404 ; 'interrupt sense' 1 for level sensitivity, 0 for edge sensitivity,
default 0 all

gpioIbe EQU 0x408 ; 'interrupt both edges' if 1 regardless of gpioie register

interrupt occur for both edge, if 0 gpioie register define which edge, default 0 all

gpioIev EQU 0x40C ; 'interrupt evet' 1 for rising edge, 0 for falling edge, 0 default

gpioIm EQU 0x410 ; 'interrupt mask' 1 to send interrupt to interrupt controller, 0

default

gpioRis EQU 0x414 ; 'raw interrupt status' read only, set automatically if
interrupt occur if gpioim is set interrupt sent is to interrupt controller, if level detectin signal must be
held until serviced, if edge write 1 to gpioicr to erase relavent gpioris, gpiomis is the masked value of
gpioris
gpioMis EQU 0x418 ; 'masked interrupt status' readonly, if 1 sent to
interrupt controller, if 0 no interrupt or masked

gpioIcr EQU 0x41C ; 'interrupt clear' for edge sensitivity write 1 clears gpiomis
and gpioris, no effect on level detect, no effect writing 0

; GPIO Pad control registers

gpioDr2r EQU 0x500 ; '2ma drive select' if select dr4r, dr8r cleared automatically,
all set default

gpioDr4r EQU 0x504

gpioDr8r EQU 0x508 ; used for high current applications

gpioOdr EQU 0x50C ; 'open drain select' set for open drain, if set
corresponding gpioden bit should also be set, gpiodr2r, 4r,8r, gpioslr should be used for desired fall
time, if pin is imput no effect

gpioPur EQU 0x510 ; 'pullup select' set to add 20k ohm pullup, if set gpiopdr
automatically cleared, write access protected by gpiocr register

gpioPdr EQU 0x514 ; 'pulldownselect'

gpioSlr EQU 0x518 ; 'slew rate sontrol select' available only when 8ma strength
used

; GPIO clck gating register

; default 0 and disabled by clck blocking

; bit #0 for port A and #1 for port B should be set to enable ports

; after setting 3 clck cycle is needed to reach port registers properly

rcgcgpio EQU 0x400FE608

fast_delaydata1 EQU 0xABCD

AREA INTRPT, CODE

ALIGN

EXTERN checkblink

EXPORT ISRD

ISRD PROC

PUSH {LR}
 BL checkblink

POP {LR}

; clear flag for further interrupts

LDR R1, =gpioDbase

ADD R1,#gpioIcr

LDR R0,[R1]

ORR R0,#2

STR R0,[R1]

BX LR

ENDP

ALIGN

AREA MAIN, CODE

ALIGN

EXTERN initializegpio

ENTRY

EXPORT __main

__main

BL initializegpio

bbb B bbb
 ALIGN

END

BLİNKS

; GPIO base addresses of port D and E

gpioDbase EQU 0x4005B000 ; inp

gpioEbase EQU 0x4005C000 ; out

gpioAbase EQU 0x40058000

; GPIO offsets, least significant 8 bits (mostly)

gpioData EQU 0x000 ; 'data' add relevant gpio data mask offset for masking, to
read or write all values add 0x3FC to base which is sum of all bit constants

gpioDir EQU 0x400 ; 'direction' 0 for inp, 1 for out, inp by default

gpioAfsel EQU 0x420 ; 'alterrnate function select' 0 for standard gpio and gpio
register used in this time, 1 for path over selected alternate hardware function, hardware function
selection is done by gpiopctl register control, 0 default

gpioPctrl EQU 0x52C ; 'port control' see documentation

gpioLock EQU 0x520 ; to unlock 0x4c4f434b shoulb be written, any other write
locks back, enables write access to gpiocr

gpioCr EQU 0x524 ; 'commit' gpioafsel, pur, pdr, den can only be changed with
setting bit in cr, only modified when unlock gpiolock

gpioAmsel EQU 0x528 ; 'analog mode select' only valid for pins of adc, set for
analog,

gpioDen EQU 0x51c ; 'digital enable'

; GPIO data mask offset constant, [9:2] in address are ussed for [7:0] bits masking

; to only write to pin 5 of any port 'five' offset should be added to gpiodata

; to only write to pins 2 and 5 of any port data should be written dataregister address + 'two'+'five'
offset address remainings left unchange in output 0 in input mode

gpioDataZero EQU 0x004

gpioDataOne EQU 0x008

gpioDataTwo EQU 0x010

gpioDataThree EQU 0x020

gpioDataFour EQU 0x040

gpioDataFive EQU 0x080

gpioDataSix EQU 0x100

gpioDataSeven EQU 0x200

; GPIO Interrupt registers, least significant 8 bits (mostly)

gpioIs EQU 0x404 ; 'interrupt sense' 1 for level sensitivity, 0 for edge sensitivity

gpioIbe EQU 0x408 ; 'interrupt both edges' if 1 regardless of gpioie register

interrupt occur for both edge, if 0 gpioie register define which edge, default 0 all

gpioIev EQU 0x40C ; 'interrupt evet' 1 for rising edge, 0 for falling edge, 0 default

gpioIm EQU 0x410 ; 'interrupt mask' 1 to sendt interrupt co interrupt controller,

0 default

gpioRis EQU 0x414 ; 'raw interrupt status' read only, set automatically if
interrupt occur if gpioim is set interrupt sent is to interrupt controller, if level detectin signal must be
held until serviced, if edge write 1 to gpioicr to erase relavent gpioris, gpiomis is the masked value of
gpioris

gpioMis EQU 0x418 ; 'masked interrupt status' readonly, if 1 sent to

interrupt controller, if 0 no interrupt or masked

gpioIcr EQU 0x41C ; 'interrupt clear' for edge sensitivity write 1 clears gpiomis
and gpioris, no effect on level detect, no effect writing 0

; GPIO Pad control registers

gpioDr2r EQU 0x500 ; '2ma drive select' if select dr4r, dr8r cleared automatically,
all set default

gpioDr4r EQU 0x504

gpioDr8r EQU 0x508 ; used for high current applications

gpioOdr EQU 0x50C ; 'open drain select' set for open drain, if set
corresponding gpioden bit should also be set, gpiodr2r, 4r,8r, gpioslr should be used for desired fall
time, if pin is imput no effect

gpioPur EQU 0x510 ; 'pullup select' set to add 20k ohm pullup, if set gpiopdr
automatically cleared, write access protected by gpiocr register

gpioPdr EQU 0x514 ; 'pulldownselect'

gpioSlr EQU 0x518 ; 'slew rate sontrol select' available only when 8ma strength
used
; GPIO clck gating register

; default 0 and disabled by clck blocking

; bit #0 for port A and #1 for port B should be set to enable ports

; after setting 3 clck cycle is needed to reach port registers properly

rcgcgpio EQU 0x400FE608

delayDataAddr EQU 0x20000400

fastDelayData EQU 0X0C0000

slowDelayData EQU 0X4C0000

AREA BLINK, CODE

ALIGN

EXPORT checkblink

checkblink

PUSH {LR}

; check sw

LDR R2,=1

blink

LDR R1,=gpioEbase

ADD R1,#0x04

LDR R0,[R1]

ORR R0,#0x01

STR R0,[R1]

BL delay

AND R0,#0x0

STR R0,[R1]

BL delay

SUBS R2,#1
 BNE blink

POP {LR}

BX LR

delay

LDR R8, =slowDelayData ; read

delay amount from memory

wait

SUBS R8, #1

BNE wait

BX LR

ALIGN

END