Dynamic RAM

Dynamic RAM (DRAM) is a type of random access memory used to store and access larger sets
of data than block RAM (BRAM) or look-up tables (LUTs). DRAM is not available on all FPGA
targets.
Storing data in DRAM provides the following benefits:
 Additional space for large data sets that do not fit on the FPGA in BRAM or LUTs
 Lower latency access to memory than reading directly from the host
 Dedicated memory for data logging from embedded FPGAs that are not continuously
connected to a host device
DRAM access has the following restrictions:
 Applications running on the FPGA cannot receive data from DRAM in a single clock
cycle.
 Only one command can access DRAM memory at a time because DRAM requires
sequential access.
 The sequential access required by DRAM prevents deterministic timing and may increase
execution time.
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Some of the key highlights of the clock management architecture include:

• High-speed buffers and routing for low-skew clock distribution

• Frequency synthesis and phase shifting

• Low-jitter clock generation and jitter filtering

Each Defense-grade 7 series FPGA has up to 20 clock management tiles (CMTs), each
consisting of one mixed-mode clock manager (MMCM) and one phase-locked loop (PLL).